drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 152                                               uint16_t *);
 153         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 154                                       unsigned int, unsigned int,
 155                                       unsigned int);
 156         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 157         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 158         void            (*erxo_qenable)(efx_rxq_t *);
 159         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 160                                         unsigned int, efx_rxq_type_t,
 161                                         efsys_mem_t *, size_t, uint32_t,
 162                                         efx_evq_t *, efx_rxq_t *);
 163         void            (*erxo_qdestroy)(efx_rxq_t *);
 164 } efx_rx_ops_t;
 165
 166 typedef struct efx_mac_ops_s {
 167         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 168         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 169         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 170         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 171         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 172         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 173         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 174         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 175                                                       efx_rxq_t *, boolean_t);
 176         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 177 } efx_mac_ops_t;
 178
 179 typedef struct efx_phy_ops_s {
 180         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 181         efx_rc_t        (*epo_reset)(efx_nic_t *);
 182         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 183         efx_rc_t        (*epo_verify)(efx_nic_t *);
 184         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 185 #if EFSYS_OPT_PHY_STATS
 186         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 187                                             uint32_t *);
 188 #endif  /* EFSYS_OPT_PHY_STATS */
 189 #if EFSYS_OPT_BIST
 190         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 191         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 192         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 193                                          efx_bist_result_t *, uint32_t *,
 194                                          unsigned long *, size_t);
 195         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 196 #endif  /* EFSYS_OPT_BIST */
 197 } efx_phy_ops_t;
 198
 199 #if EFSYS_OPT_FILTER
 200 typedef struct efx_filter_ops_s {
 201         efx_rc_t        (*efo_init)(efx_nic_t *);
 202         void            (*efo_fini)(efx_nic_t *);
 203         efx_rc_t        (*efo_restore)(efx_nic_t *);
 204         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 205                                    boolean_t may_replace);
 206         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 207         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 208         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 209                                    boolean_t, boolean_t, boolean_t,
 210                                    uint8_t const *, uint32_t);
 211 } efx_filter_ops_t;
 212
 213 extern  __checkReturn   efx_rc_t
 214 efx_filter_reconfigure(
 215         __in                            efx_nic_t *enp,
 216         __in_ecount(6)                  uint8_t const *mac_addr,
 217         __in                            boolean_t all_unicst,
 218         __in                            boolean_t mulcst,
 219         __in                            boolean_t all_mulcst,
 220         __in                            boolean_t brdcst,
 221         __in_ecount(6*count)            uint8_t const *addrs,
 222         __in                            uint32_t count);
 223
 224 #endif /* EFSYS_OPT_FILTER */
 225
 226
 227 typedef struct efx_port_s {
 228         efx_mac_type_t          ep_mac_type;
 229         uint32_t                ep_phy_type;
 230         uint8_t                 ep_port;
 231         uint32_t                ep_mac_pdu;
 232         uint8_t                 ep_mac_addr[6];
 233         efx_link_mode_t         ep_link_mode;
 234         boolean_t               ep_all_unicst;
 235         boolean_t               ep_mulcst;
 236         boolean_t               ep_all_mulcst;
 237         boolean_t               ep_brdcst;
 238         unsigned int            ep_fcntl;
 239         boolean_t               ep_fcntl_autoneg;
 240         efx_oword_t             ep_multicst_hash[2];
 241         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 242                                                     EFX_MAC_MULTICAST_LIST_MAX];
 243         uint32_t                ep_mulcst_addr_count;
 244 #if EFSYS_OPT_PHY_FLAGS
 245         uint32_t                ep_phy_flags;
 246 #endif  /* EFSYS_OPT_PHY_FLAGS */
 247         efx_phy_media_type_t    ep_fixed_port_type;
 248         efx_phy_media_type_t    ep_module_type;
 249         uint32_t                ep_adv_cap_mask;
 250         uint32_t                ep_lp_cap_mask;
 251         uint32_t                ep_default_adv_cap_mask;
 252         uint32_t                ep_phy_cap_mask;
 253         boolean_t               ep_mac_drain;
 254         boolean_t               ep_mac_stats_pending;
 255 #if EFSYS_OPT_BIST
 256         efx_bist_type_t         ep_current_bist;
 257 #endif
 258         const efx_mac_ops_t     *ep_emop;
 259         const efx_phy_ops_t     *ep_epop;
 260 } efx_port_t;
 261
 262 typedef struct efx_mon_ops_s {
 263 } efx_mon_ops_t;
 264
 265 typedef struct efx_mon_s {
 266         efx_mon_type_t          em_type;
 267         const efx_mon_ops_t     *em_emop;
 268 } efx_mon_t;
 269
 270 typedef struct efx_intr_ops_s {
 271         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 272         void            (*eio_enable)(efx_nic_t *);
 273         void            (*eio_disable)(efx_nic_t *);
 274         void            (*eio_disable_unlocked)(efx_nic_t *);
 275         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 276         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 277         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 278                                  boolean_t *);
 279         void            (*eio_fatal)(efx_nic_t *);
 280         void            (*eio_fini)(efx_nic_t *);
 281 } efx_intr_ops_t;
 282
 283 typedef struct efx_intr_s {
 284         const efx_intr_ops_t    *ei_eiop;
 285         efsys_mem_t             *ei_esmp;
 286         efx_intr_type_t         ei_type;
 287         unsigned int            ei_level;
 288 } efx_intr_t;
 289
 290 typedef struct efx_nic_ops_s {
 291         efx_rc_t        (*eno_probe)(efx_nic_t *);
 292         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 293         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 294         efx_rc_t        (*eno_reset)(efx_nic_t *);
 295         efx_rc_t        (*eno_init)(efx_nic_t *);
 296         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 297         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 298                                         uint32_t *, size_t *);
 299 #if EFSYS_OPT_DIAG
 300         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 301 #endif  /* EFSYS_OPT_DIAG */
 302         void            (*eno_fini)(efx_nic_t *);
 303         void            (*eno_unprobe)(efx_nic_t *);
 304 } efx_nic_ops_t;
 305
 306 #ifndef EFX_TXQ_LIMIT_TARGET
 307 #define EFX_TXQ_LIMIT_TARGET 259
 308 #endif
 309 #ifndef EFX_RXQ_LIMIT_TARGET
 310 #define EFX_RXQ_LIMIT_TARGET 512
 311 #endif
 312 #ifndef EFX_TXQ_DC_SIZE
 313 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 314 #endif
 315 #ifndef EFX_RXQ_DC_SIZE
 316 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 317 #endif
 318
 319 #if EFSYS_OPT_FILTER
 320
 321 #if EFSYS_OPT_SIENA
 322
 323 typedef struct siena_filter_spec_s {
 324         uint8_t         sfs_type;
 325         uint32_t        sfs_flags;
 326         uint32_t        sfs_dmaq_id;
 327         uint32_t        sfs_dword[3];
 328 } siena_filter_spec_t;
 329
 330 typedef enum siena_filter_type_e {
 331         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 332         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 333         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 334         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 335         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 336         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 337
 338         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 339         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 340         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 341         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 342         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 343         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 344
 345         EFX_SIENA_FILTER_NTYPES
 346 } siena_filter_type_t;
 347
 348 typedef enum siena_filter_tbl_id_e {
 349         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 350         EFX_SIENA_FILTER_TBL_RX_MAC,
 351         EFX_SIENA_FILTER_TBL_TX_IP,
 352         EFX_SIENA_FILTER_TBL_TX_MAC,
 353         EFX_SIENA_FILTER_NTBLS
 354 } siena_filter_tbl_id_t;
 355
 356 typedef struct siena_filter_tbl_s {
 357         int                     sft_size;       /* number of entries */
 358         int                     sft_used;       /* active count */
 359         uint32_t                *sft_bitmap;    /* active bitmap */
 360         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 361 } siena_filter_tbl_t;
 362
 363 typedef struct siena_filter_s {
 364         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 365         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 366 } siena_filter_t;
 367
 368 #endif  /* EFSYS_OPT_SIENA */
 369
 370 typedef struct efx_filter_s {
 371 #if EFSYS_OPT_SIENA
 372         siena_filter_t          *ef_siena_filter;
 373 #endif /* EFSYS_OPT_SIENA */
 374 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 375         ef10_filter_table_t     *ef_ef10_filter_table;
 376 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 377 } efx_filter_t;
 378
 379 #if EFSYS_OPT_SIENA
 380
 381 extern                  void
 382 siena_filter_tbl_clear(
 383         __in            efx_nic_t *enp,
 384         __in            siena_filter_tbl_id_t tbl);
 385
 386 #endif  /* EFSYS_OPT_SIENA */
 387
 388 #endif  /* EFSYS_OPT_FILTER */
 389
 390 #if EFSYS_OPT_MCDI
 391
 392 typedef struct efx_mcdi_ops_s {
 393         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 394         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 395                                         void *, size_t);
 396         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 397         boolean_t       (*emco_poll_response)(efx_nic_t *);
 398         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 399         void            (*emco_fini)(efx_nic_t *);
 400         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 401                                             efx_mcdi_feature_id_t, boolean_t *);
 402         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 403                                             uint32_t *);
 404 } efx_mcdi_ops_t;
 405
 406 typedef struct efx_mcdi_s {
 407         const efx_mcdi_ops_t            *em_emcop;
 408         const efx_mcdi_transport_t      *em_emtp;
 409         efx_mcdi_iface_t                em_emip;
 410 } efx_mcdi_t;
 411
 412 #endif /* EFSYS_OPT_MCDI */
 413
 414 typedef struct efx_drv_cfg_s {
 415         uint32_t                edc_min_vi_count;
 416         uint32_t                edc_max_vi_count;
 417
 418         uint32_t                edc_max_piobuf_count;
 419         uint32_t                edc_pio_alloc_size;
 420 } efx_drv_cfg_t;
 421
 422 struct efx_nic_s {
 423         uint32_t                en_magic;
 424         efx_family_t            en_family;
 425         uint32_t                en_features;
 426         efsys_identifier_t      *en_esip;
 427         efsys_lock_t            *en_eslp;
 428         efsys_bar_t             *en_esbp;
 429         unsigned int            en_mod_flags;
 430         unsigned int            en_reset_flags;
 431         efx_nic_cfg_t           en_nic_cfg;
 432         efx_drv_cfg_t           en_drv_cfg;
 433         efx_port_t              en_port;
 434         efx_mon_t               en_mon;
 435         efx_intr_t              en_intr;
 436         uint32_t                en_ev_qcount;
 437         uint32_t                en_rx_qcount;
 438         uint32_t                en_tx_qcount;
 439         const efx_nic_ops_t     *en_enop;
 440         const efx_ev_ops_t      *en_eevop;
 441         const efx_tx_ops_t      *en_etxop;
 442         const efx_rx_ops_t      *en_erxop;
 443 #if EFSYS_OPT_FILTER
 444         efx_filter_t            en_filter;
 445         const efx_filter_ops_t  *en_efop;
 446 #endif  /* EFSYS_OPT_FILTER */
 447 #if EFSYS_OPT_MCDI
 448         efx_mcdi_t              en_mcdi;
 449 #endif  /* EFSYS_OPT_MCDI */
 450         uint32_t                en_vport_id;
 451         union {
 452 #if EFSYS_OPT_SIENA
 453                 struct {
 454                         int                     enu_unused;
 455                 } siena;
 456 #endif  /* EFSYS_OPT_SIENA */
 457                 int     enu_unused;
 458         } en_u;
 459 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 460         union en_arch {
 461                 struct {
 462                         int                     ena_vi_base;
 463                         int                     ena_vi_count;
 464                         int                     ena_vi_shift;
 465                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 466                         uint32_t                ena_piobuf_count;
 467                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 468                         uint32_t                ena_pio_write_vi_base;
 469                         /* Memory BAR mapping regions */
 470                         uint32_t                ena_uc_mem_map_offset;
 471                         size_t                  ena_uc_mem_map_size;
 472                         uint32_t                ena_wc_mem_map_offset;
 473                         size_t                  ena_wc_mem_map_size;
 474                 } ef10;
 475         } en_arch;
 476 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 477 };
 478
 479
 480 #define EFX_NIC_MAGIC   0x02121996
 481
 482 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 483     const efx_ev_callbacks_t *, void *);
 484
 485 typedef struct efx_evq_rxq_state_s {
 486         unsigned int                    eers_rx_read_ptr;
 487         unsigned int                    eers_rx_mask;
 488 } efx_evq_rxq_state_t;
 489
 490 struct efx_evq_s {
 491         uint32_t                        ee_magic;
 492         efx_nic_t                       *ee_enp;
 493         unsigned int                    ee_index;
 494         unsigned int                    ee_mask;
 495         efsys_mem_t                     *ee_esmp;
 496 #if EFSYS_OPT_QSTATS
 497         uint32_t                        ee_stat[EV_NQSTATS];
 498 #endif  /* EFSYS_OPT_QSTATS */
 499
 500         efx_ev_handler_t                ee_rx;
 501         efx_ev_handler_t                ee_tx;
 502         efx_ev_handler_t                ee_driver;
 503         efx_ev_handler_t                ee_global;
 504         efx_ev_handler_t                ee_drv_gen;
 505 #if EFSYS_OPT_MCDI
 506         efx_ev_handler_t                ee_mcdi;
 507 #endif  /* EFSYS_OPT_MCDI */
 508
 509         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 510
 511         uint32_t                        ee_flags;
 512 };
 513
 514 #define EFX_EVQ_MAGIC   0x08081997
 515
 516 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 517
 518 struct efx_rxq_s {
 519         uint32_t                        er_magic;
 520         efx_nic_t                       *er_enp;
 521         efx_evq_t                       *er_eep;
 522         unsigned int                    er_index;
 523         unsigned int                    er_label;
 524         unsigned int                    er_mask;
 525         efsys_mem_t                     *er_esmp;
 526 };
 527
 528 #define EFX_RXQ_MAGIC   0x15022005
 529
 530 struct efx_txq_s {
 531         uint32_t                        et_magic;
 532         efx_nic_t                       *et_enp;
 533         unsigned int                    et_index;
 534         unsigned int                    et_mask;
 535         efsys_mem_t                     *et_esmp;
 536 #if EFSYS_OPT_HUNTINGTON
 537         uint32_t                        et_pio_bufnum;
 538         uint32_t                        et_pio_blknum;
 539         uint32_t                        et_pio_write_offset;
 540         uint32_t                        et_pio_offset;
 541         size_t                          et_pio_size;
 542 #endif
 543 #if EFSYS_OPT_QSTATS
 544         uint32_t                        et_stat[TX_NQSTATS];
 545 #endif  /* EFSYS_OPT_QSTATS */
 546 };
 547
 548 #define EFX_TXQ_MAGIC   0x05092005
 549
 550 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 551         do {                                                            \
 552                 (_dst)[0] = (_src)[0];                                  \
 553                 (_dst)[1] = (_src)[1];                                  \
 554                 (_dst)[2] = (_src)[2];                                  \
 555                 (_dst)[3] = (_src)[3];                                  \
 556                 (_dst)[4] = (_src)[4];                                  \
 557                 (_dst)[5] = (_src)[5];                                  \
 558         _NOTE(CONSTANTCONDITION)                                        \
 559         } while (B_FALSE)
 560
 561 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 562         do {                                                            \
 563                 uint16_t *_d = (uint16_t *)(_dst);                      \
 564                 _d[0] = 0xffff;                                         \
 565                 _d[1] = 0xffff;                                         \
 566                 _d[2] = 0xffff;                                         \
 567         _NOTE(CONSTANTCONDITION)                                        \
 568         } while (B_FALSE)
 569
 570 #if EFSYS_OPT_CHECK_REG
 571 #define EFX_CHECK_REG(_enp, _reg)                                       \
 572         do {                                                            \
 573                 const char *name = #_reg;                               \
 574                 char min = name[4];                                     \
 575                 char max = name[5];                                     \
 576                 char rev;                                               \
 577                                                                         \
 578                 switch ((_enp)->en_family) {                            \
 579                 case EFX_FAMILY_SIENA:                                  \
 580                         rev = 'C';                                      \
 581                         break;                                          \
 582                                                                         \
 583                 case EFX_FAMILY_HUNTINGTON:                             \
 584                         rev = 'D';                                      \
 585                         break;                                          \
 586                                                                         \
 587                 case EFX_FAMILY_MEDFORD:                                \
 588                         rev = 'E';                                      \
 589                         break;                                          \
 590                                                                         \
 591                 default:                                                \
 592                         rev = '?';                                      \
 593                         break;                                          \
 594                 }                                                       \
 595                                                                         \
 596                 EFSYS_ASSERT3S(rev, >=, min);                           \
 597                 EFSYS_ASSERT3S(rev, <=, max);                           \
 598                                                                         \
 599         _NOTE(CONSTANTCONDITION)                                        \
 600         } while (B_FALSE)
 601 #else
 602 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 603         _NOTE(CONSTANTCONDITION)                                        \
 604         } while (B_FALSE)
 605 #endif
 606
 607 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 608         do {                                                            \
 609                 EFX_CHECK_REG((_enp), (_reg));                          \
 610                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 611                     (_edp), (_lock));                                   \
 612                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 613                     uint32_t, _reg ## _OFST,                            \
 614                     uint32_t, (_edp)->ed_u32[0]);                       \
 615         _NOTE(CONSTANTCONDITION)                                        \
 616         } while (B_FALSE)
 617
 618 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 619         do {                                                            \
 620                 EFX_CHECK_REG((_enp), (_reg));                          \
 621                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 622                     uint32_t, _reg ## _OFST,                            \
 623                     uint32_t, (_edp)->ed_u32[0]);                       \
 624                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 625                     (_edp), (_lock));                                   \
 626         _NOTE(CONSTANTCONDITION)                                        \
 627         } while (B_FALSE)
 628
 629 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 630         do {                                                            \
 631                 EFX_CHECK_REG((_enp), (_reg));                          \
 632                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 633                     (_eqp));                                            \
 634                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 635                     uint32_t, _reg ## _OFST,                            \
 636                     uint32_t, (_eqp)->eq_u32[1],                        \
 637                     uint32_t, (_eqp)->eq_u32[0]);                       \
 638         _NOTE(CONSTANTCONDITION)                                        \
 639         } while (B_FALSE)
 640
 641 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 642         do {                                                            \
 643                 EFX_CHECK_REG((_enp), (_reg));                          \
 644                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 645                     uint32_t, _reg ## _OFST,                            \
 646                     uint32_t, (_eqp)->eq_u32[1],                        \
 647                     uint32_t, (_eqp)->eq_u32[0]);                       \
 648                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 649                     (_eqp));                                            \
 650         _NOTE(CONSTANTCONDITION)                                        \
 651         } while (B_FALSE)
 652
 653 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 654         do {                                                            \
 655                 EFX_CHECK_REG((_enp), (_reg));                          \
 656                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 657                     (_eop), B_TRUE);                                    \
 658                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 659                     uint32_t, _reg ## _OFST,                            \
 660                     uint32_t, (_eop)->eo_u32[3],                        \
 661                     uint32_t, (_eop)->eo_u32[2],                        \
 662                     uint32_t, (_eop)->eo_u32[1],                        \
 663                     uint32_t, (_eop)->eo_u32[0]);                       \
 664         _NOTE(CONSTANTCONDITION)                                        \
 665         } while (B_FALSE)
 666
 667 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 668         do {                                                            \
 669                 EFX_CHECK_REG((_enp), (_reg));                          \
 670                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 671                     uint32_t, _reg ## _OFST,                            \
 672                     uint32_t, (_eop)->eo_u32[3],                        \
 673                     uint32_t, (_eop)->eo_u32[2],                        \
 674                     uint32_t, (_eop)->eo_u32[1],                        \
 675                     uint32_t, (_eop)->eo_u32[0]);                       \
 676                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 677                     (_eop), B_TRUE);                                    \
 678         _NOTE(CONSTANTCONDITION)                                        \
 679         } while (B_FALSE)
 680
 681 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 682         do {                                                            \
 683                 EFX_CHECK_REG((_enp), (_reg));                          \
 684                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 685                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 686                     (_edp), (_lock));                                   \
 687                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 688                     uint32_t, (_index),                                 \
 689                     uint32_t, _reg ## _OFST,                            \
 690                     uint32_t, (_edp)->ed_u32[0]);                       \
 691         _NOTE(CONSTANTCONDITION)                                        \
 692         } while (B_FALSE)
 693
 694 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 695         do {                                                            \
 696                 EFX_CHECK_REG((_enp), (_reg));                          \
 697                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 698                     uint32_t, (_index),                                 \
 699                     uint32_t, _reg ## _OFST,                            \
 700                     uint32_t, (_edp)->ed_u32[0]);                       \
 701                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 702                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 703                     (_edp), (_lock));                                   \
 704         _NOTE(CONSTANTCONDITION)                                        \
 705         } while (B_FALSE)
 706
 707 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 708         do {                                                            \
 709                 EFX_CHECK_REG((_enp), (_reg));                          \
 710                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 711                     uint32_t, (_index),                                 \
 712                     uint32_t, _reg ## _OFST,                            \
 713                     uint32_t, (_edp)->ed_u32[0]);                       \
 714                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 715                     (_reg ## _OFST +                                    \
 716                     (2 * sizeof (efx_dword_t)) +                        \
 717                     ((_index) * _reg ## _STEP)),                        \
 718                     (_edp), (_lock));                                   \
 719         _NOTE(CONSTANTCONDITION)                                        \
 720         } while (B_FALSE)
 721
 722 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 723         do {                                                            \
 724                 EFX_CHECK_REG((_enp), (_reg));                          \
 725                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 726                     uint32_t, (_index),                                 \
 727                     uint32_t, _reg ## _OFST,                            \
 728                     uint32_t, (_edp)->ed_u32[0]);                       \
 729                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 730                     (_reg ## _OFST +                                    \
 731                     (3 * sizeof (efx_dword_t)) +                        \
 732                     ((_index) * _reg ## _STEP)),                        \
 733                     (_edp), (_lock));                                   \
 734         _NOTE(CONSTANTCONDITION)                                        \
 735         } while (B_FALSE)
 736
 737 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 738         do {                                                            \
 739                 EFX_CHECK_REG((_enp), (_reg));                          \
 740                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 741                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 742                     (_eqp));                                            \
 743                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 744                     uint32_t, (_index),                                 \
 745                     uint32_t, _reg ## _OFST,                            \
 746                     uint32_t, (_eqp)->eq_u32[1],                        \
 747                     uint32_t, (_eqp)->eq_u32[0]);                       \
 748         _NOTE(CONSTANTCONDITION)                                        \
 749         } while (B_FALSE)
 750
 751 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 752         do {                                                            \
 753                 EFX_CHECK_REG((_enp), (_reg));                          \
 754                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 755                     uint32_t, (_index),                                 \
 756                     uint32_t, _reg ## _OFST,                            \
 757                     uint32_t, (_eqp)->eq_u32[1],                        \
 758                     uint32_t, (_eqp)->eq_u32[0]);                       \
 759                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 760                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 761                     (_eqp));                                            \
 762         _NOTE(CONSTANTCONDITION)                                        \
 763         } while (B_FALSE)
 764
 765 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 766         do {                                                            \
 767                 EFX_CHECK_REG((_enp), (_reg));                          \
 768                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 769                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 770                     (_eop), (_lock));                                   \
 771                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 772                     uint32_t, (_index),                                 \
 773                     uint32_t, _reg ## _OFST,                            \
 774                     uint32_t, (_eop)->eo_u32[3],                        \
 775                     uint32_t, (_eop)->eo_u32[2],                        \
 776                     uint32_t, (_eop)->eo_u32[1],                        \
 777                     uint32_t, (_eop)->eo_u32[0]);                       \
 778         _NOTE(CONSTANTCONDITION)                                        \
 779         } while (B_FALSE)
 780
 781 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 782         do {                                                            \
 783                 EFX_CHECK_REG((_enp), (_reg));                          \
 784                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 785                     uint32_t, (_index),                                 \
 786                     uint32_t, _reg ## _OFST,                            \
 787                     uint32_t, (_eop)->eo_u32[3],                        \
 788                     uint32_t, (_eop)->eo_u32[2],                        \
 789                     uint32_t, (_eop)->eo_u32[1],                        \
 790                     uint32_t, (_eop)->eo_u32[0]);                       \
 791                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 792                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 793                     (_eop), (_lock));                                   \
 794         _NOTE(CONSTANTCONDITION)                                        \
 795         } while (B_FALSE)
 796
 797 /*
 798  * Allow drivers to perform optimised 128-bit doorbell writes.
 799  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 800  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 801  * the need for locking in the host, and are the only ones known to be safe to
 802  * use 128-bites write with.
 803  */
 804 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 805         do {                                                            \
 806                 EFX_CHECK_REG((_enp), (_reg));                          \
 807                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 808                     const char *,                                       \
 809                     #_reg,                                              \
 810                     uint32_t, (_index),                                 \
 811                     uint32_t, _reg ## _OFST,                            \
 812                     uint32_t, (_eop)->eo_u32[3],                        \
 813                     uint32_t, (_eop)->eo_u32[2],                        \
 814                     uint32_t, (_eop)->eo_u32[1],                        \
 815                     uint32_t, (_eop)->eo_u32[0]);                       \
 816                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
 817                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 818                     (_eop));                                            \
 819         _NOTE(CONSTANTCONDITION)                                        \
 820         } while (B_FALSE)
 821
 822 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
 823         do {                                                            \
 824                 unsigned int _new = (_wptr);                            \
 825                 unsigned int _old = (_owptr);                           \
 826                                                                         \
 827                 if ((_new) >= (_old))                                   \
 828                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 829                             (_old) * sizeof (efx_desc_t),               \
 830                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
 831                 else                                                    \
 832                         /*                                              \
 833                          * It is cheaper to sync entire map than sync   \
 834                          * two parts especially when offset/size are    \
 835                          * ignored and entire map is synced in any case.\
 836                          */                                             \
 837                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 838                             0,                                          \
 839                             (_entries) * sizeof (efx_desc_t));          \
 840         _NOTE(CONSTANTCONDITION)                                        \
 841         } while (B_FALSE)
 842
 843 extern  __checkReturn   efx_rc_t
 844 efx_nic_biu_test(
 845         __in            efx_nic_t *enp);
 846
 847 extern  __checkReturn   efx_rc_t
 848 efx_mac_select(
 849         __in            efx_nic_t *enp);
 850
 851 extern  void
 852 efx_mac_multicast_hash_compute(
 853         __in_ecount(6*count)            uint8_t const *addrs,
 854         __in                            int count,
 855         __out                           efx_oword_t *hash_low,
 856         __out                           efx_oword_t *hash_high);
 857
 858 extern  __checkReturn   efx_rc_t
 859 efx_phy_probe(
 860         __in            efx_nic_t *enp);
 861
 862 extern                  void
 863 efx_phy_unprobe(
 864         __in            efx_nic_t *enp);
 865
 866 #if EFSYS_OPT_DIAG
 867
 868 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
 869
 870 typedef struct efx_register_set_s {
 871         unsigned int            address;
 872         unsigned int            step;
 873         unsigned int            rows;
 874         efx_oword_t             mask;
 875 } efx_register_set_t;
 876
 877 extern  __checkReturn   efx_rc_t
 878 efx_nic_test_registers(
 879         __in            efx_nic_t *enp,
 880         __in            efx_register_set_t *rsp,
 881         __in            size_t count);
 882
 883 extern  __checkReturn   efx_rc_t
 884 efx_nic_test_tables(
 885         __in            efx_nic_t *enp,
 886         __in            efx_register_set_t *rsp,
 887         __in            efx_pattern_type_t pattern,
 888         __in            size_t count);
 889
 890 #endif  /* EFSYS_OPT_DIAG */
 891
 892 #if EFSYS_OPT_MCDI
 893
 894 extern  __checkReturn           efx_rc_t
 895 efx_mcdi_set_workaround(
 896         __in                    efx_nic_t *enp,
 897         __in                    uint32_t type,
 898         __in                    boolean_t enabled,
 899         __out_opt               uint32_t *flagsp);
 900
 901 extern  __checkReturn           efx_rc_t
 902 efx_mcdi_get_workarounds(
 903         __in                    efx_nic_t *enp,
 904         __out_opt               uint32_t *implementedp,
 905         __out_opt               uint32_t *enabledp);
 906
 907 #endif /* EFSYS_OPT_MCDI */
 908
 909 #ifdef  __cplusplus
 910 }
 911 #endif
 912
 913 #endif  /* _SYS_EFX_IMPL_H */