2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_FILTER 0x00001000
76 #define EFX_MOD_LIC 0x00002000
78 #define EFX_RESET_PHY 0x00000001
79 #define EFX_RESET_RXQ_ERR 0x00000002
80 #define EFX_RESET_TXQ_ERR 0x00000004
82 typedef enum efx_mac_type_e {
90 typedef struct efx_ev_ops_s {
91 efx_rc_t (*eevo_init)(efx_nic_t *);
92 void (*eevo_fini)(efx_nic_t *);
93 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
94 efsys_mem_t *, size_t, uint32_t,
95 uint32_t, uint32_t, efx_evq_t *);
96 void (*eevo_qdestroy)(efx_evq_t *);
97 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
98 void (*eevo_qpost)(efx_evq_t *, uint16_t);
99 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
101 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
105 typedef struct efx_tx_ops_s {
106 efx_rc_t (*etxo_init)(efx_nic_t *);
107 void (*etxo_fini)(efx_nic_t *);
108 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
109 unsigned int, unsigned int,
110 efsys_mem_t *, size_t,
112 efx_evq_t *, efx_txq_t *,
114 void (*etxo_qdestroy)(efx_txq_t *);
115 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
116 unsigned int, unsigned int,
118 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
119 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
120 efx_rc_t (*etxo_qflush)(efx_txq_t *);
121 void (*etxo_qenable)(efx_txq_t *);
122 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
123 void (*etxo_qpio_disable)(efx_txq_t *);
124 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
126 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
128 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
129 unsigned int, unsigned int,
131 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143 void (*etxo_qstats_update)(efx_txq_t *,
148 typedef struct efx_rx_ops_s {
149 efx_rc_t (*erxo_init)(efx_nic_t *);
150 void (*erxo_fini)(efx_nic_t *);
151 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
153 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
154 unsigned int, unsigned int,
156 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
157 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
158 void (*erxo_qenable)(efx_rxq_t *);
159 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
160 unsigned int, efx_rxq_type_t,
161 efsys_mem_t *, size_t, uint32_t,
162 efx_evq_t *, efx_rxq_t *);
163 void (*erxo_qdestroy)(efx_rxq_t *);
166 typedef struct efx_mac_ops_s {
167 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
168 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
169 efx_rc_t (*emo_addr_set)(efx_nic_t *);
170 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
171 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
172 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
173 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
174 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
175 efx_rxq_t *, boolean_t);
176 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
179 typedef struct efx_phy_ops_s {
180 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
181 efx_rc_t (*epo_reset)(efx_nic_t *);
182 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
183 efx_rc_t (*epo_verify)(efx_nic_t *);
184 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
186 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
187 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
188 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
189 efx_bist_result_t *, uint32_t *,
190 unsigned long *, size_t);
191 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
192 #endif /* EFSYS_OPT_BIST */
196 typedef struct efx_filter_ops_s {
197 efx_rc_t (*efo_init)(efx_nic_t *);
198 void (*efo_fini)(efx_nic_t *);
199 efx_rc_t (*efo_restore)(efx_nic_t *);
200 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
201 boolean_t may_replace);
202 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
203 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
204 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
205 boolean_t, boolean_t, boolean_t,
206 uint8_t const *, uint32_t);
209 extern __checkReturn efx_rc_t
210 efx_filter_reconfigure(
212 __in_ecount(6) uint8_t const *mac_addr,
213 __in boolean_t all_unicst,
214 __in boolean_t mulcst,
215 __in boolean_t all_mulcst,
216 __in boolean_t brdcst,
217 __in_ecount(6*count) uint8_t const *addrs,
218 __in uint32_t count);
220 #endif /* EFSYS_OPT_FILTER */
223 typedef struct efx_port_s {
224 efx_mac_type_t ep_mac_type;
225 uint32_t ep_phy_type;
228 uint8_t ep_mac_addr[6];
229 efx_link_mode_t ep_link_mode;
230 boolean_t ep_all_unicst;
232 boolean_t ep_all_mulcst;
234 unsigned int ep_fcntl;
235 boolean_t ep_fcntl_autoneg;
236 efx_oword_t ep_multicst_hash[2];
237 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
238 EFX_MAC_MULTICAST_LIST_MAX];
239 uint32_t ep_mulcst_addr_count;
240 #if EFSYS_OPT_PHY_FLAGS
241 uint32_t ep_phy_flags;
242 #endif /* EFSYS_OPT_PHY_FLAGS */
243 efx_phy_media_type_t ep_fixed_port_type;
244 efx_phy_media_type_t ep_module_type;
245 uint32_t ep_adv_cap_mask;
246 uint32_t ep_lp_cap_mask;
247 uint32_t ep_default_adv_cap_mask;
248 uint32_t ep_phy_cap_mask;
249 boolean_t ep_mac_drain;
250 boolean_t ep_mac_stats_pending;
252 efx_bist_type_t ep_current_bist;
254 const efx_mac_ops_t *ep_emop;
255 const efx_phy_ops_t *ep_epop;
258 typedef struct efx_mon_ops_s {
261 typedef struct efx_mon_s {
262 efx_mon_type_t em_type;
263 const efx_mon_ops_t *em_emop;
266 typedef struct efx_intr_ops_s {
267 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
268 void (*eio_enable)(efx_nic_t *);
269 void (*eio_disable)(efx_nic_t *);
270 void (*eio_disable_unlocked)(efx_nic_t *);
271 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
272 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
273 void (*eio_status_message)(efx_nic_t *, unsigned int,
275 void (*eio_fatal)(efx_nic_t *);
276 void (*eio_fini)(efx_nic_t *);
279 typedef struct efx_intr_s {
280 const efx_intr_ops_t *ei_eiop;
281 efsys_mem_t *ei_esmp;
282 efx_intr_type_t ei_type;
283 unsigned int ei_level;
286 typedef struct efx_nic_ops_s {
287 efx_rc_t (*eno_probe)(efx_nic_t *);
288 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
289 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
290 efx_rc_t (*eno_reset)(efx_nic_t *);
291 efx_rc_t (*eno_init)(efx_nic_t *);
292 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
293 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
294 uint32_t *, size_t *);
296 efx_rc_t (*eno_register_test)(efx_nic_t *);
297 #endif /* EFSYS_OPT_DIAG */
298 void (*eno_fini)(efx_nic_t *);
299 void (*eno_unprobe)(efx_nic_t *);
302 #ifndef EFX_TXQ_LIMIT_TARGET
303 #define EFX_TXQ_LIMIT_TARGET 259
305 #ifndef EFX_RXQ_LIMIT_TARGET
306 #define EFX_RXQ_LIMIT_TARGET 512
308 #ifndef EFX_TXQ_DC_SIZE
309 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
311 #ifndef EFX_RXQ_DC_SIZE
312 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
319 typedef struct siena_filter_spec_s {
322 uint32_t sfs_dmaq_id;
323 uint32_t sfs_dword[3];
324 } siena_filter_spec_t;
326 typedef enum siena_filter_type_e {
327 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
328 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
329 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
330 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
331 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
332 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
334 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
335 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
336 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
337 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
338 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
339 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
341 EFX_SIENA_FILTER_NTYPES
342 } siena_filter_type_t;
344 typedef enum siena_filter_tbl_id_e {
345 EFX_SIENA_FILTER_TBL_RX_IP = 0,
346 EFX_SIENA_FILTER_TBL_RX_MAC,
347 EFX_SIENA_FILTER_TBL_TX_IP,
348 EFX_SIENA_FILTER_TBL_TX_MAC,
349 EFX_SIENA_FILTER_NTBLS
350 } siena_filter_tbl_id_t;
352 typedef struct siena_filter_tbl_s {
353 int sft_size; /* number of entries */
354 int sft_used; /* active count */
355 uint32_t *sft_bitmap; /* active bitmap */
356 siena_filter_spec_t *sft_spec; /* array of saved specs */
357 } siena_filter_tbl_t;
359 typedef struct siena_filter_s {
360 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
361 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
364 #endif /* EFSYS_OPT_SIENA */
366 typedef struct efx_filter_s {
368 siena_filter_t *ef_siena_filter;
369 #endif /* EFSYS_OPT_SIENA */
370 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
371 ef10_filter_table_t *ef_ef10_filter_table;
372 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
378 siena_filter_tbl_clear(
380 __in siena_filter_tbl_id_t tbl);
382 #endif /* EFSYS_OPT_SIENA */
384 #endif /* EFSYS_OPT_FILTER */
388 typedef struct efx_mcdi_ops_s {
389 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
390 void (*emco_send_request)(efx_nic_t *, void *, size_t,
392 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
393 boolean_t (*emco_poll_response)(efx_nic_t *);
394 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
395 void (*emco_fini)(efx_nic_t *);
396 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
397 efx_mcdi_feature_id_t, boolean_t *);
398 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
402 typedef struct efx_mcdi_s {
403 const efx_mcdi_ops_t *em_emcop;
404 const efx_mcdi_transport_t *em_emtp;
405 efx_mcdi_iface_t em_emip;
408 #endif /* EFSYS_OPT_MCDI */
410 typedef struct efx_drv_cfg_s {
411 uint32_t edc_min_vi_count;
412 uint32_t edc_max_vi_count;
414 uint32_t edc_max_piobuf_count;
415 uint32_t edc_pio_alloc_size;
420 efx_family_t en_family;
421 uint32_t en_features;
422 efsys_identifier_t *en_esip;
423 efsys_lock_t *en_eslp;
424 efsys_bar_t *en_esbp;
425 unsigned int en_mod_flags;
426 unsigned int en_reset_flags;
427 efx_nic_cfg_t en_nic_cfg;
428 efx_drv_cfg_t en_drv_cfg;
432 uint32_t en_ev_qcount;
433 uint32_t en_rx_qcount;
434 uint32_t en_tx_qcount;
435 const efx_nic_ops_t *en_enop;
436 const efx_ev_ops_t *en_eevop;
437 const efx_tx_ops_t *en_etxop;
438 const efx_rx_ops_t *en_erxop;
440 efx_filter_t en_filter;
441 const efx_filter_ops_t *en_efop;
442 #endif /* EFSYS_OPT_FILTER */
445 #endif /* EFSYS_OPT_MCDI */
446 uint32_t en_vport_id;
452 #endif /* EFSYS_OPT_SIENA */
455 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
461 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
462 uint32_t ena_piobuf_count;
463 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
464 uint32_t ena_pio_write_vi_base;
465 /* Memory BAR mapping regions */
466 uint32_t ena_uc_mem_map_offset;
467 size_t ena_uc_mem_map_size;
468 uint32_t ena_wc_mem_map_offset;
469 size_t ena_wc_mem_map_size;
472 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
476 #define EFX_NIC_MAGIC 0x02121996
478 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
479 const efx_ev_callbacks_t *, void *);
481 typedef struct efx_evq_rxq_state_s {
482 unsigned int eers_rx_read_ptr;
483 unsigned int eers_rx_mask;
484 } efx_evq_rxq_state_t;
489 unsigned int ee_index;
490 unsigned int ee_mask;
491 efsys_mem_t *ee_esmp;
493 uint32_t ee_stat[EV_NQSTATS];
494 #endif /* EFSYS_OPT_QSTATS */
496 efx_ev_handler_t ee_rx;
497 efx_ev_handler_t ee_tx;
498 efx_ev_handler_t ee_driver;
499 efx_ev_handler_t ee_global;
500 efx_ev_handler_t ee_drv_gen;
502 efx_ev_handler_t ee_mcdi;
503 #endif /* EFSYS_OPT_MCDI */
505 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
510 #define EFX_EVQ_MAGIC 0x08081997
512 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
518 unsigned int er_index;
519 unsigned int er_label;
520 unsigned int er_mask;
521 efsys_mem_t *er_esmp;
524 #define EFX_RXQ_MAGIC 0x15022005
529 unsigned int et_index;
530 unsigned int et_mask;
531 efsys_mem_t *et_esmp;
532 #if EFSYS_OPT_HUNTINGTON
533 uint32_t et_pio_bufnum;
534 uint32_t et_pio_blknum;
535 uint32_t et_pio_write_offset;
536 uint32_t et_pio_offset;
540 uint32_t et_stat[TX_NQSTATS];
541 #endif /* EFSYS_OPT_QSTATS */
544 #define EFX_TXQ_MAGIC 0x05092005
546 #define EFX_MAC_ADDR_COPY(_dst, _src) \
548 (_dst)[0] = (_src)[0]; \
549 (_dst)[1] = (_src)[1]; \
550 (_dst)[2] = (_src)[2]; \
551 (_dst)[3] = (_src)[3]; \
552 (_dst)[4] = (_src)[4]; \
553 (_dst)[5] = (_src)[5]; \
554 _NOTE(CONSTANTCONDITION) \
557 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
559 uint16_t *_d = (uint16_t *)(_dst); \
563 _NOTE(CONSTANTCONDITION) \
566 #if EFSYS_OPT_CHECK_REG
567 #define EFX_CHECK_REG(_enp, _reg) \
569 const char *name = #_reg; \
570 char min = name[4]; \
571 char max = name[5]; \
574 switch ((_enp)->en_family) { \
575 case EFX_FAMILY_SIENA: \
579 case EFX_FAMILY_HUNTINGTON: \
583 case EFX_FAMILY_MEDFORD: \
592 EFSYS_ASSERT3S(rev, >=, min); \
593 EFSYS_ASSERT3S(rev, <=, max); \
595 _NOTE(CONSTANTCONDITION) \
598 #define EFX_CHECK_REG(_enp, _reg) do { \
599 _NOTE(CONSTANTCONDITION) \
603 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
605 EFX_CHECK_REG((_enp), (_reg)); \
606 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
608 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
609 uint32_t, _reg ## _OFST, \
610 uint32_t, (_edp)->ed_u32[0]); \
611 _NOTE(CONSTANTCONDITION) \
614 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
616 EFX_CHECK_REG((_enp), (_reg)); \
617 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
618 uint32_t, _reg ## _OFST, \
619 uint32_t, (_edp)->ed_u32[0]); \
620 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
622 _NOTE(CONSTANTCONDITION) \
625 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
627 EFX_CHECK_REG((_enp), (_reg)); \
628 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
630 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
631 uint32_t, _reg ## _OFST, \
632 uint32_t, (_eqp)->eq_u32[1], \
633 uint32_t, (_eqp)->eq_u32[0]); \
634 _NOTE(CONSTANTCONDITION) \
637 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
639 EFX_CHECK_REG((_enp), (_reg)); \
640 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
641 uint32_t, _reg ## _OFST, \
642 uint32_t, (_eqp)->eq_u32[1], \
643 uint32_t, (_eqp)->eq_u32[0]); \
644 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
646 _NOTE(CONSTANTCONDITION) \
649 #define EFX_BAR_READO(_enp, _reg, _eop) \
651 EFX_CHECK_REG((_enp), (_reg)); \
652 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
654 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
655 uint32_t, _reg ## _OFST, \
656 uint32_t, (_eop)->eo_u32[3], \
657 uint32_t, (_eop)->eo_u32[2], \
658 uint32_t, (_eop)->eo_u32[1], \
659 uint32_t, (_eop)->eo_u32[0]); \
660 _NOTE(CONSTANTCONDITION) \
663 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
665 EFX_CHECK_REG((_enp), (_reg)); \
666 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
667 uint32_t, _reg ## _OFST, \
668 uint32_t, (_eop)->eo_u32[3], \
669 uint32_t, (_eop)->eo_u32[2], \
670 uint32_t, (_eop)->eo_u32[1], \
671 uint32_t, (_eop)->eo_u32[0]); \
672 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
674 _NOTE(CONSTANTCONDITION) \
677 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
679 EFX_CHECK_REG((_enp), (_reg)); \
680 EFSYS_BAR_READD((_enp)->en_esbp, \
681 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
683 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
684 uint32_t, (_index), \
685 uint32_t, _reg ## _OFST, \
686 uint32_t, (_edp)->ed_u32[0]); \
687 _NOTE(CONSTANTCONDITION) \
690 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
692 EFX_CHECK_REG((_enp), (_reg)); \
693 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
694 uint32_t, (_index), \
695 uint32_t, _reg ## _OFST, \
696 uint32_t, (_edp)->ed_u32[0]); \
697 EFSYS_BAR_WRITED((_enp)->en_esbp, \
698 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
700 _NOTE(CONSTANTCONDITION) \
703 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
705 EFX_CHECK_REG((_enp), (_reg)); \
706 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
707 uint32_t, (_index), \
708 uint32_t, _reg ## _OFST, \
709 uint32_t, (_edp)->ed_u32[0]); \
710 EFSYS_BAR_WRITED((_enp)->en_esbp, \
712 (2 * sizeof (efx_dword_t)) + \
713 ((_index) * _reg ## _STEP)), \
715 _NOTE(CONSTANTCONDITION) \
718 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
720 EFX_CHECK_REG((_enp), (_reg)); \
721 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
722 uint32_t, (_index), \
723 uint32_t, _reg ## _OFST, \
724 uint32_t, (_edp)->ed_u32[0]); \
725 EFSYS_BAR_WRITED((_enp)->en_esbp, \
727 (3 * sizeof (efx_dword_t)) + \
728 ((_index) * _reg ## _STEP)), \
730 _NOTE(CONSTANTCONDITION) \
733 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
735 EFX_CHECK_REG((_enp), (_reg)); \
736 EFSYS_BAR_READQ((_enp)->en_esbp, \
737 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
739 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
740 uint32_t, (_index), \
741 uint32_t, _reg ## _OFST, \
742 uint32_t, (_eqp)->eq_u32[1], \
743 uint32_t, (_eqp)->eq_u32[0]); \
744 _NOTE(CONSTANTCONDITION) \
747 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
749 EFX_CHECK_REG((_enp), (_reg)); \
750 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
751 uint32_t, (_index), \
752 uint32_t, _reg ## _OFST, \
753 uint32_t, (_eqp)->eq_u32[1], \
754 uint32_t, (_eqp)->eq_u32[0]); \
755 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
756 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
758 _NOTE(CONSTANTCONDITION) \
761 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
763 EFX_CHECK_REG((_enp), (_reg)); \
764 EFSYS_BAR_READO((_enp)->en_esbp, \
765 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
767 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
768 uint32_t, (_index), \
769 uint32_t, _reg ## _OFST, \
770 uint32_t, (_eop)->eo_u32[3], \
771 uint32_t, (_eop)->eo_u32[2], \
772 uint32_t, (_eop)->eo_u32[1], \
773 uint32_t, (_eop)->eo_u32[0]); \
774 _NOTE(CONSTANTCONDITION) \
777 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
779 EFX_CHECK_REG((_enp), (_reg)); \
780 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
781 uint32_t, (_index), \
782 uint32_t, _reg ## _OFST, \
783 uint32_t, (_eop)->eo_u32[3], \
784 uint32_t, (_eop)->eo_u32[2], \
785 uint32_t, (_eop)->eo_u32[1], \
786 uint32_t, (_eop)->eo_u32[0]); \
787 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
788 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
790 _NOTE(CONSTANTCONDITION) \
794 * Allow drivers to perform optimised 128-bit doorbell writes.
795 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
796 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
797 * the need for locking in the host, and are the only ones known to be safe to
798 * use 128-bites write with.
800 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
802 EFX_CHECK_REG((_enp), (_reg)); \
803 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
806 uint32_t, (_index), \
807 uint32_t, _reg ## _OFST, \
808 uint32_t, (_eop)->eo_u32[3], \
809 uint32_t, (_eop)->eo_u32[2], \
810 uint32_t, (_eop)->eo_u32[1], \
811 uint32_t, (_eop)->eo_u32[0]); \
812 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
813 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
815 _NOTE(CONSTANTCONDITION) \
818 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
820 unsigned int _new = (_wptr); \
821 unsigned int _old = (_owptr); \
823 if ((_new) >= (_old)) \
824 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
825 (_old) * sizeof (efx_desc_t), \
826 ((_new) - (_old)) * sizeof (efx_desc_t)); \
829 * It is cheaper to sync entire map than sync \
830 * two parts especially when offset/size are \
831 * ignored and entire map is synced in any case.\
833 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
835 (_entries) * sizeof (efx_desc_t)); \
836 _NOTE(CONSTANTCONDITION) \
839 extern __checkReturn efx_rc_t
841 __in efx_nic_t *enp);
843 extern __checkReturn efx_rc_t
845 __in efx_nic_t *enp);
848 efx_mac_multicast_hash_compute(
849 __in_ecount(6*count) uint8_t const *addrs,
851 __out efx_oword_t *hash_low,
852 __out efx_oword_t *hash_high);
854 extern __checkReturn efx_rc_t
856 __in efx_nic_t *enp);
860 __in efx_nic_t *enp);
864 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
866 typedef struct efx_register_set_s {
867 unsigned int address;
871 } efx_register_set_t;
873 extern __checkReturn efx_rc_t
874 efx_nic_test_registers(
876 __in efx_register_set_t *rsp,
879 extern __checkReturn efx_rc_t
882 __in efx_register_set_t *rsp,
883 __in efx_pattern_type_t pattern,
886 #endif /* EFSYS_OPT_DIAG */
890 extern __checkReturn efx_rc_t
891 efx_mcdi_set_workaround(
894 __in boolean_t enabled,
895 __out_opt uint32_t *flagsp);
897 extern __checkReturn efx_rc_t
898 efx_mcdi_get_workarounds(
900 __out_opt uint32_t *implementedp,
901 __out_opt uint32_t *enabledp);
903 #endif /* EFSYS_OPT_MCDI */
909 #endif /* _SYS_EFX_IMPL_H */