drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13
  14 /* FIXME: Add definition for driver generated software events */
  15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  17 #endif
  18
  19
  20 #if EFSYS_OPT_SIENA
  21 #include "siena_impl.h"
  22 #endif  /* EFSYS_OPT_SIENA */
  23
  24 #if EFSYS_OPT_HUNTINGTON
  25 #include "hunt_impl.h"
  26 #endif  /* EFSYS_OPT_HUNTINGTON */
  27
  28 #if EFSYS_OPT_MEDFORD
  29 #include "medford_impl.h"
  30 #endif  /* EFSYS_OPT_MEDFORD */
  31
  32 #if EFSYS_OPT_MEDFORD2
  33 #include "medford2_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD2 */
  35
  36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
  37 #include "ef10_impl.h"
  38 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
  39
  40 #ifdef  __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 #define EFX_MOD_MCDI            0x00000001
  45 #define EFX_MOD_PROBE           0x00000002
  46 #define EFX_MOD_NVRAM           0x00000004
  47 #define EFX_MOD_VPD             0x00000008
  48 #define EFX_MOD_NIC             0x00000010
  49 #define EFX_MOD_INTR            0x00000020
  50 #define EFX_MOD_EV              0x00000040
  51 #define EFX_MOD_RX              0x00000080
  52 #define EFX_MOD_TX              0x00000100
  53 #define EFX_MOD_PORT            0x00000200
  54 #define EFX_MOD_MON             0x00000400
  55 #define EFX_MOD_FILTER          0x00001000
  56 #define EFX_MOD_LIC             0x00002000
  57 #define EFX_MOD_TUNNEL          0x00004000
  58
  59 #define EFX_RESET_PHY           0x00000001
  60 #define EFX_RESET_RXQ_ERR       0x00000002
  61 #define EFX_RESET_TXQ_ERR       0x00000004
  62 #define EFX_RESET_HW_UNAVAIL    0x00000008
  63
  64 typedef enum efx_mac_type_e {
  65         EFX_MAC_INVALID = 0,
  66         EFX_MAC_SIENA,
  67         EFX_MAC_HUNTINGTON,
  68         EFX_MAC_MEDFORD,
  69         EFX_MAC_MEDFORD2,
  70         EFX_MAC_NTYPES
  71 } efx_mac_type_t;
  72
  73 typedef struct efx_ev_ops_s {
  74         efx_rc_t        (*eevo_init)(efx_nic_t *);
  75         void            (*eevo_fini)(efx_nic_t *);
  76         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  77                                           efsys_mem_t *, size_t, uint32_t,
  78                                           uint32_t, uint32_t, efx_evq_t *);
  79         void            (*eevo_qdestroy)(efx_evq_t *);
  80         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  81         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  82         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  83 #if EFSYS_OPT_QSTATS
  84         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  85 #endif
  86 } efx_ev_ops_t;
  87
  88 typedef struct efx_tx_ops_s {
  89         efx_rc_t        (*etxo_init)(efx_nic_t *);
  90         void            (*etxo_fini)(efx_nic_t *);
  91         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  92                                         unsigned int, unsigned int,
  93                                         efsys_mem_t *, size_t,
  94                                         uint32_t, uint16_t,
  95                                         efx_evq_t *, efx_txq_t *,
  96                                         unsigned int *);
  97         void            (*etxo_qdestroy)(efx_txq_t *);
  98         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
  99                                       unsigned int, unsigned int,
 100                                       unsigned int *);
 101         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 102         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 103         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 104         void            (*etxo_qenable)(efx_txq_t *);
 105         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 106         void            (*etxo_qpio_disable)(efx_txq_t *);
 107         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 108                                            size_t);
 109         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 110                                            unsigned int *);
 111         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 112                                       unsigned int, unsigned int,
 113                                       unsigned int *);
 114         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 115                                                 size_t, boolean_t,
 116                                                 efx_desc_t *);
 117         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 118                                                 uint32_t, uint8_t,
 119                                                 efx_desc_t *);
 120         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 121                                                 uint16_t, uint32_t, uint16_t,
 122                                                 efx_desc_t *, int);
 123         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 124                                                 efx_desc_t *);
 125         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 126                                                 efx_desc_t *);
 127 #if EFSYS_OPT_QSTATS
 128         void            (*etxo_qstats_update)(efx_txq_t *,
 129                                               efsys_stat_t *);
 130 #endif
 131 } efx_tx_ops_t;
 132
 133 typedef union efx_rxq_type_data_u {
 134         struct {
 135                 size_t          ed_buf_size;
 136         } ertd_default;
 137 #if EFSYS_OPT_RX_PACKED_STREAM
 138         struct {
 139                 uint32_t        eps_buf_size;
 140         } ertd_packed_stream;
 141 #endif
 142 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 143         struct {
 144                 uint32_t        eessb_bufs_per_desc;
 145                 uint32_t        eessb_max_dma_len;
 146                 uint32_t        eessb_buf_stride;
 147                 uint32_t        eessb_hol_block_timeout;
 148         } ertd_es_super_buffer;
 149 #endif
 150 } efx_rxq_type_data_t;
 151
 152 typedef struct efx_rx_ops_s {
 153         efx_rc_t        (*erxo_init)(efx_nic_t *);
 154         void            (*erxo_fini)(efx_nic_t *);
 155 #if EFSYS_OPT_RX_SCATTER
 156         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 157 #endif
 158 #if EFSYS_OPT_RX_SCALE
 159         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 160                                                     efx_rx_scale_context_type_t,
 161                                                     uint32_t, uint32_t *);
 162         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 163         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 164                                                efx_rx_hash_alg_t,
 165                                                efx_rx_hash_type_t, boolean_t);
 166         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 167                                               uint8_t *, size_t);
 168         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 169                                               unsigned int *, size_t);
 170         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 171                                             uint8_t *);
 172 #endif /* EFSYS_OPT_RX_SCALE */
 173         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 174                                               uint16_t *);
 175         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 176                                       unsigned int, unsigned int,
 177                                       unsigned int);
 178         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 179 #if EFSYS_OPT_RX_PACKED_STREAM
 180         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 181         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 182                                                 uint32_t, uint32_t,
 183                                                 uint16_t *, uint32_t *, uint32_t *);
 184 #endif
 185         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 186         void            (*erxo_qenable)(efx_rxq_t *);
 187         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 188                                         unsigned int, efx_rxq_type_t,
 189                                         const efx_rxq_type_data_t *,
 190                                         efsys_mem_t *, size_t, uint32_t,
 191                                         unsigned int,
 192                                         efx_evq_t *, efx_rxq_t *);
 193         void            (*erxo_qdestroy)(efx_rxq_t *);
 194 } efx_rx_ops_t;
 195
 196 typedef struct efx_mac_ops_s {
 197         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 198         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 199         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 200         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 201         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 202         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 203         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 204         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 205                                                       efx_rxq_t *, boolean_t);
 206         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 207 #if EFSYS_OPT_LOOPBACK
 208         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 209                                             efx_loopback_type_t);
 210 #endif  /* EFSYS_OPT_LOOPBACK */
 211 #if EFSYS_OPT_MAC_STATS
 212         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 213         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 214         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 215         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 216                                               uint16_t, boolean_t);
 217         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 218                                             efsys_stat_t *, uint32_t *);
 219 #endif  /* EFSYS_OPT_MAC_STATS */
 220 } efx_mac_ops_t;
 221
 222 typedef struct efx_phy_ops_s {
 223         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 224         efx_rc_t        (*epo_reset)(efx_nic_t *);
 225         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 226         efx_rc_t        (*epo_verify)(efx_nic_t *);
 227         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 228         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 229 #if EFSYS_OPT_PHY_STATS
 230         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 231                                             uint32_t *);
 232 #endif  /* EFSYS_OPT_PHY_STATS */
 233 #if EFSYS_OPT_BIST
 234         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 235         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 236         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 237                                          efx_bist_result_t *, uint32_t *,
 238                                          unsigned long *, size_t);
 239         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 240 #endif  /* EFSYS_OPT_BIST */
 241 } efx_phy_ops_t;
 242
 243 #if EFSYS_OPT_FILTER
 244 typedef struct efx_filter_ops_s {
 245         efx_rc_t        (*efo_init)(efx_nic_t *);
 246         void            (*efo_fini)(efx_nic_t *);
 247         efx_rc_t        (*efo_restore)(efx_nic_t *);
 248         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 249                                    boolean_t may_replace);
 250         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 251         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 252                                    size_t, size_t *);
 253         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 254                                    boolean_t, boolean_t, boolean_t,
 255                                    uint8_t const *, uint32_t);
 256 } efx_filter_ops_t;
 257
 258 extern  __checkReturn   efx_rc_t
 259 efx_filter_reconfigure(
 260         __in                            efx_nic_t *enp,
 261         __in_ecount(6)                  uint8_t const *mac_addr,
 262         __in                            boolean_t all_unicst,
 263         __in                            boolean_t mulcst,
 264         __in                            boolean_t all_mulcst,
 265         __in                            boolean_t brdcst,
 266         __in_ecount(6*count)            uint8_t const *addrs,
 267         __in                            uint32_t count);
 268
 269 #endif /* EFSYS_OPT_FILTER */
 270
 271 #if EFSYS_OPT_TUNNEL
 272 typedef struct efx_tunnel_ops_s {
 273         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 274         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 275 } efx_tunnel_ops_t;
 276 #endif /* EFSYS_OPT_TUNNEL */
 277
 278 typedef struct efx_port_s {
 279         efx_mac_type_t          ep_mac_type;
 280         uint32_t                ep_phy_type;
 281         uint8_t                 ep_port;
 282         uint32_t                ep_mac_pdu;
 283         uint8_t                 ep_mac_addr[6];
 284         efx_link_mode_t         ep_link_mode;
 285         boolean_t               ep_all_unicst;
 286         boolean_t               ep_mulcst;
 287         boolean_t               ep_all_mulcst;
 288         boolean_t               ep_brdcst;
 289         unsigned int            ep_fcntl;
 290         boolean_t               ep_fcntl_autoneg;
 291         efx_oword_t             ep_multicst_hash[2];
 292         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 293                                                     EFX_MAC_MULTICAST_LIST_MAX];
 294         uint32_t                ep_mulcst_addr_count;
 295 #if EFSYS_OPT_LOOPBACK
 296         efx_loopback_type_t     ep_loopback_type;
 297         efx_link_mode_t         ep_loopback_link_mode;
 298 #endif  /* EFSYS_OPT_LOOPBACK */
 299 #if EFSYS_OPT_PHY_FLAGS
 300         uint32_t                ep_phy_flags;
 301 #endif  /* EFSYS_OPT_PHY_FLAGS */
 302 #if EFSYS_OPT_PHY_LED_CONTROL
 303         efx_phy_led_mode_t      ep_phy_led_mode;
 304 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 305         efx_phy_media_type_t    ep_fixed_port_type;
 306         efx_phy_media_type_t    ep_module_type;
 307         uint32_t                ep_adv_cap_mask;
 308         uint32_t                ep_lp_cap_mask;
 309         uint32_t                ep_default_adv_cap_mask;
 310         uint32_t                ep_phy_cap_mask;
 311         boolean_t               ep_mac_drain;
 312 #if EFSYS_OPT_BIST
 313         efx_bist_type_t         ep_current_bist;
 314 #endif
 315         const efx_mac_ops_t     *ep_emop;
 316         const efx_phy_ops_t     *ep_epop;
 317 } efx_port_t;
 318
 319 typedef struct efx_mon_ops_s {
 320 #if EFSYS_OPT_MON_STATS
 321         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 322                                             efx_mon_stat_value_t *);
 323         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 324                                              efx_mon_stat_limits_t *);
 325 #endif  /* EFSYS_OPT_MON_STATS */
 326 } efx_mon_ops_t;
 327
 328 typedef struct efx_mon_s {
 329         efx_mon_type_t          em_type;
 330         const efx_mon_ops_t     *em_emop;
 331 } efx_mon_t;
 332
 333 typedef struct efx_intr_ops_s {
 334         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 335         void            (*eio_enable)(efx_nic_t *);
 336         void            (*eio_disable)(efx_nic_t *);
 337         void            (*eio_disable_unlocked)(efx_nic_t *);
 338         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 339         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 340         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 341                                  boolean_t *);
 342         void            (*eio_fatal)(efx_nic_t *);
 343         void            (*eio_fini)(efx_nic_t *);
 344 } efx_intr_ops_t;
 345
 346 typedef struct efx_intr_s {
 347         const efx_intr_ops_t    *ei_eiop;
 348         efsys_mem_t             *ei_esmp;
 349         efx_intr_type_t         ei_type;
 350         unsigned int            ei_level;
 351 } efx_intr_t;
 352
 353 typedef struct efx_nic_ops_s {
 354         efx_rc_t        (*eno_probe)(efx_nic_t *);
 355         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 356         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 357         efx_rc_t        (*eno_reset)(efx_nic_t *);
 358         efx_rc_t        (*eno_init)(efx_nic_t *);
 359         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 360         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 361                                         uint32_t *, size_t *);
 362         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 363         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 364 #if EFSYS_OPT_DIAG
 365         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 366 #endif  /* EFSYS_OPT_DIAG */
 367         void            (*eno_fini)(efx_nic_t *);
 368         void            (*eno_unprobe)(efx_nic_t *);
 369 } efx_nic_ops_t;
 370
 371 #ifndef EFX_TXQ_LIMIT_TARGET
 372 #define EFX_TXQ_LIMIT_TARGET 259
 373 #endif
 374 #ifndef EFX_RXQ_LIMIT_TARGET
 375 #define EFX_RXQ_LIMIT_TARGET 512
 376 #endif
 377
 378
 379 #if EFSYS_OPT_FILTER
 380
 381 #if EFSYS_OPT_SIENA
 382
 383 typedef struct siena_filter_spec_s {
 384         uint8_t         sfs_type;
 385         uint32_t        sfs_flags;
 386         uint32_t        sfs_dmaq_id;
 387         uint32_t        sfs_dword[3];
 388 } siena_filter_spec_t;
 389
 390 typedef enum siena_filter_type_e {
 391         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 392         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 393         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 394         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 395         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 396         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 397
 398         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 399         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 400         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 401         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 402         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 403         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 404
 405         EFX_SIENA_FILTER_NTYPES
 406 } siena_filter_type_t;
 407
 408 typedef enum siena_filter_tbl_id_e {
 409         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 410         EFX_SIENA_FILTER_TBL_RX_MAC,
 411         EFX_SIENA_FILTER_TBL_TX_IP,
 412         EFX_SIENA_FILTER_TBL_TX_MAC,
 413         EFX_SIENA_FILTER_NTBLS
 414 } siena_filter_tbl_id_t;
 415
 416 typedef struct siena_filter_tbl_s {
 417         int                     sft_size;       /* number of entries */
 418         int                     sft_used;       /* active count */
 419         uint32_t                *sft_bitmap;    /* active bitmap */
 420         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 421 } siena_filter_tbl_t;
 422
 423 typedef struct siena_filter_s {
 424         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 425         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 426 } siena_filter_t;
 427
 428 #endif  /* EFSYS_OPT_SIENA */
 429
 430 typedef struct efx_filter_s {
 431 #if EFSYS_OPT_SIENA
 432         siena_filter_t          *ef_siena_filter;
 433 #endif /* EFSYS_OPT_SIENA */
 434 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 435         ef10_filter_table_t     *ef_ef10_filter_table;
 436 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 437 } efx_filter_t;
 438
 439 #if EFSYS_OPT_SIENA
 440
 441 extern                  void
 442 siena_filter_tbl_clear(
 443         __in            efx_nic_t *enp,
 444         __in            siena_filter_tbl_id_t tbl);
 445
 446 #endif  /* EFSYS_OPT_SIENA */
 447
 448 #endif  /* EFSYS_OPT_FILTER */
 449
 450 #if EFSYS_OPT_MCDI
 451
 452 #define EFX_TUNNEL_MAXNENTRIES  (16)
 453
 454 #if EFSYS_OPT_TUNNEL
 455
 456 typedef struct efx_tunnel_udp_entry_s {
 457         uint16_t                        etue_port; /* host/cpu-endian */
 458         uint16_t                        etue_protocol;
 459 } efx_tunnel_udp_entry_t;
 460
 461 typedef struct efx_tunnel_cfg_s {
 462         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 463         unsigned int            etc_udp_entries_num;
 464 } efx_tunnel_cfg_t;
 465
 466 #endif /* EFSYS_OPT_TUNNEL */
 467
 468 typedef struct efx_mcdi_ops_s {
 469         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 470         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 471                                         void *, size_t);
 472         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 473         boolean_t       (*emco_poll_response)(efx_nic_t *);
 474         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 475         void            (*emco_fini)(efx_nic_t *);
 476         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 477                                             efx_mcdi_feature_id_t, boolean_t *);
 478         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 479                                             uint32_t *);
 480 } efx_mcdi_ops_t;
 481
 482 typedef struct efx_mcdi_s {
 483         const efx_mcdi_ops_t            *em_emcop;
 484         const efx_mcdi_transport_t      *em_emtp;
 485         efx_mcdi_iface_t                em_emip;
 486 } efx_mcdi_t;
 487
 488 #endif /* EFSYS_OPT_MCDI */
 489
 490 #if EFSYS_OPT_NVRAM
 491
 492 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 493 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 494
 495 typedef struct efx_nvram_ops_s {
 496 #if EFSYS_OPT_DIAG
 497         efx_rc_t        (*envo_test)(efx_nic_t *);
 498 #endif  /* EFSYS_OPT_DIAG */
 499         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 500                                             uint32_t *);
 501         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 502         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 503         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 504                                             unsigned int, caddr_t, size_t);
 505         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 506                                             unsigned int, caddr_t, size_t);
 507         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 508                                             unsigned int, size_t);
 509         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 510                                             unsigned int, caddr_t, size_t);
 511         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 512                                             uint32_t *);
 513         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 514                                             uint32_t *, uint16_t *);
 515         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 516                                             uint16_t *);
 517         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 518                                             caddr_t, size_t);
 519 } efx_nvram_ops_t;
 520 #endif /* EFSYS_OPT_NVRAM */
 521
 522 #if EFSYS_OPT_VPD
 523 typedef struct efx_vpd_ops_s {
 524         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 525         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 526         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 527         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 528         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 529         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 530                                         efx_vpd_value_t *);
 531         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 532                                         efx_vpd_value_t *);
 533         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 534                                         efx_vpd_value_t *, unsigned int *);
 535         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 536         void            (*evpdo_fini)(efx_nic_t *);
 537 } efx_vpd_ops_t;
 538 #endif  /* EFSYS_OPT_VPD */
 539
 540 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 541
 542         __checkReturn           efx_rc_t
 543 efx_mcdi_nvram_partitions(
 544         __in                    efx_nic_t *enp,
 545         __out_bcount(size)      caddr_t data,
 546         __in                    size_t size,
 547         __out                   unsigned int *npartnp);
 548
 549         __checkReturn           efx_rc_t
 550 efx_mcdi_nvram_metadata(
 551         __in                    efx_nic_t *enp,
 552         __in                    uint32_t partn,
 553         __out                   uint32_t *subtypep,
 554         __out_ecount(4)         uint16_t version[4],
 555         __out_bcount_opt(size)  char *descp,
 556         __in                    size_t size);
 557
 558         __checkReturn           efx_rc_t
 559 efx_mcdi_nvram_info(
 560         __in                    efx_nic_t *enp,
 561         __in                    uint32_t partn,
 562         __out_opt               size_t *sizep,
 563         __out_opt               uint32_t *addressp,
 564         __out_opt               uint32_t *erase_sizep,
 565         __out_opt               uint32_t *write_sizep);
 566
 567         __checkReturn           efx_rc_t
 568 efx_mcdi_nvram_update_start(
 569         __in                    efx_nic_t *enp,
 570         __in                    uint32_t partn);
 571
 572         __checkReturn           efx_rc_t
 573 efx_mcdi_nvram_read(
 574         __in                    efx_nic_t *enp,
 575         __in                    uint32_t partn,
 576         __in                    uint32_t offset,
 577         __out_bcount(size)      caddr_t data,
 578         __in                    size_t size,
 579         __in                    uint32_t mode);
 580
 581         __checkReturn           efx_rc_t
 582 efx_mcdi_nvram_erase(
 583         __in                    efx_nic_t *enp,
 584         __in                    uint32_t partn,
 585         __in                    uint32_t offset,
 586         __in                    size_t size);
 587
 588         __checkReturn           efx_rc_t
 589 efx_mcdi_nvram_write(
 590         __in                    efx_nic_t *enp,
 591         __in                    uint32_t partn,
 592         __in                    uint32_t offset,
 593         __in_bcount(size)       caddr_t data,
 594         __in                    size_t size);
 595
 596         __checkReturn           efx_rc_t
 597 efx_mcdi_nvram_update_finish(
 598         __in                    efx_nic_t *enp,
 599         __in                    uint32_t partn,
 600         __in                    boolean_t reboot,
 601         __out_opt               uint32_t *verify_resultp);
 602
 603 #if EFSYS_OPT_DIAG
 604
 605         __checkReturn           efx_rc_t
 606 efx_mcdi_nvram_test(
 607         __in                    efx_nic_t *enp,
 608         __in                    uint32_t partn);
 609
 610 #endif  /* EFSYS_OPT_DIAG */
 611
 612 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 613
 614 #if EFSYS_OPT_LICENSING
 615
 616 typedef struct efx_lic_ops_s {
 617         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 618         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 619         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 620         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 621                                       size_t *, uint8_t *);
 622         efx_rc_t        (*elo_find_start)
 623                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 624         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 625                                 uint32_t, uint32_t *);
 626         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 627                                 uint32_t, uint32_t *, uint32_t *);
 628         boolean_t       (*elo_validate_key)(efx_nic_t *,
 629                                 caddr_t, uint32_t);
 630         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 631                                 caddr_t, size_t, uint32_t, uint32_t,
 632                                 caddr_t, size_t, uint32_t *);
 633         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 634                                 caddr_t, size_t, uint32_t,
 635                                 caddr_t, uint32_t, uint32_t *);
 636         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 637                                 caddr_t, size_t, uint32_t,
 638                                 uint32_t, uint32_t, uint32_t *);
 639         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 640                                 caddr_t, size_t);
 641         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 642                                 caddr_t, size_t);
 643 } efx_lic_ops_t;
 644
 645 #endif
 646
 647 typedef struct efx_drv_cfg_s {
 648         uint32_t                edc_min_vi_count;
 649         uint32_t                edc_max_vi_count;
 650
 651         uint32_t                edc_max_piobuf_count;
 652         uint32_t                edc_pio_alloc_size;
 653 } efx_drv_cfg_t;
 654
 655 struct efx_nic_s {
 656         uint32_t                en_magic;
 657         efx_family_t            en_family;
 658         uint32_t                en_features;
 659         efsys_identifier_t      *en_esip;
 660         efsys_lock_t            *en_eslp;
 661         efsys_bar_t             *en_esbp;
 662         unsigned int            en_mod_flags;
 663         unsigned int            en_reset_flags;
 664         efx_nic_cfg_t           en_nic_cfg;
 665         efx_drv_cfg_t           en_drv_cfg;
 666         efx_port_t              en_port;
 667         efx_mon_t               en_mon;
 668         efx_intr_t              en_intr;
 669         uint32_t                en_ev_qcount;
 670         uint32_t                en_rx_qcount;
 671         uint32_t                en_tx_qcount;
 672         const efx_nic_ops_t     *en_enop;
 673         const efx_ev_ops_t      *en_eevop;
 674         const efx_tx_ops_t      *en_etxop;
 675         const efx_rx_ops_t      *en_erxop;
 676         efx_fw_variant_t        efv;
 677 #if EFSYS_OPT_FILTER
 678         efx_filter_t            en_filter;
 679         const efx_filter_ops_t  *en_efop;
 680 #endif  /* EFSYS_OPT_FILTER */
 681 #if EFSYS_OPT_TUNNEL
 682         efx_tunnel_cfg_t        en_tunnel_cfg;
 683         const efx_tunnel_ops_t  *en_etop;
 684 #endif /* EFSYS_OPT_TUNNEL */
 685 #if EFSYS_OPT_MCDI
 686         efx_mcdi_t              en_mcdi;
 687 #endif  /* EFSYS_OPT_MCDI */
 688 #if EFSYS_OPT_NVRAM
 689         uint32_t                en_nvram_partn_locked;
 690         const efx_nvram_ops_t   *en_envop;
 691 #endif  /* EFSYS_OPT_NVRAM */
 692 #if EFSYS_OPT_VPD
 693         const efx_vpd_ops_t     *en_evpdop;
 694 #endif  /* EFSYS_OPT_VPD */
 695 #if EFSYS_OPT_RX_SCALE
 696         efx_rx_hash_support_t           en_hash_support;
 697         efx_rx_scale_context_type_t     en_rss_context_type;
 698         uint32_t                        en_rss_context;
 699 #endif  /* EFSYS_OPT_RX_SCALE */
 700         uint32_t                en_vport_id;
 701 #if EFSYS_OPT_LICENSING
 702         const efx_lic_ops_t     *en_elop;
 703         boolean_t               en_licensing_supported;
 704 #endif
 705         union {
 706 #if EFSYS_OPT_SIENA
 707                 struct {
 708 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 709                         unsigned int            enu_partn_mask;
 710 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 711 #if EFSYS_OPT_VPD
 712                         caddr_t                 enu_svpd;
 713                         size_t                  enu_svpd_length;
 714 #endif  /* EFSYS_OPT_VPD */
 715                         int                     enu_unused;
 716                 } siena;
 717 #endif  /* EFSYS_OPT_SIENA */
 718                 int     enu_unused;
 719         } en_u;
 720 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
 721         union en_arch {
 722                 struct {
 723                         int                     ena_vi_base;
 724                         int                     ena_vi_count;
 725                         int                     ena_vi_shift;
 726 #if EFSYS_OPT_VPD
 727                         caddr_t                 ena_svpd;
 728                         size_t                  ena_svpd_length;
 729 #endif  /* EFSYS_OPT_VPD */
 730                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 731                         uint32_t                ena_piobuf_count;
 732                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 733                         uint32_t                ena_pio_write_vi_base;
 734                         /* Memory BAR mapping regions */
 735                         uint32_t                ena_uc_mem_map_offset;
 736                         size_t                  ena_uc_mem_map_size;
 737                         uint32_t                ena_wc_mem_map_offset;
 738                         size_t                  ena_wc_mem_map_size;
 739                 } ef10;
 740         } en_arch;
 741 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 742 };
 743
 744
 745 #define EFX_NIC_MAGIC   0x02121996
 746
 747 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 748     const efx_ev_callbacks_t *, void *);
 749
 750 typedef struct efx_evq_rxq_state_s {
 751         unsigned int                    eers_rx_read_ptr;
 752         unsigned int                    eers_rx_mask;
 753 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 754         unsigned int                    eers_rx_stream_npackets;
 755         boolean_t                       eers_rx_packed_stream;
 756 #endif
 757 #if EFSYS_OPT_RX_PACKED_STREAM
 758         unsigned int                    eers_rx_packed_stream_credits;
 759 #endif
 760 } efx_evq_rxq_state_t;
 761
 762 struct efx_evq_s {
 763         uint32_t                        ee_magic;
 764         uint32_t                        ee_flags;
 765         efx_nic_t                       *ee_enp;
 766         unsigned int                    ee_index;
 767         unsigned int                    ee_mask;
 768         efsys_mem_t                     *ee_esmp;
 769 #if EFSYS_OPT_QSTATS
 770         uint32_t                        ee_stat[EV_NQSTATS];
 771 #endif  /* EFSYS_OPT_QSTATS */
 772
 773         efx_ev_handler_t                ee_rx;
 774         efx_ev_handler_t                ee_tx;
 775         efx_ev_handler_t                ee_driver;
 776         efx_ev_handler_t                ee_global;
 777         efx_ev_handler_t                ee_drv_gen;
 778 #if EFSYS_OPT_MCDI
 779         efx_ev_handler_t                ee_mcdi;
 780 #endif  /* EFSYS_OPT_MCDI */
 781
 782         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 783 };
 784
 785 #define EFX_EVQ_MAGIC   0x08081997
 786
 787 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 788
 789 struct efx_rxq_s {
 790         uint32_t                        er_magic;
 791         efx_nic_t                       *er_enp;
 792         efx_evq_t                       *er_eep;
 793         unsigned int                    er_index;
 794         unsigned int                    er_label;
 795         unsigned int                    er_mask;
 796         size_t                          er_buf_size;
 797         efsys_mem_t                     *er_esmp;
 798         efx_evq_rxq_state_t             *er_ev_qstate;
 799 };
 800
 801 #define EFX_RXQ_MAGIC   0x15022005
 802
 803 struct efx_txq_s {
 804         uint32_t                        et_magic;
 805         efx_nic_t                       *et_enp;
 806         unsigned int                    et_index;
 807         unsigned int                    et_mask;
 808         efsys_mem_t                     *et_esmp;
 809 #if EFSYS_OPT_HUNTINGTON
 810         uint32_t                        et_pio_bufnum;
 811         uint32_t                        et_pio_blknum;
 812         uint32_t                        et_pio_write_offset;
 813         uint32_t                        et_pio_offset;
 814         size_t                          et_pio_size;
 815 #endif
 816 #if EFSYS_OPT_QSTATS
 817         uint32_t                        et_stat[TX_NQSTATS];
 818 #endif  /* EFSYS_OPT_QSTATS */
 819 };
 820
 821 #define EFX_TXQ_MAGIC   0x05092005
 822
 823 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 824         do {                                                            \
 825                 (_dst)[0] = (_src)[0];                                  \
 826                 (_dst)[1] = (_src)[1];                                  \
 827                 (_dst)[2] = (_src)[2];                                  \
 828                 (_dst)[3] = (_src)[3];                                  \
 829                 (_dst)[4] = (_src)[4];                                  \
 830                 (_dst)[5] = (_src)[5];                                  \
 831         _NOTE(CONSTANTCONDITION)                                        \
 832         } while (B_FALSE)
 833
 834 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 835         do {                                                            \
 836                 uint16_t *_d = (uint16_t *)(_dst);                      \
 837                 _d[0] = 0xffff;                                         \
 838                 _d[1] = 0xffff;                                         \
 839                 _d[2] = 0xffff;                                         \
 840         _NOTE(CONSTANTCONDITION)                                        \
 841         } while (B_FALSE)
 842
 843 #if EFSYS_OPT_CHECK_REG
 844 #define EFX_CHECK_REG(_enp, _reg)                                       \
 845         do {                                                            \
 846                 const char *name = #_reg;                               \
 847                 char min = name[4];                                     \
 848                 char max = name[5];                                     \
 849                 char rev;                                               \
 850                                                                         \
 851                 switch ((_enp)->en_family) {                            \
 852                 case EFX_FAMILY_SIENA:                                  \
 853                         rev = 'C';                                      \
 854                         break;                                          \
 855                                                                         \
 856                 case EFX_FAMILY_HUNTINGTON:                             \
 857                         rev = 'D';                                      \
 858                         break;                                          \
 859                                                                         \
 860                 case EFX_FAMILY_MEDFORD:                                \
 861                         rev = 'E';                                      \
 862                         break;                                          \
 863                                                                         \
 864                 case EFX_FAMILY_MEDFORD2:                               \
 865                         rev = 'F';                                      \
 866                         break;                                          \
 867                                                                         \
 868                 default:                                                \
 869                         rev = '?';                                      \
 870                         break;                                          \
 871                 }                                                       \
 872                                                                         \
 873                 EFSYS_ASSERT3S(rev, >=, min);                           \
 874                 EFSYS_ASSERT3S(rev, <=, max);                           \
 875                                                                         \
 876         _NOTE(CONSTANTCONDITION)                                        \
 877         } while (B_FALSE)
 878 #else
 879 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 880         _NOTE(CONSTANTCONDITION)                                        \
 881         } while (B_FALSE)
 882 #endif
 883
 884 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 885         do {                                                            \
 886                 EFX_CHECK_REG((_enp), (_reg));                          \
 887                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 888                     (_edp), (_lock));                                   \
 889                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 890                     uint32_t, _reg ## _OFST,                            \
 891                     uint32_t, (_edp)->ed_u32[0]);                       \
 892         _NOTE(CONSTANTCONDITION)                                        \
 893         } while (B_FALSE)
 894
 895 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 896         do {                                                            \
 897                 EFX_CHECK_REG((_enp), (_reg));                          \
 898                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 899                     uint32_t, _reg ## _OFST,                            \
 900                     uint32_t, (_edp)->ed_u32[0]);                       \
 901                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 902                     (_edp), (_lock));                                   \
 903         _NOTE(CONSTANTCONDITION)                                        \
 904         } while (B_FALSE)
 905
 906 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 907         do {                                                            \
 908                 EFX_CHECK_REG((_enp), (_reg));                          \
 909                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 910                     (_eqp));                                            \
 911                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 912                     uint32_t, _reg ## _OFST,                            \
 913                     uint32_t, (_eqp)->eq_u32[1],                        \
 914                     uint32_t, (_eqp)->eq_u32[0]);                       \
 915         _NOTE(CONSTANTCONDITION)                                        \
 916         } while (B_FALSE)
 917
 918 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 919         do {                                                            \
 920                 EFX_CHECK_REG((_enp), (_reg));                          \
 921                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 922                     uint32_t, _reg ## _OFST,                            \
 923                     uint32_t, (_eqp)->eq_u32[1],                        \
 924                     uint32_t, (_eqp)->eq_u32[0]);                       \
 925                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 926                     (_eqp));                                            \
 927         _NOTE(CONSTANTCONDITION)                                        \
 928         } while (B_FALSE)
 929
 930 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 931         do {                                                            \
 932                 EFX_CHECK_REG((_enp), (_reg));                          \
 933                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 934                     (_eop), B_TRUE);                                    \
 935                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 936                     uint32_t, _reg ## _OFST,                            \
 937                     uint32_t, (_eop)->eo_u32[3],                        \
 938                     uint32_t, (_eop)->eo_u32[2],                        \
 939                     uint32_t, (_eop)->eo_u32[1],                        \
 940                     uint32_t, (_eop)->eo_u32[0]);                       \
 941         _NOTE(CONSTANTCONDITION)                                        \
 942         } while (B_FALSE)
 943
 944 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 945         do {                                                            \
 946                 EFX_CHECK_REG((_enp), (_reg));                          \
 947                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 948                     uint32_t, _reg ## _OFST,                            \
 949                     uint32_t, (_eop)->eo_u32[3],                        \
 950                     uint32_t, (_eop)->eo_u32[2],                        \
 951                     uint32_t, (_eop)->eo_u32[1],                        \
 952                     uint32_t, (_eop)->eo_u32[0]);                       \
 953                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 954                     (_eop), B_TRUE);                                    \
 955         _NOTE(CONSTANTCONDITION)                                        \
 956         } while (B_FALSE)
 957
 958 /*
 959  * Accessors for memory BAR non-VI tables.
 960  *
 961  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
 962  * to ensure the correct runtime VI window size is used on Medford2.
 963  *
 964  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
 965  */
 966
 967 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 968         do {                                                            \
 969                 EFX_CHECK_REG((_enp), (_reg));                          \
 970                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 971                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 972                     (_edp), (_lock));                                   \
 973                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 974                     uint32_t, (_index),                                 \
 975                     uint32_t, _reg ## _OFST,                            \
 976                     uint32_t, (_edp)->ed_u32[0]);                       \
 977         _NOTE(CONSTANTCONDITION)                                        \
 978         } while (B_FALSE)
 979
 980 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 981         do {                                                            \
 982                 EFX_CHECK_REG((_enp), (_reg));                          \
 983                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 984                     uint32_t, (_index),                                 \
 985                     uint32_t, _reg ## _OFST,                            \
 986                     uint32_t, (_edp)->ed_u32[0]);                       \
 987                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 988                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 989                     (_edp), (_lock));                                   \
 990         _NOTE(CONSTANTCONDITION)                                        \
 991         } while (B_FALSE)
 992
 993 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 994         do {                                                            \
 995                 EFX_CHECK_REG((_enp), (_reg));                          \
 996                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 997                     uint32_t, (_index),                                 \
 998                     uint32_t, _reg ## _OFST,                            \
 999                     uint32_t, (_edp)->ed_u32[0]);                       \
1000                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1001                     (_reg ## _OFST +                                    \
1002                     (3 * sizeof (efx_dword_t)) +                        \
1003                     ((_index) * _reg ## _STEP)),                        \
1004                     (_edp), (_lock));                                   \
1005         _NOTE(CONSTANTCONDITION)                                        \
1006         } while (B_FALSE)
1007
1008 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1009         do {                                                            \
1010                 EFX_CHECK_REG((_enp), (_reg));                          \
1011                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1012                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1013                     (_eqp));                                            \
1014                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1015                     uint32_t, (_index),                                 \
1016                     uint32_t, _reg ## _OFST,                            \
1017                     uint32_t, (_eqp)->eq_u32[1],                        \
1018                     uint32_t, (_eqp)->eq_u32[0]);                       \
1019         _NOTE(CONSTANTCONDITION)                                        \
1020         } while (B_FALSE)
1021
1022 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1023         do {                                                            \
1024                 EFX_CHECK_REG((_enp), (_reg));                          \
1025                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1026                     uint32_t, (_index),                                 \
1027                     uint32_t, _reg ## _OFST,                            \
1028                     uint32_t, (_eqp)->eq_u32[1],                        \
1029                     uint32_t, (_eqp)->eq_u32[0]);                       \
1030                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1031                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1032                     (_eqp));                                            \
1033         _NOTE(CONSTANTCONDITION)                                        \
1034         } while (B_FALSE)
1035
1036 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1037         do {                                                            \
1038                 EFX_CHECK_REG((_enp), (_reg));                          \
1039                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1040                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1041                     (_eop), (_lock));                                   \
1042                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1043                     uint32_t, (_index),                                 \
1044                     uint32_t, _reg ## _OFST,                            \
1045                     uint32_t, (_eop)->eo_u32[3],                        \
1046                     uint32_t, (_eop)->eo_u32[2],                        \
1047                     uint32_t, (_eop)->eo_u32[1],                        \
1048                     uint32_t, (_eop)->eo_u32[0]);                       \
1049         _NOTE(CONSTANTCONDITION)                                        \
1050         } while (B_FALSE)
1051
1052 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1053         do {                                                            \
1054                 EFX_CHECK_REG((_enp), (_reg));                          \
1055                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1056                     uint32_t, (_index),                                 \
1057                     uint32_t, _reg ## _OFST,                            \
1058                     uint32_t, (_eop)->eo_u32[3],                        \
1059                     uint32_t, (_eop)->eo_u32[2],                        \
1060                     uint32_t, (_eop)->eo_u32[1],                        \
1061                     uint32_t, (_eop)->eo_u32[0]);                       \
1062                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1063                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1064                     (_eop), (_lock));                                   \
1065         _NOTE(CONSTANTCONDITION)                                        \
1066         } while (B_FALSE)
1067
1068 /*
1069  * Accessors for memory BAR per-VI registers.
1070  *
1071  * The VI window size is 8KB for Medford and all earlier controllers.
1072  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1073  */
1074
1075 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1076         do {                                                            \
1077                 EFX_CHECK_REG((_enp), (_reg));                          \
1078                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1079                     ((_reg ## _OFST) +                                  \
1080                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1081                     (_edp), (_lock));                                   \
1082                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1083                     uint32_t, (_index),                                 \
1084                     uint32_t, _reg ## _OFST,                            \
1085                     uint32_t, (_edp)->ed_u32[0]);                       \
1086         _NOTE(CONSTANTCONDITION)                                        \
1087         } while (B_FALSE)
1088
1089 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1090         do {                                                            \
1091                 EFX_CHECK_REG((_enp), (_reg));                          \
1092                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1093                     uint32_t, (_index),                                 \
1094                     uint32_t, _reg ## _OFST,                            \
1095                     uint32_t, (_edp)->ed_u32[0]);                       \
1096                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1097                     ((_reg ## _OFST) +                                  \
1098                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1099                     (_edp), (_lock));                                   \
1100         _NOTE(CONSTANTCONDITION)                                        \
1101         } while (B_FALSE)
1102
1103 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1104         do {                                                            \
1105                 EFX_CHECK_REG((_enp), (_reg));                          \
1106                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1107                     uint32_t, (_index),                                 \
1108                     uint32_t, _reg ## _OFST,                            \
1109                     uint32_t, (_edp)->ed_u32[0]);                       \
1110                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1111                     ((_reg ## _OFST) +                                  \
1112                     (2 * sizeof (efx_dword_t)) +                        \
1113                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1114                     (_edp), (_lock));                                   \
1115         _NOTE(CONSTANTCONDITION)                                        \
1116         } while (B_FALSE)
1117
1118 /*
1119  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1120  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1121  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1122  * the need for locking in the host, and are the only ones known to be safe to
1123  * use 128-bites write with.
1124  */
1125 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1126         do {                                                            \
1127                 EFX_CHECK_REG((_enp), (_reg));                          \
1128                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1129                     const char *, #_reg,                                \
1130                     uint32_t, (_index),                                 \
1131                     uint32_t, _reg ## _OFST,                            \
1132                     uint32_t, (_eop)->eo_u32[3],                        \
1133                     uint32_t, (_eop)->eo_u32[2],                        \
1134                     uint32_t, (_eop)->eo_u32[1],                        \
1135                     uint32_t, (_eop)->eo_u32[0]);                       \
1136                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1137                     (_reg ## _OFST +                                    \
1138                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1139                     (_eop));                                            \
1140         _NOTE(CONSTANTCONDITION)                                        \
1141         } while (B_FALSE)
1142
1143 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1144         do {                                                            \
1145                 unsigned int _new = (_wptr);                            \
1146                 unsigned int _old = (_owptr);                           \
1147                                                                         \
1148                 if ((_new) >= (_old))                                   \
1149                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1150                             (_old) * sizeof (efx_desc_t),               \
1151                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1152                 else                                                    \
1153                         /*                                              \
1154                          * It is cheaper to sync entire map than sync   \
1155                          * two parts especially when offset/size are    \
1156                          * ignored and entire map is synced in any case.\
1157                          */                                             \
1158                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1159                             0,                                          \
1160                             (_entries) * sizeof (efx_desc_t));          \
1161         _NOTE(CONSTANTCONDITION)                                        \
1162         } while (B_FALSE)
1163
1164 extern  __checkReturn   efx_rc_t
1165 efx_mac_select(
1166         __in            efx_nic_t *enp);
1167
1168 extern  void
1169 efx_mac_multicast_hash_compute(
1170         __in_ecount(6*count)            uint8_t const *addrs,
1171         __in                            int count,
1172         __out                           efx_oword_t *hash_low,
1173         __out                           efx_oword_t *hash_high);
1174
1175 extern  __checkReturn   efx_rc_t
1176 efx_phy_probe(
1177         __in            efx_nic_t *enp);
1178
1179 extern                  void
1180 efx_phy_unprobe(
1181         __in            efx_nic_t *enp);
1182
1183 #if EFSYS_OPT_VPD
1184
1185 /* VPD utility functions */
1186
1187 extern  __checkReturn           efx_rc_t
1188 efx_vpd_hunk_length(
1189         __in_bcount(size)       caddr_t data,
1190         __in                    size_t size,
1191         __out                   size_t *lengthp);
1192
1193 extern  __checkReturn           efx_rc_t
1194 efx_vpd_hunk_verify(
1195         __in_bcount(size)       caddr_t data,
1196         __in                    size_t size,
1197         __out_opt               boolean_t *cksummedp);
1198
1199 extern  __checkReturn           efx_rc_t
1200 efx_vpd_hunk_reinit(
1201         __in_bcount(size)       caddr_t data,
1202         __in                    size_t size,
1203         __in                    boolean_t wantpid);
1204
1205 extern  __checkReturn           efx_rc_t
1206 efx_vpd_hunk_get(
1207         __in_bcount(size)       caddr_t data,
1208         __in                    size_t size,
1209         __in                    efx_vpd_tag_t tag,
1210         __in                    efx_vpd_keyword_t keyword,
1211         __out                   unsigned int *payloadp,
1212         __out                   uint8_t *paylenp);
1213
1214 extern  __checkReturn                   efx_rc_t
1215 efx_vpd_hunk_next(
1216         __in_bcount(size)               caddr_t data,
1217         __in                            size_t size,
1218         __out                           efx_vpd_tag_t *tagp,
1219         __out                           efx_vpd_keyword_t *keyword,
1220         __out_opt                       unsigned int *payloadp,
1221         __out_opt                       uint8_t *paylenp,
1222         __inout                         unsigned int *contp);
1223
1224 extern  __checkReturn           efx_rc_t
1225 efx_vpd_hunk_set(
1226         __in_bcount(size)       caddr_t data,
1227         __in                    size_t size,
1228         __in                    efx_vpd_value_t *evvp);
1229
1230 #endif  /* EFSYS_OPT_VPD */
1231
1232 #if EFSYS_OPT_MCDI
1233
1234 extern  __checkReturn           efx_rc_t
1235 efx_mcdi_set_workaround(
1236         __in                    efx_nic_t *enp,
1237         __in                    uint32_t type,
1238         __in                    boolean_t enabled,
1239         __out_opt               uint32_t *flagsp);
1240
1241 extern  __checkReturn           efx_rc_t
1242 efx_mcdi_get_workarounds(
1243         __in                    efx_nic_t *enp,
1244         __out_opt               uint32_t *implementedp,
1245         __out_opt               uint32_t *enabledp);
1246
1247 #endif /* EFSYS_OPT_MCDI */
1248
1249 #if EFSYS_OPT_MAC_STATS
1250
1251 /*
1252  * Closed range of stats (i.e. the first and the last are included).
1253  * The last must be greater or equal (if the range is one item only) to
1254  * the first.
1255  */
1256 struct efx_mac_stats_range {
1257         efx_mac_stat_t          first;
1258         efx_mac_stat_t          last;
1259 };
1260
1261 extern                                  efx_rc_t
1262 efx_mac_stats_mask_add_ranges(
1263         __inout_bcount(mask_size)       uint32_t *maskp,
1264         __in                            size_t mask_size,
1265         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1266         __in                            unsigned int rng_count);
1267
1268 #endif  /* EFSYS_OPT_MAC_STATS */
1269
1270 #ifdef  __cplusplus
1271 }
1272 #endif
1273
1274 #endif  /* _SYS_EFX_IMPL_H */