drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13
  14 /* FIXME: Add definition for driver generated software events */
  15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  17 #endif
  18
  19
  20 #if EFSYS_OPT_SIENA
  21 #include "siena_impl.h"
  22 #endif  /* EFSYS_OPT_SIENA */
  23
  24 #if EFSYS_OPT_HUNTINGTON
  25 #include "hunt_impl.h"
  26 #endif  /* EFSYS_OPT_HUNTINGTON */
  27
  28 #if EFSYS_OPT_MEDFORD
  29 #include "medford_impl.h"
  30 #endif  /* EFSYS_OPT_MEDFORD */
  31
  32 #if EFSYS_OPT_MEDFORD2
  33 #include "medford2_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD2 */
  35
  36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
  37 #include "ef10_impl.h"
  38 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
  39
  40 #ifdef  __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 #define EFX_MOD_MCDI            0x00000001
  45 #define EFX_MOD_PROBE           0x00000002
  46 #define EFX_MOD_NVRAM           0x00000004
  47 #define EFX_MOD_VPD             0x00000008
  48 #define EFX_MOD_NIC             0x00000010
  49 #define EFX_MOD_INTR            0x00000020
  50 #define EFX_MOD_EV              0x00000040
  51 #define EFX_MOD_RX              0x00000080
  52 #define EFX_MOD_TX              0x00000100
  53 #define EFX_MOD_PORT            0x00000200
  54 #define EFX_MOD_MON             0x00000400
  55 #define EFX_MOD_FILTER          0x00001000
  56 #define EFX_MOD_LIC             0x00002000
  57 #define EFX_MOD_TUNNEL          0x00004000
  58
  59 #define EFX_RESET_PHY           0x00000001
  60 #define EFX_RESET_RXQ_ERR       0x00000002
  61 #define EFX_RESET_TXQ_ERR       0x00000004
  62
  63 typedef enum efx_mac_type_e {
  64         EFX_MAC_INVALID = 0,
  65         EFX_MAC_SIENA,
  66         EFX_MAC_HUNTINGTON,
  67         EFX_MAC_MEDFORD,
  68         EFX_MAC_MEDFORD2,
  69         EFX_MAC_NTYPES
  70 } efx_mac_type_t;
  71
  72 typedef struct efx_ev_ops_s {
  73         efx_rc_t        (*eevo_init)(efx_nic_t *);
  74         void            (*eevo_fini)(efx_nic_t *);
  75         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  76                                           efsys_mem_t *, size_t, uint32_t,
  77                                           uint32_t, uint32_t, efx_evq_t *);
  78         void            (*eevo_qdestroy)(efx_evq_t *);
  79         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  80         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  81         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  82 #if EFSYS_OPT_QSTATS
  83         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  84 #endif
  85 } efx_ev_ops_t;
  86
  87 typedef struct efx_tx_ops_s {
  88         efx_rc_t        (*etxo_init)(efx_nic_t *);
  89         void            (*etxo_fini)(efx_nic_t *);
  90         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  91                                         unsigned int, unsigned int,
  92                                         efsys_mem_t *, size_t,
  93                                         uint32_t, uint16_t,
  94                                         efx_evq_t *, efx_txq_t *,
  95                                         unsigned int *);
  96         void            (*etxo_qdestroy)(efx_txq_t *);
  97         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
  98                                       unsigned int, unsigned int,
  99                                       unsigned int *);
 100         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 101         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 102         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 103         void            (*etxo_qenable)(efx_txq_t *);
 104         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 105         void            (*etxo_qpio_disable)(efx_txq_t *);
 106         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 107                                            size_t);
 108         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 109                                            unsigned int *);
 110         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 111                                       unsigned int, unsigned int,
 112                                       unsigned int *);
 113         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 114                                                 size_t, boolean_t,
 115                                                 efx_desc_t *);
 116         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 117                                                 uint32_t, uint8_t,
 118                                                 efx_desc_t *);
 119         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 120                                                 uint16_t, uint32_t, uint16_t,
 121                                                 efx_desc_t *, int);
 122         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 123                                                 efx_desc_t *);
 124         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 125                                                 efx_desc_t *);
 126 #if EFSYS_OPT_QSTATS
 127         void            (*etxo_qstats_update)(efx_txq_t *,
 128                                               efsys_stat_t *);
 129 #endif
 130 } efx_tx_ops_t;
 131
 132 typedef union efx_rxq_type_data_u {
 133         /* Dummy member to have non-empty union if no options are enabled */
 134         uint32_t        ertd_dummy;
 135 #if EFSYS_OPT_RX_PACKED_STREAM
 136         struct {
 137                 uint32_t        eps_buf_size;
 138         } ertd_packed_stream;
 139 #endif
 140 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 141         struct {
 142                 uint32_t        eessb_bufs_per_desc;
 143                 uint32_t        eessb_max_dma_len;
 144                 uint32_t        eessb_buf_stride;
 145                 uint32_t        eessb_hol_block_timeout;
 146         } ertd_es_super_buffer;
 147 #endif
 148 } efx_rxq_type_data_t;
 149
 150 typedef struct efx_rx_ops_s {
 151         efx_rc_t        (*erxo_init)(efx_nic_t *);
 152         void            (*erxo_fini)(efx_nic_t *);
 153 #if EFSYS_OPT_RX_SCATTER
 154         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 155 #endif
 156 #if EFSYS_OPT_RX_SCALE
 157         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 158                                                     efx_rx_scale_context_type_t,
 159                                                     uint32_t, uint32_t *);
 160         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 161         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 162                                                efx_rx_hash_alg_t,
 163                                                efx_rx_hash_type_t, boolean_t);
 164         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 165                                               uint8_t *, size_t);
 166         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 167                                               unsigned int *, size_t);
 168         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 169                                             uint8_t *);
 170 #endif /* EFSYS_OPT_RX_SCALE */
 171         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 172                                               uint16_t *);
 173         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 174                                       unsigned int, unsigned int,
 175                                       unsigned int);
 176         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 177 #if EFSYS_OPT_RX_PACKED_STREAM
 178         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 179         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 180                                                 uint32_t, uint32_t,
 181                                                 uint16_t *, uint32_t *, uint32_t *);
 182 #endif
 183         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 184         void            (*erxo_qenable)(efx_rxq_t *);
 185         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 186                                         unsigned int, efx_rxq_type_t,
 187                                         const efx_rxq_type_data_t *,
 188                                         efsys_mem_t *, size_t, uint32_t,
 189                                         unsigned int,
 190                                         efx_evq_t *, efx_rxq_t *);
 191         void            (*erxo_qdestroy)(efx_rxq_t *);
 192 } efx_rx_ops_t;
 193
 194 typedef struct efx_mac_ops_s {
 195         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 196         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 197         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 198         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 199         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 200         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 201         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 202         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 203                                                       efx_rxq_t *, boolean_t);
 204         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 205 #if EFSYS_OPT_LOOPBACK
 206         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 207                                             efx_loopback_type_t);
 208 #endif  /* EFSYS_OPT_LOOPBACK */
 209 #if EFSYS_OPT_MAC_STATS
 210         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 211         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 212         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 213         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 214                                               uint16_t, boolean_t);
 215         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 216                                             efsys_stat_t *, uint32_t *);
 217 #endif  /* EFSYS_OPT_MAC_STATS */
 218 } efx_mac_ops_t;
 219
 220 typedef struct efx_phy_ops_s {
 221         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 222         efx_rc_t        (*epo_reset)(efx_nic_t *);
 223         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 224         efx_rc_t        (*epo_verify)(efx_nic_t *);
 225         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 226 #if EFSYS_OPT_PHY_STATS
 227         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 228                                             uint32_t *);
 229 #endif  /* EFSYS_OPT_PHY_STATS */
 230 #if EFSYS_OPT_BIST
 231         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 232         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 233         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 234                                          efx_bist_result_t *, uint32_t *,
 235                                          unsigned long *, size_t);
 236         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 237 #endif  /* EFSYS_OPT_BIST */
 238 } efx_phy_ops_t;
 239
 240 #if EFSYS_OPT_FILTER
 241 typedef struct efx_filter_ops_s {
 242         efx_rc_t        (*efo_init)(efx_nic_t *);
 243         void            (*efo_fini)(efx_nic_t *);
 244         efx_rc_t        (*efo_restore)(efx_nic_t *);
 245         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 246                                    boolean_t may_replace);
 247         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 248         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 249                                    size_t, size_t *);
 250         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 251                                    boolean_t, boolean_t, boolean_t,
 252                                    uint8_t const *, uint32_t);
 253 } efx_filter_ops_t;
 254
 255 extern  __checkReturn   efx_rc_t
 256 efx_filter_reconfigure(
 257         __in                            efx_nic_t *enp,
 258         __in_ecount(6)                  uint8_t const *mac_addr,
 259         __in                            boolean_t all_unicst,
 260         __in                            boolean_t mulcst,
 261         __in                            boolean_t all_mulcst,
 262         __in                            boolean_t brdcst,
 263         __in_ecount(6*count)            uint8_t const *addrs,
 264         __in                            uint32_t count);
 265
 266 #endif /* EFSYS_OPT_FILTER */
 267
 268 #if EFSYS_OPT_TUNNEL
 269 typedef struct efx_tunnel_ops_s {
 270         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 271         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 272 } efx_tunnel_ops_t;
 273 #endif /* EFSYS_OPT_TUNNEL */
 274
 275 typedef struct efx_port_s {
 276         efx_mac_type_t          ep_mac_type;
 277         uint32_t                ep_phy_type;
 278         uint8_t                 ep_port;
 279         uint32_t                ep_mac_pdu;
 280         uint8_t                 ep_mac_addr[6];
 281         efx_link_mode_t         ep_link_mode;
 282         boolean_t               ep_all_unicst;
 283         boolean_t               ep_mulcst;
 284         boolean_t               ep_all_mulcst;
 285         boolean_t               ep_brdcst;
 286         unsigned int            ep_fcntl;
 287         boolean_t               ep_fcntl_autoneg;
 288         efx_oword_t             ep_multicst_hash[2];
 289         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 290                                                     EFX_MAC_MULTICAST_LIST_MAX];
 291         uint32_t                ep_mulcst_addr_count;
 292 #if EFSYS_OPT_LOOPBACK
 293         efx_loopback_type_t     ep_loopback_type;
 294         efx_link_mode_t         ep_loopback_link_mode;
 295 #endif  /* EFSYS_OPT_LOOPBACK */
 296 #if EFSYS_OPT_PHY_FLAGS
 297         uint32_t                ep_phy_flags;
 298 #endif  /* EFSYS_OPT_PHY_FLAGS */
 299 #if EFSYS_OPT_PHY_LED_CONTROL
 300         efx_phy_led_mode_t      ep_phy_led_mode;
 301 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 302         efx_phy_media_type_t    ep_fixed_port_type;
 303         efx_phy_media_type_t    ep_module_type;
 304         uint32_t                ep_adv_cap_mask;
 305         uint32_t                ep_lp_cap_mask;
 306         uint32_t                ep_default_adv_cap_mask;
 307         uint32_t                ep_phy_cap_mask;
 308         boolean_t               ep_mac_drain;
 309 #if EFSYS_OPT_BIST
 310         efx_bist_type_t         ep_current_bist;
 311 #endif
 312         const efx_mac_ops_t     *ep_emop;
 313         const efx_phy_ops_t     *ep_epop;
 314 } efx_port_t;
 315
 316 typedef struct efx_mon_ops_s {
 317 #if EFSYS_OPT_MON_STATS
 318         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 319                                             efx_mon_stat_value_t *);
 320         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 321                                              efx_mon_stat_limits_t *);
 322 #endif  /* EFSYS_OPT_MON_STATS */
 323 } efx_mon_ops_t;
 324
 325 typedef struct efx_mon_s {
 326         efx_mon_type_t          em_type;
 327         const efx_mon_ops_t     *em_emop;
 328 } efx_mon_t;
 329
 330 typedef struct efx_intr_ops_s {
 331         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 332         void            (*eio_enable)(efx_nic_t *);
 333         void            (*eio_disable)(efx_nic_t *);
 334         void            (*eio_disable_unlocked)(efx_nic_t *);
 335         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 336         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 337         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 338                                  boolean_t *);
 339         void            (*eio_fatal)(efx_nic_t *);
 340         void            (*eio_fini)(efx_nic_t *);
 341 } efx_intr_ops_t;
 342
 343 typedef struct efx_intr_s {
 344         const efx_intr_ops_t    *ei_eiop;
 345         efsys_mem_t             *ei_esmp;
 346         efx_intr_type_t         ei_type;
 347         unsigned int            ei_level;
 348 } efx_intr_t;
 349
 350 typedef struct efx_nic_ops_s {
 351         efx_rc_t        (*eno_probe)(efx_nic_t *);
 352         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 353         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 354         efx_rc_t        (*eno_reset)(efx_nic_t *);
 355         efx_rc_t        (*eno_init)(efx_nic_t *);
 356         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 357         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 358                                         uint32_t *, size_t *);
 359 #if EFSYS_OPT_DIAG
 360         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 361 #endif  /* EFSYS_OPT_DIAG */
 362         void            (*eno_fini)(efx_nic_t *);
 363         void            (*eno_unprobe)(efx_nic_t *);
 364 } efx_nic_ops_t;
 365
 366 #ifndef EFX_TXQ_LIMIT_TARGET
 367 #define EFX_TXQ_LIMIT_TARGET 259
 368 #endif
 369 #ifndef EFX_RXQ_LIMIT_TARGET
 370 #define EFX_RXQ_LIMIT_TARGET 512
 371 #endif
 372
 373
 374 #if EFSYS_OPT_FILTER
 375
 376 #if EFSYS_OPT_SIENA
 377
 378 typedef struct siena_filter_spec_s {
 379         uint8_t         sfs_type;
 380         uint32_t        sfs_flags;
 381         uint32_t        sfs_dmaq_id;
 382         uint32_t        sfs_dword[3];
 383 } siena_filter_spec_t;
 384
 385 typedef enum siena_filter_type_e {
 386         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 387         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 388         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 389         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 390         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 391         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 392
 393         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 394         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 395         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 396         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 397         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 398         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 399
 400         EFX_SIENA_FILTER_NTYPES
 401 } siena_filter_type_t;
 402
 403 typedef enum siena_filter_tbl_id_e {
 404         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 405         EFX_SIENA_FILTER_TBL_RX_MAC,
 406         EFX_SIENA_FILTER_TBL_TX_IP,
 407         EFX_SIENA_FILTER_TBL_TX_MAC,
 408         EFX_SIENA_FILTER_NTBLS
 409 } siena_filter_tbl_id_t;
 410
 411 typedef struct siena_filter_tbl_s {
 412         int                     sft_size;       /* number of entries */
 413         int                     sft_used;       /* active count */
 414         uint32_t                *sft_bitmap;    /* active bitmap */
 415         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 416 } siena_filter_tbl_t;
 417
 418 typedef struct siena_filter_s {
 419         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 420         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 421 } siena_filter_t;
 422
 423 #endif  /* EFSYS_OPT_SIENA */
 424
 425 typedef struct efx_filter_s {
 426 #if EFSYS_OPT_SIENA
 427         siena_filter_t          *ef_siena_filter;
 428 #endif /* EFSYS_OPT_SIENA */
 429 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 430         ef10_filter_table_t     *ef_ef10_filter_table;
 431 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 432 } efx_filter_t;
 433
 434 #if EFSYS_OPT_SIENA
 435
 436 extern                  void
 437 siena_filter_tbl_clear(
 438         __in            efx_nic_t *enp,
 439         __in            siena_filter_tbl_id_t tbl);
 440
 441 #endif  /* EFSYS_OPT_SIENA */
 442
 443 #endif  /* EFSYS_OPT_FILTER */
 444
 445 #if EFSYS_OPT_MCDI
 446
 447 #define EFX_TUNNEL_MAXNENTRIES  (16)
 448
 449 #if EFSYS_OPT_TUNNEL
 450
 451 typedef struct efx_tunnel_udp_entry_s {
 452         uint16_t                        etue_port; /* host/cpu-endian */
 453         uint16_t                        etue_protocol;
 454 } efx_tunnel_udp_entry_t;
 455
 456 typedef struct efx_tunnel_cfg_s {
 457         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 458         unsigned int            etc_udp_entries_num;
 459 } efx_tunnel_cfg_t;
 460
 461 #endif /* EFSYS_OPT_TUNNEL */
 462
 463 typedef struct efx_mcdi_ops_s {
 464         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 465         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 466                                         void *, size_t);
 467         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 468         boolean_t       (*emco_poll_response)(efx_nic_t *);
 469         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 470         void            (*emco_fini)(efx_nic_t *);
 471         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 472                                             efx_mcdi_feature_id_t, boolean_t *);
 473         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 474                                             uint32_t *);
 475 } efx_mcdi_ops_t;
 476
 477 typedef struct efx_mcdi_s {
 478         const efx_mcdi_ops_t            *em_emcop;
 479         const efx_mcdi_transport_t      *em_emtp;
 480         efx_mcdi_iface_t                em_emip;
 481 } efx_mcdi_t;
 482
 483 #endif /* EFSYS_OPT_MCDI */
 484
 485 #if EFSYS_OPT_NVRAM
 486
 487 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 488 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 489
 490 typedef struct efx_nvram_ops_s {
 491 #if EFSYS_OPT_DIAG
 492         efx_rc_t        (*envo_test)(efx_nic_t *);
 493 #endif  /* EFSYS_OPT_DIAG */
 494         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 495                                             uint32_t *);
 496         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 497         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 498         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 499                                             unsigned int, caddr_t, size_t);
 500         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 501                                             unsigned int, caddr_t, size_t);
 502         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 503                                             unsigned int, size_t);
 504         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 505                                             unsigned int, caddr_t, size_t);
 506         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 507                                             uint32_t *);
 508         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 509                                             uint32_t *, uint16_t *);
 510         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 511                                             uint16_t *);
 512         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 513                                             caddr_t, size_t);
 514 } efx_nvram_ops_t;
 515 #endif /* EFSYS_OPT_NVRAM */
 516
 517 #if EFSYS_OPT_VPD
 518 typedef struct efx_vpd_ops_s {
 519         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 520         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 521         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 522         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 523         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 524         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 525                                         efx_vpd_value_t *);
 526         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 527                                         efx_vpd_value_t *);
 528         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 529                                         efx_vpd_value_t *, unsigned int *);
 530         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 531         void            (*evpdo_fini)(efx_nic_t *);
 532 } efx_vpd_ops_t;
 533 #endif  /* EFSYS_OPT_VPD */
 534
 535 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 536
 537         __checkReturn           efx_rc_t
 538 efx_mcdi_nvram_partitions(
 539         __in                    efx_nic_t *enp,
 540         __out_bcount(size)      caddr_t data,
 541         __in                    size_t size,
 542         __out                   unsigned int *npartnp);
 543
 544         __checkReturn           efx_rc_t
 545 efx_mcdi_nvram_metadata(
 546         __in                    efx_nic_t *enp,
 547         __in                    uint32_t partn,
 548         __out                   uint32_t *subtypep,
 549         __out_ecount(4)         uint16_t version[4],
 550         __out_bcount_opt(size)  char *descp,
 551         __in                    size_t size);
 552
 553         __checkReturn           efx_rc_t
 554 efx_mcdi_nvram_info(
 555         __in                    efx_nic_t *enp,
 556         __in                    uint32_t partn,
 557         __out_opt               size_t *sizep,
 558         __out_opt               uint32_t *addressp,
 559         __out_opt               uint32_t *erase_sizep,
 560         __out_opt               uint32_t *write_sizep);
 561
 562         __checkReturn           efx_rc_t
 563 efx_mcdi_nvram_update_start(
 564         __in                    efx_nic_t *enp,
 565         __in                    uint32_t partn);
 566
 567         __checkReturn           efx_rc_t
 568 efx_mcdi_nvram_read(
 569         __in                    efx_nic_t *enp,
 570         __in                    uint32_t partn,
 571         __in                    uint32_t offset,
 572         __out_bcount(size)      caddr_t data,
 573         __in                    size_t size,
 574         __in                    uint32_t mode);
 575
 576         __checkReturn           efx_rc_t
 577 efx_mcdi_nvram_erase(
 578         __in                    efx_nic_t *enp,
 579         __in                    uint32_t partn,
 580         __in                    uint32_t offset,
 581         __in                    size_t size);
 582
 583         __checkReturn           efx_rc_t
 584 efx_mcdi_nvram_write(
 585         __in                    efx_nic_t *enp,
 586         __in                    uint32_t partn,
 587         __in                    uint32_t offset,
 588         __in_bcount(size)       caddr_t data,
 589         __in                    size_t size);
 590
 591         __checkReturn           efx_rc_t
 592 efx_mcdi_nvram_update_finish(
 593         __in                    efx_nic_t *enp,
 594         __in                    uint32_t partn,
 595         __in                    boolean_t reboot,
 596         __out_opt               uint32_t *verify_resultp);
 597
 598 #if EFSYS_OPT_DIAG
 599
 600         __checkReturn           efx_rc_t
 601 efx_mcdi_nvram_test(
 602         __in                    efx_nic_t *enp,
 603         __in                    uint32_t partn);
 604
 605 #endif  /* EFSYS_OPT_DIAG */
 606
 607 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 608
 609 #if EFSYS_OPT_LICENSING
 610
 611 typedef struct efx_lic_ops_s {
 612         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 613         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 614         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 615         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 616                                       size_t *, uint8_t *);
 617         efx_rc_t        (*elo_find_start)
 618                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 619         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 620                                 uint32_t, uint32_t *);
 621         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 622                                 uint32_t, uint32_t *, uint32_t *);
 623         boolean_t       (*elo_validate_key)(efx_nic_t *,
 624                                 caddr_t, uint32_t);
 625         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 626                                 caddr_t, size_t, uint32_t, uint32_t,
 627                                 caddr_t, size_t, uint32_t *);
 628         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 629                                 caddr_t, size_t, uint32_t,
 630                                 caddr_t, uint32_t, uint32_t *);
 631         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 632                                 caddr_t, size_t, uint32_t,
 633                                 uint32_t, uint32_t, uint32_t *);
 634         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 635                                 caddr_t, size_t);
 636         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 637                                 caddr_t, size_t);
 638 } efx_lic_ops_t;
 639
 640 #endif
 641
 642 typedef struct efx_drv_cfg_s {
 643         uint32_t                edc_min_vi_count;
 644         uint32_t                edc_max_vi_count;
 645
 646         uint32_t                edc_max_piobuf_count;
 647         uint32_t                edc_pio_alloc_size;
 648 } efx_drv_cfg_t;
 649
 650 struct efx_nic_s {
 651         uint32_t                en_magic;
 652         efx_family_t            en_family;
 653         uint32_t                en_features;
 654         efsys_identifier_t      *en_esip;
 655         efsys_lock_t            *en_eslp;
 656         efsys_bar_t             *en_esbp;
 657         unsigned int            en_mod_flags;
 658         unsigned int            en_reset_flags;
 659         efx_nic_cfg_t           en_nic_cfg;
 660         efx_drv_cfg_t           en_drv_cfg;
 661         efx_port_t              en_port;
 662         efx_mon_t               en_mon;
 663         efx_intr_t              en_intr;
 664         uint32_t                en_ev_qcount;
 665         uint32_t                en_rx_qcount;
 666         uint32_t                en_tx_qcount;
 667         const efx_nic_ops_t     *en_enop;
 668         const efx_ev_ops_t      *en_eevop;
 669         const efx_tx_ops_t      *en_etxop;
 670         const efx_rx_ops_t      *en_erxop;
 671         efx_fw_variant_t        efv;
 672 #if EFSYS_OPT_FILTER
 673         efx_filter_t            en_filter;
 674         const efx_filter_ops_t  *en_efop;
 675 #endif  /* EFSYS_OPT_FILTER */
 676 #if EFSYS_OPT_TUNNEL
 677         efx_tunnel_cfg_t        en_tunnel_cfg;
 678         const efx_tunnel_ops_t  *en_etop;
 679 #endif /* EFSYS_OPT_TUNNEL */
 680 #if EFSYS_OPT_MCDI
 681         efx_mcdi_t              en_mcdi;
 682 #endif  /* EFSYS_OPT_MCDI */
 683 #if EFSYS_OPT_NVRAM
 684         uint32_t                en_nvram_partn_locked;
 685         const efx_nvram_ops_t   *en_envop;
 686 #endif  /* EFSYS_OPT_NVRAM */
 687 #if EFSYS_OPT_VPD
 688         const efx_vpd_ops_t     *en_evpdop;
 689 #endif  /* EFSYS_OPT_VPD */
 690 #if EFSYS_OPT_RX_SCALE
 691         efx_rx_hash_support_t           en_hash_support;
 692         efx_rx_scale_context_type_t     en_rss_context_type;
 693         uint32_t                        en_rss_context;
 694 #endif  /* EFSYS_OPT_RX_SCALE */
 695         uint32_t                en_vport_id;
 696 #if EFSYS_OPT_LICENSING
 697         const efx_lic_ops_t     *en_elop;
 698         boolean_t               en_licensing_supported;
 699 #endif
 700         union {
 701 #if EFSYS_OPT_SIENA
 702                 struct {
 703 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 704                         unsigned int            enu_partn_mask;
 705 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 706 #if EFSYS_OPT_VPD
 707                         caddr_t                 enu_svpd;
 708                         size_t                  enu_svpd_length;
 709 #endif  /* EFSYS_OPT_VPD */
 710                         int                     enu_unused;
 711                 } siena;
 712 #endif  /* EFSYS_OPT_SIENA */
 713                 int     enu_unused;
 714         } en_u;
 715 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
 716         union en_arch {
 717                 struct {
 718                         int                     ena_vi_base;
 719                         int                     ena_vi_count;
 720                         int                     ena_vi_shift;
 721 #if EFSYS_OPT_VPD
 722                         caddr_t                 ena_svpd;
 723                         size_t                  ena_svpd_length;
 724 #endif  /* EFSYS_OPT_VPD */
 725                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 726                         uint32_t                ena_piobuf_count;
 727                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 728                         uint32_t                ena_pio_write_vi_base;
 729                         /* Memory BAR mapping regions */
 730                         uint32_t                ena_uc_mem_map_offset;
 731                         size_t                  ena_uc_mem_map_size;
 732                         uint32_t                ena_wc_mem_map_offset;
 733                         size_t                  ena_wc_mem_map_size;
 734                 } ef10;
 735         } en_arch;
 736 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 737 };
 738
 739
 740 #define EFX_NIC_MAGIC   0x02121996
 741
 742 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 743     const efx_ev_callbacks_t *, void *);
 744
 745 typedef struct efx_evq_rxq_state_s {
 746         unsigned int                    eers_rx_read_ptr;
 747         unsigned int                    eers_rx_mask;
 748 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 749         unsigned int                    eers_rx_stream_npackets;
 750         boolean_t                       eers_rx_packed_stream;
 751 #endif
 752 #if EFSYS_OPT_RX_PACKED_STREAM
 753         unsigned int                    eers_rx_packed_stream_credits;
 754 #endif
 755 } efx_evq_rxq_state_t;
 756
 757 struct efx_evq_s {
 758         uint32_t                        ee_magic;
 759         efx_nic_t                       *ee_enp;
 760         unsigned int                    ee_index;
 761         unsigned int                    ee_mask;
 762         efsys_mem_t                     *ee_esmp;
 763 #if EFSYS_OPT_QSTATS
 764         uint32_t                        ee_stat[EV_NQSTATS];
 765 #endif  /* EFSYS_OPT_QSTATS */
 766
 767         efx_ev_handler_t                ee_rx;
 768         efx_ev_handler_t                ee_tx;
 769         efx_ev_handler_t                ee_driver;
 770         efx_ev_handler_t                ee_global;
 771         efx_ev_handler_t                ee_drv_gen;
 772 #if EFSYS_OPT_MCDI
 773         efx_ev_handler_t                ee_mcdi;
 774 #endif  /* EFSYS_OPT_MCDI */
 775
 776         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 777
 778         uint32_t                        ee_flags;
 779 };
 780
 781 #define EFX_EVQ_MAGIC   0x08081997
 782
 783 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 784
 785 struct efx_rxq_s {
 786         uint32_t                        er_magic;
 787         efx_nic_t                       *er_enp;
 788         efx_evq_t                       *er_eep;
 789         unsigned int                    er_index;
 790         unsigned int                    er_label;
 791         unsigned int                    er_mask;
 792         efsys_mem_t                     *er_esmp;
 793         efx_evq_rxq_state_t             *er_ev_qstate;
 794 };
 795
 796 #define EFX_RXQ_MAGIC   0x15022005
 797
 798 struct efx_txq_s {
 799         uint32_t                        et_magic;
 800         efx_nic_t                       *et_enp;
 801         unsigned int                    et_index;
 802         unsigned int                    et_mask;
 803         efsys_mem_t                     *et_esmp;
 804 #if EFSYS_OPT_HUNTINGTON
 805         uint32_t                        et_pio_bufnum;
 806         uint32_t                        et_pio_blknum;
 807         uint32_t                        et_pio_write_offset;
 808         uint32_t                        et_pio_offset;
 809         size_t                          et_pio_size;
 810 #endif
 811 #if EFSYS_OPT_QSTATS
 812         uint32_t                        et_stat[TX_NQSTATS];
 813 #endif  /* EFSYS_OPT_QSTATS */
 814 };
 815
 816 #define EFX_TXQ_MAGIC   0x05092005
 817
 818 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 819         do {                                                            \
 820                 (_dst)[0] = (_src)[0];                                  \
 821                 (_dst)[1] = (_src)[1];                                  \
 822                 (_dst)[2] = (_src)[2];                                  \
 823                 (_dst)[3] = (_src)[3];                                  \
 824                 (_dst)[4] = (_src)[4];                                  \
 825                 (_dst)[5] = (_src)[5];                                  \
 826         _NOTE(CONSTANTCONDITION)                                        \
 827         } while (B_FALSE)
 828
 829 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 830         do {                                                            \
 831                 uint16_t *_d = (uint16_t *)(_dst);                      \
 832                 _d[0] = 0xffff;                                         \
 833                 _d[1] = 0xffff;                                         \
 834                 _d[2] = 0xffff;                                         \
 835         _NOTE(CONSTANTCONDITION)                                        \
 836         } while (B_FALSE)
 837
 838 #if EFSYS_OPT_CHECK_REG
 839 #define EFX_CHECK_REG(_enp, _reg)                                       \
 840         do {                                                            \
 841                 const char *name = #_reg;                               \
 842                 char min = name[4];                                     \
 843                 char max = name[5];                                     \
 844                 char rev;                                               \
 845                                                                         \
 846                 switch ((_enp)->en_family) {                            \
 847                 case EFX_FAMILY_SIENA:                                  \
 848                         rev = 'C';                                      \
 849                         break;                                          \
 850                                                                         \
 851                 case EFX_FAMILY_HUNTINGTON:                             \
 852                         rev = 'D';                                      \
 853                         break;                                          \
 854                                                                         \
 855                 case EFX_FAMILY_MEDFORD:                                \
 856                         rev = 'E';                                      \
 857                         break;                                          \
 858                                                                         \
 859                 case EFX_FAMILY_MEDFORD2:                               \
 860                         rev = 'F';                                      \
 861                         break;                                          \
 862                                                                         \
 863                 default:                                                \
 864                         rev = '?';                                      \
 865                         break;                                          \
 866                 }                                                       \
 867                                                                         \
 868                 EFSYS_ASSERT3S(rev, >=, min);                           \
 869                 EFSYS_ASSERT3S(rev, <=, max);                           \
 870                                                                         \
 871         _NOTE(CONSTANTCONDITION)                                        \
 872         } while (B_FALSE)
 873 #else
 874 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 875         _NOTE(CONSTANTCONDITION)                                        \
 876         } while (B_FALSE)
 877 #endif
 878
 879 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 880         do {                                                            \
 881                 EFX_CHECK_REG((_enp), (_reg));                          \
 882                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 883                     (_edp), (_lock));                                   \
 884                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 885                     uint32_t, _reg ## _OFST,                            \
 886                     uint32_t, (_edp)->ed_u32[0]);                       \
 887         _NOTE(CONSTANTCONDITION)                                        \
 888         } while (B_FALSE)
 889
 890 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 891         do {                                                            \
 892                 EFX_CHECK_REG((_enp), (_reg));                          \
 893                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 894                     uint32_t, _reg ## _OFST,                            \
 895                     uint32_t, (_edp)->ed_u32[0]);                       \
 896                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 897                     (_edp), (_lock));                                   \
 898         _NOTE(CONSTANTCONDITION)                                        \
 899         } while (B_FALSE)
 900
 901 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 902         do {                                                            \
 903                 EFX_CHECK_REG((_enp), (_reg));                          \
 904                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 905                     (_eqp));                                            \
 906                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 907                     uint32_t, _reg ## _OFST,                            \
 908                     uint32_t, (_eqp)->eq_u32[1],                        \
 909                     uint32_t, (_eqp)->eq_u32[0]);                       \
 910         _NOTE(CONSTANTCONDITION)                                        \
 911         } while (B_FALSE)
 912
 913 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 914         do {                                                            \
 915                 EFX_CHECK_REG((_enp), (_reg));                          \
 916                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 917                     uint32_t, _reg ## _OFST,                            \
 918                     uint32_t, (_eqp)->eq_u32[1],                        \
 919                     uint32_t, (_eqp)->eq_u32[0]);                       \
 920                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 921                     (_eqp));                                            \
 922         _NOTE(CONSTANTCONDITION)                                        \
 923         } while (B_FALSE)
 924
 925 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 926         do {                                                            \
 927                 EFX_CHECK_REG((_enp), (_reg));                          \
 928                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 929                     (_eop), B_TRUE);                                    \
 930                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 931                     uint32_t, _reg ## _OFST,                            \
 932                     uint32_t, (_eop)->eo_u32[3],                        \
 933                     uint32_t, (_eop)->eo_u32[2],                        \
 934                     uint32_t, (_eop)->eo_u32[1],                        \
 935                     uint32_t, (_eop)->eo_u32[0]);                       \
 936         _NOTE(CONSTANTCONDITION)                                        \
 937         } while (B_FALSE)
 938
 939 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 940         do {                                                            \
 941                 EFX_CHECK_REG((_enp), (_reg));                          \
 942                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 943                     uint32_t, _reg ## _OFST,                            \
 944                     uint32_t, (_eop)->eo_u32[3],                        \
 945                     uint32_t, (_eop)->eo_u32[2],                        \
 946                     uint32_t, (_eop)->eo_u32[1],                        \
 947                     uint32_t, (_eop)->eo_u32[0]);                       \
 948                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 949                     (_eop), B_TRUE);                                    \
 950         _NOTE(CONSTANTCONDITION)                                        \
 951         } while (B_FALSE)
 952
 953 /*
 954  * Accessors for memory BAR non-VI tables.
 955  *
 956  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
 957  * to ensure the correct runtime VI window size is used on Medford2.
 958  *
 959  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
 960  */
 961
 962 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 963         do {                                                            \
 964                 EFX_CHECK_REG((_enp), (_reg));                          \
 965                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 966                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 967                     (_edp), (_lock));                                   \
 968                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 969                     uint32_t, (_index),                                 \
 970                     uint32_t, _reg ## _OFST,                            \
 971                     uint32_t, (_edp)->ed_u32[0]);                       \
 972         _NOTE(CONSTANTCONDITION)                                        \
 973         } while (B_FALSE)
 974
 975 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 976         do {                                                            \
 977                 EFX_CHECK_REG((_enp), (_reg));                          \
 978                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 979                     uint32_t, (_index),                                 \
 980                     uint32_t, _reg ## _OFST,                            \
 981                     uint32_t, (_edp)->ed_u32[0]);                       \
 982                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 983                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 984                     (_edp), (_lock));                                   \
 985         _NOTE(CONSTANTCONDITION)                                        \
 986         } while (B_FALSE)
 987
 988 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 989         do {                                                            \
 990                 EFX_CHECK_REG((_enp), (_reg));                          \
 991                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 992                     uint32_t, (_index),                                 \
 993                     uint32_t, _reg ## _OFST,                            \
 994                     uint32_t, (_edp)->ed_u32[0]);                       \
 995                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 996                     (_reg ## _OFST +                                    \
 997                     (3 * sizeof (efx_dword_t)) +                        \
 998                     ((_index) * _reg ## _STEP)),                        \
 999                     (_edp), (_lock));                                   \
1000         _NOTE(CONSTANTCONDITION)                                        \
1001         } while (B_FALSE)
1002
1003 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1004         do {                                                            \
1005                 EFX_CHECK_REG((_enp), (_reg));                          \
1006                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1007                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1008                     (_eqp));                                            \
1009                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1010                     uint32_t, (_index),                                 \
1011                     uint32_t, _reg ## _OFST,                            \
1012                     uint32_t, (_eqp)->eq_u32[1],                        \
1013                     uint32_t, (_eqp)->eq_u32[0]);                       \
1014         _NOTE(CONSTANTCONDITION)                                        \
1015         } while (B_FALSE)
1016
1017 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1018         do {                                                            \
1019                 EFX_CHECK_REG((_enp), (_reg));                          \
1020                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1021                     uint32_t, (_index),                                 \
1022                     uint32_t, _reg ## _OFST,                            \
1023                     uint32_t, (_eqp)->eq_u32[1],                        \
1024                     uint32_t, (_eqp)->eq_u32[0]);                       \
1025                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1026                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1027                     (_eqp));                                            \
1028         _NOTE(CONSTANTCONDITION)                                        \
1029         } while (B_FALSE)
1030
1031 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1032         do {                                                            \
1033                 EFX_CHECK_REG((_enp), (_reg));                          \
1034                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1035                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1036                     (_eop), (_lock));                                   \
1037                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1038                     uint32_t, (_index),                                 \
1039                     uint32_t, _reg ## _OFST,                            \
1040                     uint32_t, (_eop)->eo_u32[3],                        \
1041                     uint32_t, (_eop)->eo_u32[2],                        \
1042                     uint32_t, (_eop)->eo_u32[1],                        \
1043                     uint32_t, (_eop)->eo_u32[0]);                       \
1044         _NOTE(CONSTANTCONDITION)                                        \
1045         } while (B_FALSE)
1046
1047 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1048         do {                                                            \
1049                 EFX_CHECK_REG((_enp), (_reg));                          \
1050                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1051                     uint32_t, (_index),                                 \
1052                     uint32_t, _reg ## _OFST,                            \
1053                     uint32_t, (_eop)->eo_u32[3],                        \
1054                     uint32_t, (_eop)->eo_u32[2],                        \
1055                     uint32_t, (_eop)->eo_u32[1],                        \
1056                     uint32_t, (_eop)->eo_u32[0]);                       \
1057                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1058                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1059                     (_eop), (_lock));                                   \
1060         _NOTE(CONSTANTCONDITION)                                        \
1061         } while (B_FALSE)
1062
1063 /*
1064  * Accessors for memory BAR per-VI registers.
1065  *
1066  * The VI window size is 8KB for Medford and all earlier controllers.
1067  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1068  */
1069
1070 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1071         do {                                                            \
1072                 EFX_CHECK_REG((_enp), (_reg));                          \
1073                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1074                     ((_reg ## _OFST) +                                  \
1075                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1076                     (_edp), (_lock));                                   \
1077                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1078                     uint32_t, (_index),                                 \
1079                     uint32_t, _reg ## _OFST,                            \
1080                     uint32_t, (_edp)->ed_u32[0]);                       \
1081         _NOTE(CONSTANTCONDITION)                                        \
1082         } while (B_FALSE)
1083
1084 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1085         do {                                                            \
1086                 EFX_CHECK_REG((_enp), (_reg));                          \
1087                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1088                     uint32_t, (_index),                                 \
1089                     uint32_t, _reg ## _OFST,                            \
1090                     uint32_t, (_edp)->ed_u32[0]);                       \
1091                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1092                     ((_reg ## _OFST) +                                  \
1093                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1094                     (_edp), (_lock));                                   \
1095         _NOTE(CONSTANTCONDITION)                                        \
1096         } while (B_FALSE)
1097
1098 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1099         do {                                                            \
1100                 EFX_CHECK_REG((_enp), (_reg));                          \
1101                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1102                     uint32_t, (_index),                                 \
1103                     uint32_t, _reg ## _OFST,                            \
1104                     uint32_t, (_edp)->ed_u32[0]);                       \
1105                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1106                     ((_reg ## _OFST) +                                  \
1107                     (2 * sizeof (efx_dword_t)) +                        \
1108                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1109                     (_edp), (_lock));                                   \
1110         _NOTE(CONSTANTCONDITION)                                        \
1111         } while (B_FALSE)
1112
1113 /*
1114  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1115  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1116  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1117  * the need for locking in the host, and are the only ones known to be safe to
1118  * use 128-bites write with.
1119  */
1120 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1121         do {                                                            \
1122                 EFX_CHECK_REG((_enp), (_reg));                          \
1123                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1124                     const char *, #_reg,                                \
1125                     uint32_t, (_index),                                 \
1126                     uint32_t, _reg ## _OFST,                            \
1127                     uint32_t, (_eop)->eo_u32[3],                        \
1128                     uint32_t, (_eop)->eo_u32[2],                        \
1129                     uint32_t, (_eop)->eo_u32[1],                        \
1130                     uint32_t, (_eop)->eo_u32[0]);                       \
1131                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1132                     (_reg ## _OFST +                                    \
1133                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1134                     (_eop));                                            \
1135         _NOTE(CONSTANTCONDITION)                                        \
1136         } while (B_FALSE)
1137
1138 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1139         do {                                                            \
1140                 unsigned int _new = (_wptr);                            \
1141                 unsigned int _old = (_owptr);                           \
1142                                                                         \
1143                 if ((_new) >= (_old))                                   \
1144                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1145                             (_old) * sizeof (efx_desc_t),               \
1146                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1147                 else                                                    \
1148                         /*                                              \
1149                          * It is cheaper to sync entire map than sync   \
1150                          * two parts especially when offset/size are    \
1151                          * ignored and entire map is synced in any case.\
1152                          */                                             \
1153                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1154                             0,                                          \
1155                             (_entries) * sizeof (efx_desc_t));          \
1156         _NOTE(CONSTANTCONDITION)                                        \
1157         } while (B_FALSE)
1158
1159 extern  __checkReturn   efx_rc_t
1160 efx_mac_select(
1161         __in            efx_nic_t *enp);
1162
1163 extern  void
1164 efx_mac_multicast_hash_compute(
1165         __in_ecount(6*count)            uint8_t const *addrs,
1166         __in                            int count,
1167         __out                           efx_oword_t *hash_low,
1168         __out                           efx_oword_t *hash_high);
1169
1170 extern  __checkReturn   efx_rc_t
1171 efx_phy_probe(
1172         __in            efx_nic_t *enp);
1173
1174 extern                  void
1175 efx_phy_unprobe(
1176         __in            efx_nic_t *enp);
1177
1178 #if EFSYS_OPT_VPD
1179
1180 /* VPD utility functions */
1181
1182 extern  __checkReturn           efx_rc_t
1183 efx_vpd_hunk_length(
1184         __in_bcount(size)       caddr_t data,
1185         __in                    size_t size,
1186         __out                   size_t *lengthp);
1187
1188 extern  __checkReturn           efx_rc_t
1189 efx_vpd_hunk_verify(
1190         __in_bcount(size)       caddr_t data,
1191         __in                    size_t size,
1192         __out_opt               boolean_t *cksummedp);
1193
1194 extern  __checkReturn           efx_rc_t
1195 efx_vpd_hunk_reinit(
1196         __in_bcount(size)       caddr_t data,
1197         __in                    size_t size,
1198         __in                    boolean_t wantpid);
1199
1200 extern  __checkReturn           efx_rc_t
1201 efx_vpd_hunk_get(
1202         __in_bcount(size)       caddr_t data,
1203         __in                    size_t size,
1204         __in                    efx_vpd_tag_t tag,
1205         __in                    efx_vpd_keyword_t keyword,
1206         __out                   unsigned int *payloadp,
1207         __out                   uint8_t *paylenp);
1208
1209 extern  __checkReturn                   efx_rc_t
1210 efx_vpd_hunk_next(
1211         __in_bcount(size)               caddr_t data,
1212         __in                            size_t size,
1213         __out                           efx_vpd_tag_t *tagp,
1214         __out                           efx_vpd_keyword_t *keyword,
1215         __out_opt                       unsigned int *payloadp,
1216         __out_opt                       uint8_t *paylenp,
1217         __inout                         unsigned int *contp);
1218
1219 extern  __checkReturn           efx_rc_t
1220 efx_vpd_hunk_set(
1221         __in_bcount(size)       caddr_t data,
1222         __in                    size_t size,
1223         __in                    efx_vpd_value_t *evvp);
1224
1225 #endif  /* EFSYS_OPT_VPD */
1226
1227 #if EFSYS_OPT_MCDI
1228
1229 extern  __checkReturn           efx_rc_t
1230 efx_mcdi_set_workaround(
1231         __in                    efx_nic_t *enp,
1232         __in                    uint32_t type,
1233         __in                    boolean_t enabled,
1234         __out_opt               uint32_t *flagsp);
1235
1236 extern  __checkReturn           efx_rc_t
1237 efx_mcdi_get_workarounds(
1238         __in                    efx_nic_t *enp,
1239         __out_opt               uint32_t *implementedp,
1240         __out_opt               uint32_t *enabledp);
1241
1242 #endif /* EFSYS_OPT_MCDI */
1243
1244 #if EFSYS_OPT_MAC_STATS
1245
1246 /*
1247  * Closed range of stats (i.e. the first and the last are included).
1248  * The last must be greater or equal (if the range is one item only) to
1249  * the first.
1250  */
1251 struct efx_mac_stats_range {
1252         efx_mac_stat_t          first;
1253         efx_mac_stat_t          last;
1254 };
1255
1256 extern                                  efx_rc_t
1257 efx_mac_stats_mask_add_ranges(
1258         __inout_bcount(mask_size)       uint32_t *maskp,
1259         __in                            size_t mask_size,
1260         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1261         __in                            unsigned int rng_count);
1262
1263 #endif  /* EFSYS_OPT_MAC_STATS */
1264
1265 #ifdef  __cplusplus
1266 }
1267 #endif
1268
1269 #endif  /* _SYS_EFX_IMPL_H */