drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154 #if EFSYS_OPT_RX_SCALE
 155         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 156                                                     efx_rx_scale_context_type_t,
 157                                                     uint32_t, uint32_t *);
 158         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 159         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 160                                                efx_rx_hash_alg_t,
 161                                                efx_rx_hash_type_t, boolean_t);
 162         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 163                                               uint8_t *, size_t);
 164         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 165                                               unsigned int *, size_t);
 166         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 167                                             uint8_t *);
 168 #endif /* EFSYS_OPT_RX_SCALE */
 169         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 170                                               uint16_t *);
 171         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 172                                       unsigned int, unsigned int,
 173                                       unsigned int);
 174         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 175 #if EFSYS_OPT_RX_PACKED_STREAM
 176         void            (*erxo_qps_update_credits)(efx_rxq_t *);
 177         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 178                                                 uint32_t, uint32_t,
 179                                                 uint16_t *, uint32_t *, uint32_t *);
 180 #endif
 181         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 182         void            (*erxo_qenable)(efx_rxq_t *);
 183         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 184                                         unsigned int, efx_rxq_type_t,
 185                                         efsys_mem_t *, size_t, uint32_t,
 186                                         efx_evq_t *, efx_rxq_t *);
 187         void            (*erxo_qdestroy)(efx_rxq_t *);
 188 } efx_rx_ops_t;
 189
 190 typedef struct efx_mac_ops_s {
 191         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 192         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 193         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 194         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 195         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 196         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 197         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 198         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 199                                                       efx_rxq_t *, boolean_t);
 200         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 201 #if EFSYS_OPT_LOOPBACK
 202         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 203                                             efx_loopback_type_t);
 204 #endif  /* EFSYS_OPT_LOOPBACK */
 205 #if EFSYS_OPT_MAC_STATS
 206         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 207         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 208         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 209         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 210                                               uint16_t, boolean_t);
 211         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 212                                             efsys_stat_t *, uint32_t *);
 213 #endif  /* EFSYS_OPT_MAC_STATS */
 214 } efx_mac_ops_t;
 215
 216 typedef struct efx_phy_ops_s {
 217         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 218         efx_rc_t        (*epo_reset)(efx_nic_t *);
 219         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 220         efx_rc_t        (*epo_verify)(efx_nic_t *);
 221         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 222 #if EFSYS_OPT_PHY_STATS
 223         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 224                                             uint32_t *);
 225 #endif  /* EFSYS_OPT_PHY_STATS */
 226 #if EFSYS_OPT_BIST
 227         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 228         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 229         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 230                                          efx_bist_result_t *, uint32_t *,
 231                                          unsigned long *, size_t);
 232         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 233 #endif  /* EFSYS_OPT_BIST */
 234 } efx_phy_ops_t;
 235
 236 #if EFSYS_OPT_FILTER
 237 typedef struct efx_filter_ops_s {
 238         efx_rc_t        (*efo_init)(efx_nic_t *);
 239         void            (*efo_fini)(efx_nic_t *);
 240         efx_rc_t        (*efo_restore)(efx_nic_t *);
 241         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 242                                    boolean_t may_replace);
 243         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 244         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 245                                    size_t, size_t *);
 246         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 247                                    boolean_t, boolean_t, boolean_t,
 248                                    uint8_t const *, uint32_t);
 249 } efx_filter_ops_t;
 250
 251 extern  __checkReturn   efx_rc_t
 252 efx_filter_reconfigure(
 253         __in                            efx_nic_t *enp,
 254         __in_ecount(6)                  uint8_t const *mac_addr,
 255         __in                            boolean_t all_unicst,
 256         __in                            boolean_t mulcst,
 257         __in                            boolean_t all_mulcst,
 258         __in                            boolean_t brdcst,
 259         __in_ecount(6*count)            uint8_t const *addrs,
 260         __in                            uint32_t count);
 261
 262 #endif /* EFSYS_OPT_FILTER */
 263
 264
 265 typedef struct efx_port_s {
 266         efx_mac_type_t          ep_mac_type;
 267         uint32_t                ep_phy_type;
 268         uint8_t                 ep_port;
 269         uint32_t                ep_mac_pdu;
 270         uint8_t                 ep_mac_addr[6];
 271         efx_link_mode_t         ep_link_mode;
 272         boolean_t               ep_all_unicst;
 273         boolean_t               ep_mulcst;
 274         boolean_t               ep_all_mulcst;
 275         boolean_t               ep_brdcst;
 276         unsigned int            ep_fcntl;
 277         boolean_t               ep_fcntl_autoneg;
 278         efx_oword_t             ep_multicst_hash[2];
 279         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 280                                                     EFX_MAC_MULTICAST_LIST_MAX];
 281         uint32_t                ep_mulcst_addr_count;
 282 #if EFSYS_OPT_LOOPBACK
 283         efx_loopback_type_t     ep_loopback_type;
 284         efx_link_mode_t         ep_loopback_link_mode;
 285 #endif  /* EFSYS_OPT_LOOPBACK */
 286 #if EFSYS_OPT_PHY_FLAGS
 287         uint32_t                ep_phy_flags;
 288 #endif  /* EFSYS_OPT_PHY_FLAGS */
 289 #if EFSYS_OPT_PHY_LED_CONTROL
 290         efx_phy_led_mode_t      ep_phy_led_mode;
 291 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 292         efx_phy_media_type_t    ep_fixed_port_type;
 293         efx_phy_media_type_t    ep_module_type;
 294         uint32_t                ep_adv_cap_mask;
 295         uint32_t                ep_lp_cap_mask;
 296         uint32_t                ep_default_adv_cap_mask;
 297         uint32_t                ep_phy_cap_mask;
 298         boolean_t               ep_mac_drain;
 299         boolean_t               ep_mac_stats_pending;
 300 #if EFSYS_OPT_BIST
 301         efx_bist_type_t         ep_current_bist;
 302 #endif
 303         const efx_mac_ops_t     *ep_emop;
 304         const efx_phy_ops_t     *ep_epop;
 305 } efx_port_t;
 306
 307 typedef struct efx_mon_ops_s {
 308 #if EFSYS_OPT_MON_STATS
 309         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 310                                             efx_mon_stat_value_t *);
 311 #endif  /* EFSYS_OPT_MON_STATS */
 312 } efx_mon_ops_t;
 313
 314 typedef struct efx_mon_s {
 315         efx_mon_type_t          em_type;
 316         const efx_mon_ops_t     *em_emop;
 317 } efx_mon_t;
 318
 319 typedef struct efx_intr_ops_s {
 320         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 321         void            (*eio_enable)(efx_nic_t *);
 322         void            (*eio_disable)(efx_nic_t *);
 323         void            (*eio_disable_unlocked)(efx_nic_t *);
 324         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 325         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 326         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 327                                  boolean_t *);
 328         void            (*eio_fatal)(efx_nic_t *);
 329         void            (*eio_fini)(efx_nic_t *);
 330 } efx_intr_ops_t;
 331
 332 typedef struct efx_intr_s {
 333         const efx_intr_ops_t    *ei_eiop;
 334         efsys_mem_t             *ei_esmp;
 335         efx_intr_type_t         ei_type;
 336         unsigned int            ei_level;
 337 } efx_intr_t;
 338
 339 typedef struct efx_nic_ops_s {
 340         efx_rc_t        (*eno_probe)(efx_nic_t *);
 341         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 342         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 343         efx_rc_t        (*eno_reset)(efx_nic_t *);
 344         efx_rc_t        (*eno_init)(efx_nic_t *);
 345         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 346         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 347                                         uint32_t *, size_t *);
 348 #if EFSYS_OPT_DIAG
 349         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 350 #endif  /* EFSYS_OPT_DIAG */
 351         void            (*eno_fini)(efx_nic_t *);
 352         void            (*eno_unprobe)(efx_nic_t *);
 353 } efx_nic_ops_t;
 354
 355 #ifndef EFX_TXQ_LIMIT_TARGET
 356 #define EFX_TXQ_LIMIT_TARGET 259
 357 #endif
 358 #ifndef EFX_RXQ_LIMIT_TARGET
 359 #define EFX_RXQ_LIMIT_TARGET 512
 360 #endif
 361 #ifndef EFX_TXQ_DC_SIZE
 362 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 363 #endif
 364 #ifndef EFX_RXQ_DC_SIZE
 365 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 366 #endif
 367
 368 #if EFSYS_OPT_FILTER
 369
 370 #if EFSYS_OPT_SIENA
 371
 372 typedef struct siena_filter_spec_s {
 373         uint8_t         sfs_type;
 374         uint32_t        sfs_flags;
 375         uint32_t        sfs_dmaq_id;
 376         uint32_t        sfs_dword[3];
 377 } siena_filter_spec_t;
 378
 379 typedef enum siena_filter_type_e {
 380         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 381         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 382         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 383         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 384         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 385         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 386
 387         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 388         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 389         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 390         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 391         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 392         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 393
 394         EFX_SIENA_FILTER_NTYPES
 395 } siena_filter_type_t;
 396
 397 typedef enum siena_filter_tbl_id_e {
 398         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 399         EFX_SIENA_FILTER_TBL_RX_MAC,
 400         EFX_SIENA_FILTER_TBL_TX_IP,
 401         EFX_SIENA_FILTER_TBL_TX_MAC,
 402         EFX_SIENA_FILTER_NTBLS
 403 } siena_filter_tbl_id_t;
 404
 405 typedef struct siena_filter_tbl_s {
 406         int                     sft_size;       /* number of entries */
 407         int                     sft_used;       /* active count */
 408         uint32_t                *sft_bitmap;    /* active bitmap */
 409         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 410 } siena_filter_tbl_t;
 411
 412 typedef struct siena_filter_s {
 413         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 414         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 415 } siena_filter_t;
 416
 417 #endif  /* EFSYS_OPT_SIENA */
 418
 419 typedef struct efx_filter_s {
 420 #if EFSYS_OPT_SIENA
 421         siena_filter_t          *ef_siena_filter;
 422 #endif /* EFSYS_OPT_SIENA */
 423 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 424         ef10_filter_table_t     *ef_ef10_filter_table;
 425 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 426 } efx_filter_t;
 427
 428 #if EFSYS_OPT_SIENA
 429
 430 extern                  void
 431 siena_filter_tbl_clear(
 432         __in            efx_nic_t *enp,
 433         __in            siena_filter_tbl_id_t tbl);
 434
 435 #endif  /* EFSYS_OPT_SIENA */
 436
 437 #endif  /* EFSYS_OPT_FILTER */
 438
 439 #if EFSYS_OPT_MCDI
 440
 441 typedef struct efx_mcdi_ops_s {
 442         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 443         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 444                                         void *, size_t);
 445         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 446         boolean_t       (*emco_poll_response)(efx_nic_t *);
 447         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 448         void            (*emco_fini)(efx_nic_t *);
 449         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 450                                             efx_mcdi_feature_id_t, boolean_t *);
 451         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 452                                             uint32_t *);
 453 } efx_mcdi_ops_t;
 454
 455 typedef struct efx_mcdi_s {
 456         const efx_mcdi_ops_t            *em_emcop;
 457         const efx_mcdi_transport_t      *em_emtp;
 458         efx_mcdi_iface_t                em_emip;
 459 } efx_mcdi_t;
 460
 461 #endif /* EFSYS_OPT_MCDI */
 462
 463 #if EFSYS_OPT_NVRAM
 464
 465 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 466 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 467
 468 typedef struct efx_nvram_ops_s {
 469 #if EFSYS_OPT_DIAG
 470         efx_rc_t        (*envo_test)(efx_nic_t *);
 471 #endif  /* EFSYS_OPT_DIAG */
 472         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 473                                             uint32_t *);
 474         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 475         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 476         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 477                                             unsigned int, caddr_t, size_t);
 478         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 479                                             unsigned int, size_t);
 480         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 481                                             unsigned int, caddr_t, size_t);
 482         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 483                                             uint32_t *);
 484         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 485                                             uint32_t *, uint16_t *);
 486         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 487                                             uint16_t *);
 488         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 489                                             caddr_t, size_t);
 490 } efx_nvram_ops_t;
 491 #endif /* EFSYS_OPT_NVRAM */
 492
 493 #if EFSYS_OPT_VPD
 494 typedef struct efx_vpd_ops_s {
 495         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 496         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 497         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 498         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 499         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 500         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 501                                         efx_vpd_value_t *);
 502         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 503                                         efx_vpd_value_t *);
 504         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 505                                         efx_vpd_value_t *, unsigned int *);
 506         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 507         void            (*evpdo_fini)(efx_nic_t *);
 508 } efx_vpd_ops_t;
 509 #endif  /* EFSYS_OPT_VPD */
 510
 511 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 512
 513         __checkReturn           efx_rc_t
 514 efx_mcdi_nvram_partitions(
 515         __in                    efx_nic_t *enp,
 516         __out_bcount(size)      caddr_t data,
 517         __in                    size_t size,
 518         __out                   unsigned int *npartnp);
 519
 520         __checkReturn           efx_rc_t
 521 efx_mcdi_nvram_metadata(
 522         __in                    efx_nic_t *enp,
 523         __in                    uint32_t partn,
 524         __out                   uint32_t *subtypep,
 525         __out_ecount(4)         uint16_t version[4],
 526         __out_bcount_opt(size)  char *descp,
 527         __in                    size_t size);
 528
 529         __checkReturn           efx_rc_t
 530 efx_mcdi_nvram_info(
 531         __in                    efx_nic_t *enp,
 532         __in                    uint32_t partn,
 533         __out_opt               size_t *sizep,
 534         __out_opt               uint32_t *addressp,
 535         __out_opt               uint32_t *erase_sizep,
 536         __out_opt               uint32_t *write_sizep);
 537
 538         __checkReturn           efx_rc_t
 539 efx_mcdi_nvram_update_start(
 540         __in                    efx_nic_t *enp,
 541         __in                    uint32_t partn);
 542
 543         __checkReturn           efx_rc_t
 544 efx_mcdi_nvram_read(
 545         __in                    efx_nic_t *enp,
 546         __in                    uint32_t partn,
 547         __in                    uint32_t offset,
 548         __out_bcount(size)      caddr_t data,
 549         __in                    size_t size,
 550         __in                    uint32_t mode);
 551
 552         __checkReturn           efx_rc_t
 553 efx_mcdi_nvram_erase(
 554         __in                    efx_nic_t *enp,
 555         __in                    uint32_t partn,
 556         __in                    uint32_t offset,
 557         __in                    size_t size);
 558
 559         __checkReturn           efx_rc_t
 560 efx_mcdi_nvram_write(
 561         __in                    efx_nic_t *enp,
 562         __in                    uint32_t partn,
 563         __in                    uint32_t offset,
 564         __out_bcount(size)      caddr_t data,
 565         __in                    size_t size);
 566
 567         __checkReturn           efx_rc_t
 568 efx_mcdi_nvram_update_finish(
 569         __in                    efx_nic_t *enp,
 570         __in                    uint32_t partn,
 571         __in                    boolean_t reboot,
 572         __out_opt               uint32_t *verify_resultp);
 573
 574 #if EFSYS_OPT_DIAG
 575
 576         __checkReturn           efx_rc_t
 577 efx_mcdi_nvram_test(
 578         __in                    efx_nic_t *enp,
 579         __in                    uint32_t partn);
 580
 581 #endif  /* EFSYS_OPT_DIAG */
 582
 583 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 584
 585 #if EFSYS_OPT_LICENSING
 586
 587 typedef struct efx_lic_ops_s {
 588         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 589         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 590         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 591         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 592                                       size_t *, uint8_t *);
 593         efx_rc_t        (*elo_find_start)
 594                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 595         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 596                                 uint32_t, uint32_t *);
 597         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 598                                 uint32_t, uint32_t *, uint32_t *);
 599         boolean_t       (*elo_validate_key)(efx_nic_t *,
 600                                 caddr_t, uint32_t);
 601         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 602                                 caddr_t, size_t, uint32_t, uint32_t,
 603                                 caddr_t, size_t, uint32_t *);
 604         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 605                                 caddr_t, size_t, uint32_t,
 606                                 caddr_t, uint32_t, uint32_t *);
 607         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 608                                 caddr_t, size_t, uint32_t,
 609                                 uint32_t, uint32_t, uint32_t *);
 610         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 611                                 caddr_t, size_t);
 612         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 613                                 caddr_t, size_t);
 614 } efx_lic_ops_t;
 615
 616 #endif
 617
 618 typedef struct efx_drv_cfg_s {
 619         uint32_t                edc_min_vi_count;
 620         uint32_t                edc_max_vi_count;
 621
 622         uint32_t                edc_max_piobuf_count;
 623         uint32_t                edc_pio_alloc_size;
 624 } efx_drv_cfg_t;
 625
 626 struct efx_nic_s {
 627         uint32_t                en_magic;
 628         efx_family_t            en_family;
 629         uint32_t                en_features;
 630         efsys_identifier_t      *en_esip;
 631         efsys_lock_t            *en_eslp;
 632         efsys_bar_t             *en_esbp;
 633         unsigned int            en_mod_flags;
 634         unsigned int            en_reset_flags;
 635         efx_nic_cfg_t           en_nic_cfg;
 636         efx_drv_cfg_t           en_drv_cfg;
 637         efx_port_t              en_port;
 638         efx_mon_t               en_mon;
 639         efx_intr_t              en_intr;
 640         uint32_t                en_ev_qcount;
 641         uint32_t                en_rx_qcount;
 642         uint32_t                en_tx_qcount;
 643         const efx_nic_ops_t     *en_enop;
 644         const efx_ev_ops_t      *en_eevop;
 645         const efx_tx_ops_t      *en_etxop;
 646         const efx_rx_ops_t      *en_erxop;
 647 #if EFSYS_OPT_FILTER
 648         efx_filter_t            en_filter;
 649         const efx_filter_ops_t  *en_efop;
 650 #endif  /* EFSYS_OPT_FILTER */
 651 #if EFSYS_OPT_MCDI
 652         efx_mcdi_t              en_mcdi;
 653 #endif  /* EFSYS_OPT_MCDI */
 654 #if EFSYS_OPT_NVRAM
 655         uint32_t                en_nvram_partn_locked;
 656         const efx_nvram_ops_t   *en_envop;
 657 #endif  /* EFSYS_OPT_NVRAM */
 658 #if EFSYS_OPT_VPD
 659         const efx_vpd_ops_t     *en_evpdop;
 660 #endif  /* EFSYS_OPT_VPD */
 661 #if EFSYS_OPT_RX_SCALE
 662         efx_rx_hash_support_t           en_hash_support;
 663         efx_rx_scale_context_type_t     en_rss_context_type;
 664         uint32_t                        en_rss_context;
 665 #endif  /* EFSYS_OPT_RX_SCALE */
 666         uint32_t                en_vport_id;
 667 #if EFSYS_OPT_LICENSING
 668         const efx_lic_ops_t     *en_elop;
 669         boolean_t               en_licensing_supported;
 670 #endif
 671         union {
 672 #if EFSYS_OPT_SIENA
 673                 struct {
 674 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 675                         unsigned int            enu_partn_mask;
 676 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 677 #if EFSYS_OPT_VPD
 678                         caddr_t                 enu_svpd;
 679                         size_t                  enu_svpd_length;
 680 #endif  /* EFSYS_OPT_VPD */
 681                         int                     enu_unused;
 682                 } siena;
 683 #endif  /* EFSYS_OPT_SIENA */
 684                 int     enu_unused;
 685         } en_u;
 686 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 687         union en_arch {
 688                 struct {
 689                         int                     ena_vi_base;
 690                         int                     ena_vi_count;
 691                         int                     ena_vi_shift;
 692 #if EFSYS_OPT_VPD
 693                         caddr_t                 ena_svpd;
 694                         size_t                  ena_svpd_length;
 695 #endif  /* EFSYS_OPT_VPD */
 696                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 697                         uint32_t                ena_piobuf_count;
 698                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 699                         uint32_t                ena_pio_write_vi_base;
 700                         /* Memory BAR mapping regions */
 701                         uint32_t                ena_uc_mem_map_offset;
 702                         size_t                  ena_uc_mem_map_size;
 703                         uint32_t                ena_wc_mem_map_offset;
 704                         size_t                  ena_wc_mem_map_size;
 705                 } ef10;
 706         } en_arch;
 707 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 708 };
 709
 710
 711 #define EFX_NIC_MAGIC   0x02121996
 712
 713 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 714     const efx_ev_callbacks_t *, void *);
 715
 716 typedef struct efx_evq_rxq_state_s {
 717         unsigned int                    eers_rx_read_ptr;
 718         unsigned int                    eers_rx_mask;
 719 #if EFSYS_OPT_RX_PACKED_STREAM
 720         unsigned int                    eers_rx_stream_npackets;
 721         boolean_t                       eers_rx_packed_stream;
 722         unsigned int                    eers_rx_packed_stream_credits;
 723 #endif
 724 } efx_evq_rxq_state_t;
 725
 726 struct efx_evq_s {
 727         uint32_t                        ee_magic;
 728         efx_nic_t                       *ee_enp;
 729         unsigned int                    ee_index;
 730         unsigned int                    ee_mask;
 731         efsys_mem_t                     *ee_esmp;
 732 #if EFSYS_OPT_QSTATS
 733         uint32_t                        ee_stat[EV_NQSTATS];
 734 #endif  /* EFSYS_OPT_QSTATS */
 735
 736         efx_ev_handler_t                ee_rx;
 737         efx_ev_handler_t                ee_tx;
 738         efx_ev_handler_t                ee_driver;
 739         efx_ev_handler_t                ee_global;
 740         efx_ev_handler_t                ee_drv_gen;
 741 #if EFSYS_OPT_MCDI
 742         efx_ev_handler_t                ee_mcdi;
 743 #endif  /* EFSYS_OPT_MCDI */
 744
 745         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 746
 747         uint32_t                        ee_flags;
 748 };
 749
 750 #define EFX_EVQ_MAGIC   0x08081997
 751
 752 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 753
 754 struct efx_rxq_s {
 755         uint32_t                        er_magic;
 756         efx_nic_t                       *er_enp;
 757         efx_evq_t                       *er_eep;
 758         unsigned int                    er_index;
 759         unsigned int                    er_label;
 760         unsigned int                    er_mask;
 761         efsys_mem_t                     *er_esmp;
 762 };
 763
 764 #define EFX_RXQ_MAGIC   0x15022005
 765
 766 struct efx_txq_s {
 767         uint32_t                        et_magic;
 768         efx_nic_t                       *et_enp;
 769         unsigned int                    et_index;
 770         unsigned int                    et_mask;
 771         efsys_mem_t                     *et_esmp;
 772 #if EFSYS_OPT_HUNTINGTON
 773         uint32_t                        et_pio_bufnum;
 774         uint32_t                        et_pio_blknum;
 775         uint32_t                        et_pio_write_offset;
 776         uint32_t                        et_pio_offset;
 777         size_t                          et_pio_size;
 778 #endif
 779 #if EFSYS_OPT_QSTATS
 780         uint32_t                        et_stat[TX_NQSTATS];
 781 #endif  /* EFSYS_OPT_QSTATS */
 782 };
 783
 784 #define EFX_TXQ_MAGIC   0x05092005
 785
 786 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 787         do {                                                            \
 788                 (_dst)[0] = (_src)[0];                                  \
 789                 (_dst)[1] = (_src)[1];                                  \
 790                 (_dst)[2] = (_src)[2];                                  \
 791                 (_dst)[3] = (_src)[3];                                  \
 792                 (_dst)[4] = (_src)[4];                                  \
 793                 (_dst)[5] = (_src)[5];                                  \
 794         _NOTE(CONSTANTCONDITION)                                        \
 795         } while (B_FALSE)
 796
 797 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 798         do {                                                            \
 799                 uint16_t *_d = (uint16_t *)(_dst);                      \
 800                 _d[0] = 0xffff;                                         \
 801                 _d[1] = 0xffff;                                         \
 802                 _d[2] = 0xffff;                                         \
 803         _NOTE(CONSTANTCONDITION)                                        \
 804         } while (B_FALSE)
 805
 806 #if EFSYS_OPT_CHECK_REG
 807 #define EFX_CHECK_REG(_enp, _reg)                                       \
 808         do {                                                            \
 809                 const char *name = #_reg;                               \
 810                 char min = name[4];                                     \
 811                 char max = name[5];                                     \
 812                 char rev;                                               \
 813                                                                         \
 814                 switch ((_enp)->en_family) {                            \
 815                 case EFX_FAMILY_SIENA:                                  \
 816                         rev = 'C';                                      \
 817                         break;                                          \
 818                                                                         \
 819                 case EFX_FAMILY_HUNTINGTON:                             \
 820                         rev = 'D';                                      \
 821                         break;                                          \
 822                                                                         \
 823                 case EFX_FAMILY_MEDFORD:                                \
 824                         rev = 'E';                                      \
 825                         break;                                          \
 826                                                                         \
 827                 default:                                                \
 828                         rev = '?';                                      \
 829                         break;                                          \
 830                 }                                                       \
 831                                                                         \
 832                 EFSYS_ASSERT3S(rev, >=, min);                           \
 833                 EFSYS_ASSERT3S(rev, <=, max);                           \
 834                                                                         \
 835         _NOTE(CONSTANTCONDITION)                                        \
 836         } while (B_FALSE)
 837 #else
 838 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 839         _NOTE(CONSTANTCONDITION)                                        \
 840         } while (B_FALSE)
 841 #endif
 842
 843 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 844         do {                                                            \
 845                 EFX_CHECK_REG((_enp), (_reg));                          \
 846                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 847                     (_edp), (_lock));                                   \
 848                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 849                     uint32_t, _reg ## _OFST,                            \
 850                     uint32_t, (_edp)->ed_u32[0]);                       \
 851         _NOTE(CONSTANTCONDITION)                                        \
 852         } while (B_FALSE)
 853
 854 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 855         do {                                                            \
 856                 EFX_CHECK_REG((_enp), (_reg));                          \
 857                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 858                     uint32_t, _reg ## _OFST,                            \
 859                     uint32_t, (_edp)->ed_u32[0]);                       \
 860                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 861                     (_edp), (_lock));                                   \
 862         _NOTE(CONSTANTCONDITION)                                        \
 863         } while (B_FALSE)
 864
 865 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 866         do {                                                            \
 867                 EFX_CHECK_REG((_enp), (_reg));                          \
 868                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 869                     (_eqp));                                            \
 870                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 871                     uint32_t, _reg ## _OFST,                            \
 872                     uint32_t, (_eqp)->eq_u32[1],                        \
 873                     uint32_t, (_eqp)->eq_u32[0]);                       \
 874         _NOTE(CONSTANTCONDITION)                                        \
 875         } while (B_FALSE)
 876
 877 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 878         do {                                                            \
 879                 EFX_CHECK_REG((_enp), (_reg));                          \
 880                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 881                     uint32_t, _reg ## _OFST,                            \
 882                     uint32_t, (_eqp)->eq_u32[1],                        \
 883                     uint32_t, (_eqp)->eq_u32[0]);                       \
 884                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 885                     (_eqp));                                            \
 886         _NOTE(CONSTANTCONDITION)                                        \
 887         } while (B_FALSE)
 888
 889 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 890         do {                                                            \
 891                 EFX_CHECK_REG((_enp), (_reg));                          \
 892                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 893                     (_eop), B_TRUE);                                    \
 894                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 895                     uint32_t, _reg ## _OFST,                            \
 896                     uint32_t, (_eop)->eo_u32[3],                        \
 897                     uint32_t, (_eop)->eo_u32[2],                        \
 898                     uint32_t, (_eop)->eo_u32[1],                        \
 899                     uint32_t, (_eop)->eo_u32[0]);                       \
 900         _NOTE(CONSTANTCONDITION)                                        \
 901         } while (B_FALSE)
 902
 903 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 904         do {                                                            \
 905                 EFX_CHECK_REG((_enp), (_reg));                          \
 906                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 907                     uint32_t, _reg ## _OFST,                            \
 908                     uint32_t, (_eop)->eo_u32[3],                        \
 909                     uint32_t, (_eop)->eo_u32[2],                        \
 910                     uint32_t, (_eop)->eo_u32[1],                        \
 911                     uint32_t, (_eop)->eo_u32[0]);                       \
 912                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 913                     (_eop), B_TRUE);                                    \
 914         _NOTE(CONSTANTCONDITION)                                        \
 915         } while (B_FALSE)
 916
 917 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 918         do {                                                            \
 919                 EFX_CHECK_REG((_enp), (_reg));                          \
 920                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 921                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 922                     (_edp), (_lock));                                   \
 923                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 924                     uint32_t, (_index),                                 \
 925                     uint32_t, _reg ## _OFST,                            \
 926                     uint32_t, (_edp)->ed_u32[0]);                       \
 927         _NOTE(CONSTANTCONDITION)                                        \
 928         } while (B_FALSE)
 929
 930 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 931         do {                                                            \
 932                 EFX_CHECK_REG((_enp), (_reg));                          \
 933                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 934                     uint32_t, (_index),                                 \
 935                     uint32_t, _reg ## _OFST,                            \
 936                     uint32_t, (_edp)->ed_u32[0]);                       \
 937                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 938                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 939                     (_edp), (_lock));                                   \
 940         _NOTE(CONSTANTCONDITION)                                        \
 941         } while (B_FALSE)
 942
 943 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 944         do {                                                            \
 945                 EFX_CHECK_REG((_enp), (_reg));                          \
 946                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 947                     uint32_t, (_index),                                 \
 948                     uint32_t, _reg ## _OFST,                            \
 949                     uint32_t, (_edp)->ed_u32[0]);                       \
 950                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 951                     (_reg ## _OFST +                                    \
 952                     (2 * sizeof (efx_dword_t)) +                        \
 953                     ((_index) * _reg ## _STEP)),                        \
 954                     (_edp), (_lock));                                   \
 955         _NOTE(CONSTANTCONDITION)                                        \
 956         } while (B_FALSE)
 957
 958 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 959         do {                                                            \
 960                 EFX_CHECK_REG((_enp), (_reg));                          \
 961                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 962                     uint32_t, (_index),                                 \
 963                     uint32_t, _reg ## _OFST,                            \
 964                     uint32_t, (_edp)->ed_u32[0]);                       \
 965                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 966                     (_reg ## _OFST +                                    \
 967                     (3 * sizeof (efx_dword_t)) +                        \
 968                     ((_index) * _reg ## _STEP)),                        \
 969                     (_edp), (_lock));                                   \
 970         _NOTE(CONSTANTCONDITION)                                        \
 971         } while (B_FALSE)
 972
 973 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 974         do {                                                            \
 975                 EFX_CHECK_REG((_enp), (_reg));                          \
 976                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 977                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 978                     (_eqp));                                            \
 979                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 980                     uint32_t, (_index),                                 \
 981                     uint32_t, _reg ## _OFST,                            \
 982                     uint32_t, (_eqp)->eq_u32[1],                        \
 983                     uint32_t, (_eqp)->eq_u32[0]);                       \
 984         _NOTE(CONSTANTCONDITION)                                        \
 985         } while (B_FALSE)
 986
 987 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 988         do {                                                            \
 989                 EFX_CHECK_REG((_enp), (_reg));                          \
 990                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 991                     uint32_t, (_index),                                 \
 992                     uint32_t, _reg ## _OFST,                            \
 993                     uint32_t, (_eqp)->eq_u32[1],                        \
 994                     uint32_t, (_eqp)->eq_u32[0]);                       \
 995                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 996                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 997                     (_eqp));                                            \
 998         _NOTE(CONSTANTCONDITION)                                        \
 999         } while (B_FALSE)
1000
1001 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1002         do {                                                            \
1003                 EFX_CHECK_REG((_enp), (_reg));                          \
1004                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1005                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1006                     (_eop), (_lock));                                   \
1007                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1008                     uint32_t, (_index),                                 \
1009                     uint32_t, _reg ## _OFST,                            \
1010                     uint32_t, (_eop)->eo_u32[3],                        \
1011                     uint32_t, (_eop)->eo_u32[2],                        \
1012                     uint32_t, (_eop)->eo_u32[1],                        \
1013                     uint32_t, (_eop)->eo_u32[0]);                       \
1014         _NOTE(CONSTANTCONDITION)                                        \
1015         } while (B_FALSE)
1016
1017 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1018         do {                                                            \
1019                 EFX_CHECK_REG((_enp), (_reg));                          \
1020                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1021                     uint32_t, (_index),                                 \
1022                     uint32_t, _reg ## _OFST,                            \
1023                     uint32_t, (_eop)->eo_u32[3],                        \
1024                     uint32_t, (_eop)->eo_u32[2],                        \
1025                     uint32_t, (_eop)->eo_u32[1],                        \
1026                     uint32_t, (_eop)->eo_u32[0]);                       \
1027                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1028                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1029                     (_eop), (_lock));                                   \
1030         _NOTE(CONSTANTCONDITION)                                        \
1031         } while (B_FALSE)
1032
1033 /*
1034  * Allow drivers to perform optimised 128-bit doorbell writes.
1035  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1036  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1037  * the need for locking in the host, and are the only ones known to be safe to
1038  * use 128-bites write with.
1039  */
1040 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1041         do {                                                            \
1042                 EFX_CHECK_REG((_enp), (_reg));                          \
1043                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1044                     const char *,                                       \
1045                     #_reg,                                              \
1046                     uint32_t, (_index),                                 \
1047                     uint32_t, _reg ## _OFST,                            \
1048                     uint32_t, (_eop)->eo_u32[3],                        \
1049                     uint32_t, (_eop)->eo_u32[2],                        \
1050                     uint32_t, (_eop)->eo_u32[1],                        \
1051                     uint32_t, (_eop)->eo_u32[0]);                       \
1052                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1053                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1054                     (_eop));                                            \
1055         _NOTE(CONSTANTCONDITION)                                        \
1056         } while (B_FALSE)
1057
1058 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1059         do {                                                            \
1060                 unsigned int _new = (_wptr);                            \
1061                 unsigned int _old = (_owptr);                           \
1062                                                                         \
1063                 if ((_new) >= (_old))                                   \
1064                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1065                             (_old) * sizeof (efx_desc_t),               \
1066                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1067                 else                                                    \
1068                         /*                                              \
1069                          * It is cheaper to sync entire map than sync   \
1070                          * two parts especially when offset/size are    \
1071                          * ignored and entire map is synced in any case.\
1072                          */                                             \
1073                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1074                             0,                                          \
1075                             (_entries) * sizeof (efx_desc_t));          \
1076         _NOTE(CONSTANTCONDITION)                                        \
1077         } while (B_FALSE)
1078
1079 extern  __checkReturn   efx_rc_t
1080 efx_nic_biu_test(
1081         __in            efx_nic_t *enp);
1082
1083 extern  __checkReturn   efx_rc_t
1084 efx_mac_select(
1085         __in            efx_nic_t *enp);
1086
1087 extern  void
1088 efx_mac_multicast_hash_compute(
1089         __in_ecount(6*count)            uint8_t const *addrs,
1090         __in                            int count,
1091         __out                           efx_oword_t *hash_low,
1092         __out                           efx_oword_t *hash_high);
1093
1094 extern  __checkReturn   efx_rc_t
1095 efx_phy_probe(
1096         __in            efx_nic_t *enp);
1097
1098 extern                  void
1099 efx_phy_unprobe(
1100         __in            efx_nic_t *enp);
1101
1102 #if EFSYS_OPT_VPD
1103
1104 /* VPD utility functions */
1105
1106 extern  __checkReturn           efx_rc_t
1107 efx_vpd_hunk_length(
1108         __in_bcount(size)       caddr_t data,
1109         __in                    size_t size,
1110         __out                   size_t *lengthp);
1111
1112 extern  __checkReturn           efx_rc_t
1113 efx_vpd_hunk_verify(
1114         __in_bcount(size)       caddr_t data,
1115         __in                    size_t size,
1116         __out_opt               boolean_t *cksummedp);
1117
1118 extern  __checkReturn           efx_rc_t
1119 efx_vpd_hunk_reinit(
1120         __in_bcount(size)       caddr_t data,
1121         __in                    size_t size,
1122         __in                    boolean_t wantpid);
1123
1124 extern  __checkReturn           efx_rc_t
1125 efx_vpd_hunk_get(
1126         __in_bcount(size)       caddr_t data,
1127         __in                    size_t size,
1128         __in                    efx_vpd_tag_t tag,
1129         __in                    efx_vpd_keyword_t keyword,
1130         __out                   unsigned int *payloadp,
1131         __out                   uint8_t *paylenp);
1132
1133 extern  __checkReturn                   efx_rc_t
1134 efx_vpd_hunk_next(
1135         __in_bcount(size)               caddr_t data,
1136         __in                            size_t size,
1137         __out                           efx_vpd_tag_t *tagp,
1138         __out                           efx_vpd_keyword_t *keyword,
1139         __out_opt                       unsigned int *payloadp,
1140         __out_opt                       uint8_t *paylenp,
1141         __inout                         unsigned int *contp);
1142
1143 extern  __checkReturn           efx_rc_t
1144 efx_vpd_hunk_set(
1145         __in_bcount(size)       caddr_t data,
1146         __in                    size_t size,
1147         __in                    efx_vpd_value_t *evvp);
1148
1149 #endif  /* EFSYS_OPT_VPD */
1150
1151 #if EFSYS_OPT_DIAG
1152
1153 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1154
1155 typedef struct efx_register_set_s {
1156         unsigned int            address;
1157         unsigned int            step;
1158         unsigned int            rows;
1159         efx_oword_t             mask;
1160 } efx_register_set_t;
1161
1162 extern  __checkReturn   efx_rc_t
1163 efx_nic_test_registers(
1164         __in            efx_nic_t *enp,
1165         __in            efx_register_set_t *rsp,
1166         __in            size_t count);
1167
1168 extern  __checkReturn   efx_rc_t
1169 efx_nic_test_tables(
1170         __in            efx_nic_t *enp,
1171         __in            efx_register_set_t *rsp,
1172         __in            efx_pattern_type_t pattern,
1173         __in            size_t count);
1174
1175 #endif  /* EFSYS_OPT_DIAG */
1176
1177 #if EFSYS_OPT_MCDI
1178
1179 extern  __checkReturn           efx_rc_t
1180 efx_mcdi_set_workaround(
1181         __in                    efx_nic_t *enp,
1182         __in                    uint32_t type,
1183         __in                    boolean_t enabled,
1184         __out_opt               uint32_t *flagsp);
1185
1186 extern  __checkReturn           efx_rc_t
1187 efx_mcdi_get_workarounds(
1188         __in                    efx_nic_t *enp,
1189         __out_opt               uint32_t *implementedp,
1190         __out_opt               uint32_t *enabledp);
1191
1192 #endif /* EFSYS_OPT_MCDI */
1193
1194 #if EFSYS_OPT_MAC_STATS
1195
1196 /*
1197  * Closed range of stats (i.e. the first and the last are included).
1198  * The last must be greater or equal (if the range is one item only) to
1199  * the first.
1200  */
1201 struct efx_mac_stats_range {
1202         efx_mac_stat_t          first;
1203         efx_mac_stat_t          last;
1204 };
1205
1206 extern                                  efx_rc_t
1207 efx_mac_stats_mask_add_ranges(
1208         __inout_bcount(mask_size)       uint32_t *maskp,
1209         __in                            size_t mask_size,
1210         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1211         __in                            unsigned int rng_count);
1212
1213 #endif  /* EFSYS_OPT_MAC_STATS */
1214
1215 #ifdef  __cplusplus
1216 }
1217 #endif
1218
1219 #endif  /* _SYS_EFX_IMPL_H */