drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13
  14 /* FIXME: Add definition for driver generated software events */
  15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  17 #endif
  18
  19
  20 #if EFSYS_OPT_SIENA
  21 #include "siena_impl.h"
  22 #endif  /* EFSYS_OPT_SIENA */
  23
  24 #if EFSYS_OPT_HUNTINGTON
  25 #include "hunt_impl.h"
  26 #endif  /* EFSYS_OPT_HUNTINGTON */
  27
  28 #if EFSYS_OPT_MEDFORD
  29 #include "medford_impl.h"
  30 #endif  /* EFSYS_OPT_MEDFORD */
  31
  32 #if EFSYS_OPT_MEDFORD2
  33 #include "medford2_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD2 */
  35
  36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
  37 #include "ef10_impl.h"
  38 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
  39
  40 #ifdef  __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 #define EFX_MOD_MCDI            0x00000001
  45 #define EFX_MOD_PROBE           0x00000002
  46 #define EFX_MOD_NVRAM           0x00000004
  47 #define EFX_MOD_VPD             0x00000008
  48 #define EFX_MOD_NIC             0x00000010
  49 #define EFX_MOD_INTR            0x00000020
  50 #define EFX_MOD_EV              0x00000040
  51 #define EFX_MOD_RX              0x00000080
  52 #define EFX_MOD_TX              0x00000100
  53 #define EFX_MOD_PORT            0x00000200
  54 #define EFX_MOD_MON             0x00000400
  55 #define EFX_MOD_FILTER          0x00001000
  56 #define EFX_MOD_LIC             0x00002000
  57 #define EFX_MOD_TUNNEL          0x00004000
  58
  59 #define EFX_RESET_PHY           0x00000001
  60 #define EFX_RESET_RXQ_ERR       0x00000002
  61 #define EFX_RESET_TXQ_ERR       0x00000004
  62 #define EFX_RESET_HW_UNAVAIL    0x00000008
  63
  64 typedef enum efx_mac_type_e {
  65         EFX_MAC_INVALID = 0,
  66         EFX_MAC_SIENA,
  67         EFX_MAC_HUNTINGTON,
  68         EFX_MAC_MEDFORD,
  69         EFX_MAC_MEDFORD2,
  70         EFX_MAC_NTYPES
  71 } efx_mac_type_t;
  72
  73 typedef struct efx_ev_ops_s {
  74         efx_rc_t        (*eevo_init)(efx_nic_t *);
  75         void            (*eevo_fini)(efx_nic_t *);
  76         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  77                                           efsys_mem_t *, size_t, uint32_t,
  78                                           uint32_t, uint32_t, efx_evq_t *);
  79         void            (*eevo_qdestroy)(efx_evq_t *);
  80         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  81         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  82         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  83 #if EFSYS_OPT_QSTATS
  84         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  85 #endif
  86 } efx_ev_ops_t;
  87
  88 typedef struct efx_tx_ops_s {
  89         efx_rc_t        (*etxo_init)(efx_nic_t *);
  90         void            (*etxo_fini)(efx_nic_t *);
  91         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  92                                         unsigned int, unsigned int,
  93                                         efsys_mem_t *, size_t,
  94                                         uint32_t, uint16_t,
  95                                         efx_evq_t *, efx_txq_t *,
  96                                         unsigned int *);
  97         void            (*etxo_qdestroy)(efx_txq_t *);
  98         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
  99                                       unsigned int, unsigned int,
 100                                       unsigned int *);
 101         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 102         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 103         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 104         void            (*etxo_qenable)(efx_txq_t *);
 105         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 106         void            (*etxo_qpio_disable)(efx_txq_t *);
 107         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 108                                            size_t);
 109         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 110                                            unsigned int *);
 111         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 112                                       unsigned int, unsigned int,
 113                                       unsigned int *);
 114         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 115                                                 size_t, boolean_t,
 116                                                 efx_desc_t *);
 117         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 118                                                 uint32_t, uint8_t,
 119                                                 efx_desc_t *);
 120         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 121                                                 uint16_t, uint32_t, uint16_t,
 122                                                 efx_desc_t *, int);
 123         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 124                                                 efx_desc_t *);
 125         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 126                                                 efx_desc_t *);
 127 #if EFSYS_OPT_QSTATS
 128         void            (*etxo_qstats_update)(efx_txq_t *,
 129                                               efsys_stat_t *);
 130 #endif
 131 } efx_tx_ops_t;
 132
 133 typedef union efx_rxq_type_data_u {
 134         /* Dummy member to have non-empty union if no options are enabled */
 135         uint32_t        ertd_dummy;
 136 #if EFSYS_OPT_RX_PACKED_STREAM
 137         struct {
 138                 uint32_t        eps_buf_size;
 139         } ertd_packed_stream;
 140 #endif
 141 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 142         struct {
 143                 uint32_t        eessb_bufs_per_desc;
 144                 uint32_t        eessb_max_dma_len;
 145                 uint32_t        eessb_buf_stride;
 146                 uint32_t        eessb_hol_block_timeout;
 147         } ertd_es_super_buffer;
 148 #endif
 149 } efx_rxq_type_data_t;
 150
 151 typedef struct efx_rx_ops_s {
 152         efx_rc_t        (*erxo_init)(efx_nic_t *);
 153         void            (*erxo_fini)(efx_nic_t *);
 154 #if EFSYS_OPT_RX_SCATTER
 155         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 156 #endif
 157 #if EFSYS_OPT_RX_SCALE
 158         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 159                                                     efx_rx_scale_context_type_t,
 160                                                     uint32_t, uint32_t *);
 161         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 162         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 163                                                efx_rx_hash_alg_t,
 164                                                efx_rx_hash_type_t, boolean_t);
 165         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 166                                               uint8_t *, size_t);
 167         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 168                                               unsigned int *, size_t);
 169         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 170                                             uint8_t *);
 171 #endif /* EFSYS_OPT_RX_SCALE */
 172         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 173                                               uint16_t *);
 174         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 175                                       unsigned int, unsigned int,
 176                                       unsigned int);
 177         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 178 #if EFSYS_OPT_RX_PACKED_STREAM
 179         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 180         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 181                                                 uint32_t, uint32_t,
 182                                                 uint16_t *, uint32_t *, uint32_t *);
 183 #endif
 184         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 185         void            (*erxo_qenable)(efx_rxq_t *);
 186         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 187                                         unsigned int, efx_rxq_type_t,
 188                                         const efx_rxq_type_data_t *,
 189                                         efsys_mem_t *, size_t, uint32_t,
 190                                         unsigned int,
 191                                         efx_evq_t *, efx_rxq_t *);
 192         void            (*erxo_qdestroy)(efx_rxq_t *);
 193 } efx_rx_ops_t;
 194
 195 typedef struct efx_mac_ops_s {
 196         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 197         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 198         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 199         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 200         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 201         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 202         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 203         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 204                                                       efx_rxq_t *, boolean_t);
 205         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 206 #if EFSYS_OPT_LOOPBACK
 207         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 208                                             efx_loopback_type_t);
 209 #endif  /* EFSYS_OPT_LOOPBACK */
 210 #if EFSYS_OPT_MAC_STATS
 211         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 212         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 213         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 214         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 215                                               uint16_t, boolean_t);
 216         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 217                                             efsys_stat_t *, uint32_t *);
 218 #endif  /* EFSYS_OPT_MAC_STATS */
 219 } efx_mac_ops_t;
 220
 221 typedef struct efx_phy_ops_s {
 222         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 223         efx_rc_t        (*epo_reset)(efx_nic_t *);
 224         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 225         efx_rc_t        (*epo_verify)(efx_nic_t *);
 226         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 227 #if EFSYS_OPT_PHY_STATS
 228         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 229                                             uint32_t *);
 230 #endif  /* EFSYS_OPT_PHY_STATS */
 231 #if EFSYS_OPT_BIST
 232         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 233         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 234         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 235                                          efx_bist_result_t *, uint32_t *,
 236                                          unsigned long *, size_t);
 237         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 238 #endif  /* EFSYS_OPT_BIST */
 239 } efx_phy_ops_t;
 240
 241 #if EFSYS_OPT_FILTER
 242 typedef struct efx_filter_ops_s {
 243         efx_rc_t        (*efo_init)(efx_nic_t *);
 244         void            (*efo_fini)(efx_nic_t *);
 245         efx_rc_t        (*efo_restore)(efx_nic_t *);
 246         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 247                                    boolean_t may_replace);
 248         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 249         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 250                                    size_t, size_t *);
 251         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 252                                    boolean_t, boolean_t, boolean_t,
 253                                    uint8_t const *, uint32_t);
 254 } efx_filter_ops_t;
 255
 256 extern  __checkReturn   efx_rc_t
 257 efx_filter_reconfigure(
 258         __in                            efx_nic_t *enp,
 259         __in_ecount(6)                  uint8_t const *mac_addr,
 260         __in                            boolean_t all_unicst,
 261         __in                            boolean_t mulcst,
 262         __in                            boolean_t all_mulcst,
 263         __in                            boolean_t brdcst,
 264         __in_ecount(6*count)            uint8_t const *addrs,
 265         __in                            uint32_t count);
 266
 267 #endif /* EFSYS_OPT_FILTER */
 268
 269 #if EFSYS_OPT_TUNNEL
 270 typedef struct efx_tunnel_ops_s {
 271         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 272         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 273 } efx_tunnel_ops_t;
 274 #endif /* EFSYS_OPT_TUNNEL */
 275
 276 typedef struct efx_port_s {
 277         efx_mac_type_t          ep_mac_type;
 278         uint32_t                ep_phy_type;
 279         uint8_t                 ep_port;
 280         uint32_t                ep_mac_pdu;
 281         uint8_t                 ep_mac_addr[6];
 282         efx_link_mode_t         ep_link_mode;
 283         boolean_t               ep_all_unicst;
 284         boolean_t               ep_mulcst;
 285         boolean_t               ep_all_mulcst;
 286         boolean_t               ep_brdcst;
 287         unsigned int            ep_fcntl;
 288         boolean_t               ep_fcntl_autoneg;
 289         efx_oword_t             ep_multicst_hash[2];
 290         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 291                                                     EFX_MAC_MULTICAST_LIST_MAX];
 292         uint32_t                ep_mulcst_addr_count;
 293 #if EFSYS_OPT_LOOPBACK
 294         efx_loopback_type_t     ep_loopback_type;
 295         efx_link_mode_t         ep_loopback_link_mode;
 296 #endif  /* EFSYS_OPT_LOOPBACK */
 297 #if EFSYS_OPT_PHY_FLAGS
 298         uint32_t                ep_phy_flags;
 299 #endif  /* EFSYS_OPT_PHY_FLAGS */
 300 #if EFSYS_OPT_PHY_LED_CONTROL
 301         efx_phy_led_mode_t      ep_phy_led_mode;
 302 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 303         efx_phy_media_type_t    ep_fixed_port_type;
 304         efx_phy_media_type_t    ep_module_type;
 305         uint32_t                ep_adv_cap_mask;
 306         uint32_t                ep_lp_cap_mask;
 307         uint32_t                ep_default_adv_cap_mask;
 308         uint32_t                ep_phy_cap_mask;
 309         boolean_t               ep_mac_drain;
 310 #if EFSYS_OPT_BIST
 311         efx_bist_type_t         ep_current_bist;
 312 #endif
 313         const efx_mac_ops_t     *ep_emop;
 314         const efx_phy_ops_t     *ep_epop;
 315 } efx_port_t;
 316
 317 typedef struct efx_mon_ops_s {
 318 #if EFSYS_OPT_MON_STATS
 319         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 320                                             efx_mon_stat_value_t *);
 321         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 322                                              efx_mon_stat_limits_t *);
 323 #endif  /* EFSYS_OPT_MON_STATS */
 324 } efx_mon_ops_t;
 325
 326 typedef struct efx_mon_s {
 327         efx_mon_type_t          em_type;
 328         const efx_mon_ops_t     *em_emop;
 329 } efx_mon_t;
 330
 331 typedef struct efx_intr_ops_s {
 332         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 333         void            (*eio_enable)(efx_nic_t *);
 334         void            (*eio_disable)(efx_nic_t *);
 335         void            (*eio_disable_unlocked)(efx_nic_t *);
 336         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 337         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 338         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 339                                  boolean_t *);
 340         void            (*eio_fatal)(efx_nic_t *);
 341         void            (*eio_fini)(efx_nic_t *);
 342 } efx_intr_ops_t;
 343
 344 typedef struct efx_intr_s {
 345         const efx_intr_ops_t    *ei_eiop;
 346         efsys_mem_t             *ei_esmp;
 347         efx_intr_type_t         ei_type;
 348         unsigned int            ei_level;
 349 } efx_intr_t;
 350
 351 typedef struct efx_nic_ops_s {
 352         efx_rc_t        (*eno_probe)(efx_nic_t *);
 353         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 354         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 355         efx_rc_t        (*eno_reset)(efx_nic_t *);
 356         efx_rc_t        (*eno_init)(efx_nic_t *);
 357         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 358         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 359                                         uint32_t *, size_t *);
 360         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 361 #if EFSYS_OPT_DIAG
 362         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 363 #endif  /* EFSYS_OPT_DIAG */
 364         void            (*eno_fini)(efx_nic_t *);
 365         void            (*eno_unprobe)(efx_nic_t *);
 366 } efx_nic_ops_t;
 367
 368 #ifndef EFX_TXQ_LIMIT_TARGET
 369 #define EFX_TXQ_LIMIT_TARGET 259
 370 #endif
 371 #ifndef EFX_RXQ_LIMIT_TARGET
 372 #define EFX_RXQ_LIMIT_TARGET 512
 373 #endif
 374
 375
 376 #if EFSYS_OPT_FILTER
 377
 378 #if EFSYS_OPT_SIENA
 379
 380 typedef struct siena_filter_spec_s {
 381         uint8_t         sfs_type;
 382         uint32_t        sfs_flags;
 383         uint32_t        sfs_dmaq_id;
 384         uint32_t        sfs_dword[3];
 385 } siena_filter_spec_t;
 386
 387 typedef enum siena_filter_type_e {
 388         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 389         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 390         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 391         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 392         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 393         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 394
 395         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 396         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 397         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 398         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 399         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 400         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 401
 402         EFX_SIENA_FILTER_NTYPES
 403 } siena_filter_type_t;
 404
 405 typedef enum siena_filter_tbl_id_e {
 406         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 407         EFX_SIENA_FILTER_TBL_RX_MAC,
 408         EFX_SIENA_FILTER_TBL_TX_IP,
 409         EFX_SIENA_FILTER_TBL_TX_MAC,
 410         EFX_SIENA_FILTER_NTBLS
 411 } siena_filter_tbl_id_t;
 412
 413 typedef struct siena_filter_tbl_s {
 414         int                     sft_size;       /* number of entries */
 415         int                     sft_used;       /* active count */
 416         uint32_t                *sft_bitmap;    /* active bitmap */
 417         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 418 } siena_filter_tbl_t;
 419
 420 typedef struct siena_filter_s {
 421         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 422         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 423 } siena_filter_t;
 424
 425 #endif  /* EFSYS_OPT_SIENA */
 426
 427 typedef struct efx_filter_s {
 428 #if EFSYS_OPT_SIENA
 429         siena_filter_t          *ef_siena_filter;
 430 #endif /* EFSYS_OPT_SIENA */
 431 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 432         ef10_filter_table_t     *ef_ef10_filter_table;
 433 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 434 } efx_filter_t;
 435
 436 #if EFSYS_OPT_SIENA
 437
 438 extern                  void
 439 siena_filter_tbl_clear(
 440         __in            efx_nic_t *enp,
 441         __in            siena_filter_tbl_id_t tbl);
 442
 443 #endif  /* EFSYS_OPT_SIENA */
 444
 445 #endif  /* EFSYS_OPT_FILTER */
 446
 447 #if EFSYS_OPT_MCDI
 448
 449 #define EFX_TUNNEL_MAXNENTRIES  (16)
 450
 451 #if EFSYS_OPT_TUNNEL
 452
 453 typedef struct efx_tunnel_udp_entry_s {
 454         uint16_t                        etue_port; /* host/cpu-endian */
 455         uint16_t                        etue_protocol;
 456 } efx_tunnel_udp_entry_t;
 457
 458 typedef struct efx_tunnel_cfg_s {
 459         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 460         unsigned int            etc_udp_entries_num;
 461 } efx_tunnel_cfg_t;
 462
 463 #endif /* EFSYS_OPT_TUNNEL */
 464
 465 typedef struct efx_mcdi_ops_s {
 466         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 467         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 468                                         void *, size_t);
 469         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 470         boolean_t       (*emco_poll_response)(efx_nic_t *);
 471         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 472         void            (*emco_fini)(efx_nic_t *);
 473         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 474                                             efx_mcdi_feature_id_t, boolean_t *);
 475         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 476                                             uint32_t *);
 477 } efx_mcdi_ops_t;
 478
 479 typedef struct efx_mcdi_s {
 480         const efx_mcdi_ops_t            *em_emcop;
 481         const efx_mcdi_transport_t      *em_emtp;
 482         efx_mcdi_iface_t                em_emip;
 483 } efx_mcdi_t;
 484
 485 #endif /* EFSYS_OPT_MCDI */
 486
 487 #if EFSYS_OPT_NVRAM
 488
 489 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 490 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 491
 492 typedef struct efx_nvram_ops_s {
 493 #if EFSYS_OPT_DIAG
 494         efx_rc_t        (*envo_test)(efx_nic_t *);
 495 #endif  /* EFSYS_OPT_DIAG */
 496         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 497                                             uint32_t *);
 498         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 499         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 500         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 501                                             unsigned int, caddr_t, size_t);
 502         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 503                                             unsigned int, caddr_t, size_t);
 504         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 505                                             unsigned int, size_t);
 506         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 507                                             unsigned int, caddr_t, size_t);
 508         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 509                                             uint32_t *);
 510         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 511                                             uint32_t *, uint16_t *);
 512         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 513                                             uint16_t *);
 514         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 515                                             caddr_t, size_t);
 516 } efx_nvram_ops_t;
 517 #endif /* EFSYS_OPT_NVRAM */
 518
 519 #if EFSYS_OPT_VPD
 520 typedef struct efx_vpd_ops_s {
 521         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 522         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 523         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 524         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 525         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 526         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 527                                         efx_vpd_value_t *);
 528         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 529                                         efx_vpd_value_t *);
 530         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 531                                         efx_vpd_value_t *, unsigned int *);
 532         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 533         void            (*evpdo_fini)(efx_nic_t *);
 534 } efx_vpd_ops_t;
 535 #endif  /* EFSYS_OPT_VPD */
 536
 537 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 538
 539         __checkReturn           efx_rc_t
 540 efx_mcdi_nvram_partitions(
 541         __in                    efx_nic_t *enp,
 542         __out_bcount(size)      caddr_t data,
 543         __in                    size_t size,
 544         __out                   unsigned int *npartnp);
 545
 546         __checkReturn           efx_rc_t
 547 efx_mcdi_nvram_metadata(
 548         __in                    efx_nic_t *enp,
 549         __in                    uint32_t partn,
 550         __out                   uint32_t *subtypep,
 551         __out_ecount(4)         uint16_t version[4],
 552         __out_bcount_opt(size)  char *descp,
 553         __in                    size_t size);
 554
 555         __checkReturn           efx_rc_t
 556 efx_mcdi_nvram_info(
 557         __in                    efx_nic_t *enp,
 558         __in                    uint32_t partn,
 559         __out_opt               size_t *sizep,
 560         __out_opt               uint32_t *addressp,
 561         __out_opt               uint32_t *erase_sizep,
 562         __out_opt               uint32_t *write_sizep);
 563
 564         __checkReturn           efx_rc_t
 565 efx_mcdi_nvram_update_start(
 566         __in                    efx_nic_t *enp,
 567         __in                    uint32_t partn);
 568
 569         __checkReturn           efx_rc_t
 570 efx_mcdi_nvram_read(
 571         __in                    efx_nic_t *enp,
 572         __in                    uint32_t partn,
 573         __in                    uint32_t offset,
 574         __out_bcount(size)      caddr_t data,
 575         __in                    size_t size,
 576         __in                    uint32_t mode);
 577
 578         __checkReturn           efx_rc_t
 579 efx_mcdi_nvram_erase(
 580         __in                    efx_nic_t *enp,
 581         __in                    uint32_t partn,
 582         __in                    uint32_t offset,
 583         __in                    size_t size);
 584
 585         __checkReturn           efx_rc_t
 586 efx_mcdi_nvram_write(
 587         __in                    efx_nic_t *enp,
 588         __in                    uint32_t partn,
 589         __in                    uint32_t offset,
 590         __in_bcount(size)       caddr_t data,
 591         __in                    size_t size);
 592
 593         __checkReturn           efx_rc_t
 594 efx_mcdi_nvram_update_finish(
 595         __in                    efx_nic_t *enp,
 596         __in                    uint32_t partn,
 597         __in                    boolean_t reboot,
 598         __out_opt               uint32_t *verify_resultp);
 599
 600 #if EFSYS_OPT_DIAG
 601
 602         __checkReturn           efx_rc_t
 603 efx_mcdi_nvram_test(
 604         __in                    efx_nic_t *enp,
 605         __in                    uint32_t partn);
 606
 607 #endif  /* EFSYS_OPT_DIAG */
 608
 609 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 610
 611 #if EFSYS_OPT_LICENSING
 612
 613 typedef struct efx_lic_ops_s {
 614         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 615         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 616         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 617         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 618                                       size_t *, uint8_t *);
 619         efx_rc_t        (*elo_find_start)
 620                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 621         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 622                                 uint32_t, uint32_t *);
 623         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 624                                 uint32_t, uint32_t *, uint32_t *);
 625         boolean_t       (*elo_validate_key)(efx_nic_t *,
 626                                 caddr_t, uint32_t);
 627         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 628                                 caddr_t, size_t, uint32_t, uint32_t,
 629                                 caddr_t, size_t, uint32_t *);
 630         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 631                                 caddr_t, size_t, uint32_t,
 632                                 caddr_t, uint32_t, uint32_t *);
 633         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 634                                 caddr_t, size_t, uint32_t,
 635                                 uint32_t, uint32_t, uint32_t *);
 636         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 637                                 caddr_t, size_t);
 638         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 639                                 caddr_t, size_t);
 640 } efx_lic_ops_t;
 641
 642 #endif
 643
 644 typedef struct efx_drv_cfg_s {
 645         uint32_t                edc_min_vi_count;
 646         uint32_t                edc_max_vi_count;
 647
 648         uint32_t                edc_max_piobuf_count;
 649         uint32_t                edc_pio_alloc_size;
 650 } efx_drv_cfg_t;
 651
 652 struct efx_nic_s {
 653         uint32_t                en_magic;
 654         efx_family_t            en_family;
 655         uint32_t                en_features;
 656         efsys_identifier_t      *en_esip;
 657         efsys_lock_t            *en_eslp;
 658         efsys_bar_t             *en_esbp;
 659         unsigned int            en_mod_flags;
 660         unsigned int            en_reset_flags;
 661         efx_nic_cfg_t           en_nic_cfg;
 662         efx_drv_cfg_t           en_drv_cfg;
 663         efx_port_t              en_port;
 664         efx_mon_t               en_mon;
 665         efx_intr_t              en_intr;
 666         uint32_t                en_ev_qcount;
 667         uint32_t                en_rx_qcount;
 668         uint32_t                en_tx_qcount;
 669         const efx_nic_ops_t     *en_enop;
 670         const efx_ev_ops_t      *en_eevop;
 671         const efx_tx_ops_t      *en_etxop;
 672         const efx_rx_ops_t      *en_erxop;
 673         efx_fw_variant_t        efv;
 674 #if EFSYS_OPT_FILTER
 675         efx_filter_t            en_filter;
 676         const efx_filter_ops_t  *en_efop;
 677 #endif  /* EFSYS_OPT_FILTER */
 678 #if EFSYS_OPT_TUNNEL
 679         efx_tunnel_cfg_t        en_tunnel_cfg;
 680         const efx_tunnel_ops_t  *en_etop;
 681 #endif /* EFSYS_OPT_TUNNEL */
 682 #if EFSYS_OPT_MCDI
 683         efx_mcdi_t              en_mcdi;
 684 #endif  /* EFSYS_OPT_MCDI */
 685 #if EFSYS_OPT_NVRAM
 686         uint32_t                en_nvram_partn_locked;
 687         const efx_nvram_ops_t   *en_envop;
 688 #endif  /* EFSYS_OPT_NVRAM */
 689 #if EFSYS_OPT_VPD
 690         const efx_vpd_ops_t     *en_evpdop;
 691 #endif  /* EFSYS_OPT_VPD */
 692 #if EFSYS_OPT_RX_SCALE
 693         efx_rx_hash_support_t           en_hash_support;
 694         efx_rx_scale_context_type_t     en_rss_context_type;
 695         uint32_t                        en_rss_context;
 696 #endif  /* EFSYS_OPT_RX_SCALE */
 697         uint32_t                en_vport_id;
 698 #if EFSYS_OPT_LICENSING
 699         const efx_lic_ops_t     *en_elop;
 700         boolean_t               en_licensing_supported;
 701 #endif
 702         union {
 703 #if EFSYS_OPT_SIENA
 704                 struct {
 705 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 706                         unsigned int            enu_partn_mask;
 707 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 708 #if EFSYS_OPT_VPD
 709                         caddr_t                 enu_svpd;
 710                         size_t                  enu_svpd_length;
 711 #endif  /* EFSYS_OPT_VPD */
 712                         int                     enu_unused;
 713                 } siena;
 714 #endif  /* EFSYS_OPT_SIENA */
 715                 int     enu_unused;
 716         } en_u;
 717 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
 718         union en_arch {
 719                 struct {
 720                         int                     ena_vi_base;
 721                         int                     ena_vi_count;
 722                         int                     ena_vi_shift;
 723 #if EFSYS_OPT_VPD
 724                         caddr_t                 ena_svpd;
 725                         size_t                  ena_svpd_length;
 726 #endif  /* EFSYS_OPT_VPD */
 727                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 728                         uint32_t                ena_piobuf_count;
 729                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 730                         uint32_t                ena_pio_write_vi_base;
 731                         /* Memory BAR mapping regions */
 732                         uint32_t                ena_uc_mem_map_offset;
 733                         size_t                  ena_uc_mem_map_size;
 734                         uint32_t                ena_wc_mem_map_offset;
 735                         size_t                  ena_wc_mem_map_size;
 736                 } ef10;
 737         } en_arch;
 738 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 739 };
 740
 741
 742 #define EFX_NIC_MAGIC   0x02121996
 743
 744 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 745     const efx_ev_callbacks_t *, void *);
 746
 747 typedef struct efx_evq_rxq_state_s {
 748         unsigned int                    eers_rx_read_ptr;
 749         unsigned int                    eers_rx_mask;
 750 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 751         unsigned int                    eers_rx_stream_npackets;
 752         boolean_t                       eers_rx_packed_stream;
 753 #endif
 754 #if EFSYS_OPT_RX_PACKED_STREAM
 755         unsigned int                    eers_rx_packed_stream_credits;
 756 #endif
 757 } efx_evq_rxq_state_t;
 758
 759 struct efx_evq_s {
 760         uint32_t                        ee_magic;
 761         efx_nic_t                       *ee_enp;
 762         unsigned int                    ee_index;
 763         unsigned int                    ee_mask;
 764         efsys_mem_t                     *ee_esmp;
 765 #if EFSYS_OPT_QSTATS
 766         uint32_t                        ee_stat[EV_NQSTATS];
 767 #endif  /* EFSYS_OPT_QSTATS */
 768
 769         efx_ev_handler_t                ee_rx;
 770         efx_ev_handler_t                ee_tx;
 771         efx_ev_handler_t                ee_driver;
 772         efx_ev_handler_t                ee_global;
 773         efx_ev_handler_t                ee_drv_gen;
 774 #if EFSYS_OPT_MCDI
 775         efx_ev_handler_t                ee_mcdi;
 776 #endif  /* EFSYS_OPT_MCDI */
 777
 778         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 779
 780         uint32_t                        ee_flags;
 781 };
 782
 783 #define EFX_EVQ_MAGIC   0x08081997
 784
 785 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 786
 787 struct efx_rxq_s {
 788         uint32_t                        er_magic;
 789         efx_nic_t                       *er_enp;
 790         efx_evq_t                       *er_eep;
 791         unsigned int                    er_index;
 792         unsigned int                    er_label;
 793         unsigned int                    er_mask;
 794         efsys_mem_t                     *er_esmp;
 795         efx_evq_rxq_state_t             *er_ev_qstate;
 796 };
 797
 798 #define EFX_RXQ_MAGIC   0x15022005
 799
 800 struct efx_txq_s {
 801         uint32_t                        et_magic;
 802         efx_nic_t                       *et_enp;
 803         unsigned int                    et_index;
 804         unsigned int                    et_mask;
 805         efsys_mem_t                     *et_esmp;
 806 #if EFSYS_OPT_HUNTINGTON
 807         uint32_t                        et_pio_bufnum;
 808         uint32_t                        et_pio_blknum;
 809         uint32_t                        et_pio_write_offset;
 810         uint32_t                        et_pio_offset;
 811         size_t                          et_pio_size;
 812 #endif
 813 #if EFSYS_OPT_QSTATS
 814         uint32_t                        et_stat[TX_NQSTATS];
 815 #endif  /* EFSYS_OPT_QSTATS */
 816 };
 817
 818 #define EFX_TXQ_MAGIC   0x05092005
 819
 820 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 821         do {                                                            \
 822                 (_dst)[0] = (_src)[0];                                  \
 823                 (_dst)[1] = (_src)[1];                                  \
 824                 (_dst)[2] = (_src)[2];                                  \
 825                 (_dst)[3] = (_src)[3];                                  \
 826                 (_dst)[4] = (_src)[4];                                  \
 827                 (_dst)[5] = (_src)[5];                                  \
 828         _NOTE(CONSTANTCONDITION)                                        \
 829         } while (B_FALSE)
 830
 831 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 832         do {                                                            \
 833                 uint16_t *_d = (uint16_t *)(_dst);                      \
 834                 _d[0] = 0xffff;                                         \
 835                 _d[1] = 0xffff;                                         \
 836                 _d[2] = 0xffff;                                         \
 837         _NOTE(CONSTANTCONDITION)                                        \
 838         } while (B_FALSE)
 839
 840 #if EFSYS_OPT_CHECK_REG
 841 #define EFX_CHECK_REG(_enp, _reg)                                       \
 842         do {                                                            \
 843                 const char *name = #_reg;                               \
 844                 char min = name[4];                                     \
 845                 char max = name[5];                                     \
 846                 char rev;                                               \
 847                                                                         \
 848                 switch ((_enp)->en_family) {                            \
 849                 case EFX_FAMILY_SIENA:                                  \
 850                         rev = 'C';                                      \
 851                         break;                                          \
 852                                                                         \
 853                 case EFX_FAMILY_HUNTINGTON:                             \
 854                         rev = 'D';                                      \
 855                         break;                                          \
 856                                                                         \
 857                 case EFX_FAMILY_MEDFORD:                                \
 858                         rev = 'E';                                      \
 859                         break;                                          \
 860                                                                         \
 861                 case EFX_FAMILY_MEDFORD2:                               \
 862                         rev = 'F';                                      \
 863                         break;                                          \
 864                                                                         \
 865                 default:                                                \
 866                         rev = '?';                                      \
 867                         break;                                          \
 868                 }                                                       \
 869                                                                         \
 870                 EFSYS_ASSERT3S(rev, >=, min);                           \
 871                 EFSYS_ASSERT3S(rev, <=, max);                           \
 872                                                                         \
 873         _NOTE(CONSTANTCONDITION)                                        \
 874         } while (B_FALSE)
 875 #else
 876 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 877         _NOTE(CONSTANTCONDITION)                                        \
 878         } while (B_FALSE)
 879 #endif
 880
 881 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 882         do {                                                            \
 883                 EFX_CHECK_REG((_enp), (_reg));                          \
 884                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 885                     (_edp), (_lock));                                   \
 886                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 887                     uint32_t, _reg ## _OFST,                            \
 888                     uint32_t, (_edp)->ed_u32[0]);                       \
 889         _NOTE(CONSTANTCONDITION)                                        \
 890         } while (B_FALSE)
 891
 892 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 893         do {                                                            \
 894                 EFX_CHECK_REG((_enp), (_reg));                          \
 895                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 896                     uint32_t, _reg ## _OFST,                            \
 897                     uint32_t, (_edp)->ed_u32[0]);                       \
 898                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 899                     (_edp), (_lock));                                   \
 900         _NOTE(CONSTANTCONDITION)                                        \
 901         } while (B_FALSE)
 902
 903 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 904         do {                                                            \
 905                 EFX_CHECK_REG((_enp), (_reg));                          \
 906                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 907                     (_eqp));                                            \
 908                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 909                     uint32_t, _reg ## _OFST,                            \
 910                     uint32_t, (_eqp)->eq_u32[1],                        \
 911                     uint32_t, (_eqp)->eq_u32[0]);                       \
 912         _NOTE(CONSTANTCONDITION)                                        \
 913         } while (B_FALSE)
 914
 915 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 916         do {                                                            \
 917                 EFX_CHECK_REG((_enp), (_reg));                          \
 918                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 919                     uint32_t, _reg ## _OFST,                            \
 920                     uint32_t, (_eqp)->eq_u32[1],                        \
 921                     uint32_t, (_eqp)->eq_u32[0]);                       \
 922                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 923                     (_eqp));                                            \
 924         _NOTE(CONSTANTCONDITION)                                        \
 925         } while (B_FALSE)
 926
 927 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 928         do {                                                            \
 929                 EFX_CHECK_REG((_enp), (_reg));                          \
 930                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 931                     (_eop), B_TRUE);                                    \
 932                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 933                     uint32_t, _reg ## _OFST,                            \
 934                     uint32_t, (_eop)->eo_u32[3],                        \
 935                     uint32_t, (_eop)->eo_u32[2],                        \
 936                     uint32_t, (_eop)->eo_u32[1],                        \
 937                     uint32_t, (_eop)->eo_u32[0]);                       \
 938         _NOTE(CONSTANTCONDITION)                                        \
 939         } while (B_FALSE)
 940
 941 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 942         do {                                                            \
 943                 EFX_CHECK_REG((_enp), (_reg));                          \
 944                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 945                     uint32_t, _reg ## _OFST,                            \
 946                     uint32_t, (_eop)->eo_u32[3],                        \
 947                     uint32_t, (_eop)->eo_u32[2],                        \
 948                     uint32_t, (_eop)->eo_u32[1],                        \
 949                     uint32_t, (_eop)->eo_u32[0]);                       \
 950                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 951                     (_eop), B_TRUE);                                    \
 952         _NOTE(CONSTANTCONDITION)                                        \
 953         } while (B_FALSE)
 954
 955 /*
 956  * Accessors for memory BAR non-VI tables.
 957  *
 958  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
 959  * to ensure the correct runtime VI window size is used on Medford2.
 960  *
 961  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
 962  */
 963
 964 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 965         do {                                                            \
 966                 EFX_CHECK_REG((_enp), (_reg));                          \
 967                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 968                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 969                     (_edp), (_lock));                                   \
 970                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 971                     uint32_t, (_index),                                 \
 972                     uint32_t, _reg ## _OFST,                            \
 973                     uint32_t, (_edp)->ed_u32[0]);                       \
 974         _NOTE(CONSTANTCONDITION)                                        \
 975         } while (B_FALSE)
 976
 977 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 978         do {                                                            \
 979                 EFX_CHECK_REG((_enp), (_reg));                          \
 980                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 981                     uint32_t, (_index),                                 \
 982                     uint32_t, _reg ## _OFST,                            \
 983                     uint32_t, (_edp)->ed_u32[0]);                       \
 984                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 985                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 986                     (_edp), (_lock));                                   \
 987         _NOTE(CONSTANTCONDITION)                                        \
 988         } while (B_FALSE)
 989
 990 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 991         do {                                                            \
 992                 EFX_CHECK_REG((_enp), (_reg));                          \
 993                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 994                     uint32_t, (_index),                                 \
 995                     uint32_t, _reg ## _OFST,                            \
 996                     uint32_t, (_edp)->ed_u32[0]);                       \
 997                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 998                     (_reg ## _OFST +                                    \
 999                     (3 * sizeof (efx_dword_t)) +                        \
1000                     ((_index) * _reg ## _STEP)),                        \
1001                     (_edp), (_lock));                                   \
1002         _NOTE(CONSTANTCONDITION)                                        \
1003         } while (B_FALSE)
1004
1005 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1006         do {                                                            \
1007                 EFX_CHECK_REG((_enp), (_reg));                          \
1008                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1009                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1010                     (_eqp));                                            \
1011                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1012                     uint32_t, (_index),                                 \
1013                     uint32_t, _reg ## _OFST,                            \
1014                     uint32_t, (_eqp)->eq_u32[1],                        \
1015                     uint32_t, (_eqp)->eq_u32[0]);                       \
1016         _NOTE(CONSTANTCONDITION)                                        \
1017         } while (B_FALSE)
1018
1019 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1020         do {                                                            \
1021                 EFX_CHECK_REG((_enp), (_reg));                          \
1022                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1023                     uint32_t, (_index),                                 \
1024                     uint32_t, _reg ## _OFST,                            \
1025                     uint32_t, (_eqp)->eq_u32[1],                        \
1026                     uint32_t, (_eqp)->eq_u32[0]);                       \
1027                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1028                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1029                     (_eqp));                                            \
1030         _NOTE(CONSTANTCONDITION)                                        \
1031         } while (B_FALSE)
1032
1033 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1034         do {                                                            \
1035                 EFX_CHECK_REG((_enp), (_reg));                          \
1036                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1037                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1038                     (_eop), (_lock));                                   \
1039                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1040                     uint32_t, (_index),                                 \
1041                     uint32_t, _reg ## _OFST,                            \
1042                     uint32_t, (_eop)->eo_u32[3],                        \
1043                     uint32_t, (_eop)->eo_u32[2],                        \
1044                     uint32_t, (_eop)->eo_u32[1],                        \
1045                     uint32_t, (_eop)->eo_u32[0]);                       \
1046         _NOTE(CONSTANTCONDITION)                                        \
1047         } while (B_FALSE)
1048
1049 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1050         do {                                                            \
1051                 EFX_CHECK_REG((_enp), (_reg));                          \
1052                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1053                     uint32_t, (_index),                                 \
1054                     uint32_t, _reg ## _OFST,                            \
1055                     uint32_t, (_eop)->eo_u32[3],                        \
1056                     uint32_t, (_eop)->eo_u32[2],                        \
1057                     uint32_t, (_eop)->eo_u32[1],                        \
1058                     uint32_t, (_eop)->eo_u32[0]);                       \
1059                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1060                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1061                     (_eop), (_lock));                                   \
1062         _NOTE(CONSTANTCONDITION)                                        \
1063         } while (B_FALSE)
1064
1065 /*
1066  * Accessors for memory BAR per-VI registers.
1067  *
1068  * The VI window size is 8KB for Medford and all earlier controllers.
1069  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1070  */
1071
1072 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1073         do {                                                            \
1074                 EFX_CHECK_REG((_enp), (_reg));                          \
1075                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1076                     ((_reg ## _OFST) +                                  \
1077                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1078                     (_edp), (_lock));                                   \
1079                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1080                     uint32_t, (_index),                                 \
1081                     uint32_t, _reg ## _OFST,                            \
1082                     uint32_t, (_edp)->ed_u32[0]);                       \
1083         _NOTE(CONSTANTCONDITION)                                        \
1084         } while (B_FALSE)
1085
1086 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1087         do {                                                            \
1088                 EFX_CHECK_REG((_enp), (_reg));                          \
1089                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1090                     uint32_t, (_index),                                 \
1091                     uint32_t, _reg ## _OFST,                            \
1092                     uint32_t, (_edp)->ed_u32[0]);                       \
1093                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1094                     ((_reg ## _OFST) +                                  \
1095                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1096                     (_edp), (_lock));                                   \
1097         _NOTE(CONSTANTCONDITION)                                        \
1098         } while (B_FALSE)
1099
1100 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1101         do {                                                            \
1102                 EFX_CHECK_REG((_enp), (_reg));                          \
1103                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1104                     uint32_t, (_index),                                 \
1105                     uint32_t, _reg ## _OFST,                            \
1106                     uint32_t, (_edp)->ed_u32[0]);                       \
1107                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1108                     ((_reg ## _OFST) +                                  \
1109                     (2 * sizeof (efx_dword_t)) +                        \
1110                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1111                     (_edp), (_lock));                                   \
1112         _NOTE(CONSTANTCONDITION)                                        \
1113         } while (B_FALSE)
1114
1115 /*
1116  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1117  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1118  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1119  * the need for locking in the host, and are the only ones known to be safe to
1120  * use 128-bites write with.
1121  */
1122 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1123         do {                                                            \
1124                 EFX_CHECK_REG((_enp), (_reg));                          \
1125                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1126                     const char *, #_reg,                                \
1127                     uint32_t, (_index),                                 \
1128                     uint32_t, _reg ## _OFST,                            \
1129                     uint32_t, (_eop)->eo_u32[3],                        \
1130                     uint32_t, (_eop)->eo_u32[2],                        \
1131                     uint32_t, (_eop)->eo_u32[1],                        \
1132                     uint32_t, (_eop)->eo_u32[0]);                       \
1133                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1134                     (_reg ## _OFST +                                    \
1135                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1136                     (_eop));                                            \
1137         _NOTE(CONSTANTCONDITION)                                        \
1138         } while (B_FALSE)
1139
1140 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1141         do {                                                            \
1142                 unsigned int _new = (_wptr);                            \
1143                 unsigned int _old = (_owptr);                           \
1144                                                                         \
1145                 if ((_new) >= (_old))                                   \
1146                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1147                             (_old) * sizeof (efx_desc_t),               \
1148                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1149                 else                                                    \
1150                         /*                                              \
1151                          * It is cheaper to sync entire map than sync   \
1152                          * two parts especially when offset/size are    \
1153                          * ignored and entire map is synced in any case.\
1154                          */                                             \
1155                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1156                             0,                                          \
1157                             (_entries) * sizeof (efx_desc_t));          \
1158         _NOTE(CONSTANTCONDITION)                                        \
1159         } while (B_FALSE)
1160
1161 extern  __checkReturn   efx_rc_t
1162 efx_mac_select(
1163         __in            efx_nic_t *enp);
1164
1165 extern  void
1166 efx_mac_multicast_hash_compute(
1167         __in_ecount(6*count)            uint8_t const *addrs,
1168         __in                            int count,
1169         __out                           efx_oword_t *hash_low,
1170         __out                           efx_oword_t *hash_high);
1171
1172 extern  __checkReturn   efx_rc_t
1173 efx_phy_probe(
1174         __in            efx_nic_t *enp);
1175
1176 extern                  void
1177 efx_phy_unprobe(
1178         __in            efx_nic_t *enp);
1179
1180 #if EFSYS_OPT_VPD
1181
1182 /* VPD utility functions */
1183
1184 extern  __checkReturn           efx_rc_t
1185 efx_vpd_hunk_length(
1186         __in_bcount(size)       caddr_t data,
1187         __in                    size_t size,
1188         __out                   size_t *lengthp);
1189
1190 extern  __checkReturn           efx_rc_t
1191 efx_vpd_hunk_verify(
1192         __in_bcount(size)       caddr_t data,
1193         __in                    size_t size,
1194         __out_opt               boolean_t *cksummedp);
1195
1196 extern  __checkReturn           efx_rc_t
1197 efx_vpd_hunk_reinit(
1198         __in_bcount(size)       caddr_t data,
1199         __in                    size_t size,
1200         __in                    boolean_t wantpid);
1201
1202 extern  __checkReturn           efx_rc_t
1203 efx_vpd_hunk_get(
1204         __in_bcount(size)       caddr_t data,
1205         __in                    size_t size,
1206         __in                    efx_vpd_tag_t tag,
1207         __in                    efx_vpd_keyword_t keyword,
1208         __out                   unsigned int *payloadp,
1209         __out                   uint8_t *paylenp);
1210
1211 extern  __checkReturn                   efx_rc_t
1212 efx_vpd_hunk_next(
1213         __in_bcount(size)               caddr_t data,
1214         __in                            size_t size,
1215         __out                           efx_vpd_tag_t *tagp,
1216         __out                           efx_vpd_keyword_t *keyword,
1217         __out_opt                       unsigned int *payloadp,
1218         __out_opt                       uint8_t *paylenp,
1219         __inout                         unsigned int *contp);
1220
1221 extern  __checkReturn           efx_rc_t
1222 efx_vpd_hunk_set(
1223         __in_bcount(size)       caddr_t data,
1224         __in                    size_t size,
1225         __in                    efx_vpd_value_t *evvp);
1226
1227 #endif  /* EFSYS_OPT_VPD */
1228
1229 #if EFSYS_OPT_MCDI
1230
1231 extern  __checkReturn           efx_rc_t
1232 efx_mcdi_set_workaround(
1233         __in                    efx_nic_t *enp,
1234         __in                    uint32_t type,
1235         __in                    boolean_t enabled,
1236         __out_opt               uint32_t *flagsp);
1237
1238 extern  __checkReturn           efx_rc_t
1239 efx_mcdi_get_workarounds(
1240         __in                    efx_nic_t *enp,
1241         __out_opt               uint32_t *implementedp,
1242         __out_opt               uint32_t *enabledp);
1243
1244 #endif /* EFSYS_OPT_MCDI */
1245
1246 #if EFSYS_OPT_MAC_STATS
1247
1248 /*
1249  * Closed range of stats (i.e. the first and the last are included).
1250  * The last must be greater or equal (if the range is one item only) to
1251  * the first.
1252  */
1253 struct efx_mac_stats_range {
1254         efx_mac_stat_t          first;
1255         efx_mac_stat_t          last;
1256 };
1257
1258 extern                                  efx_rc_t
1259 efx_mac_stats_mask_add_ranges(
1260         __inout_bcount(mask_size)       uint32_t *maskp,
1261         __in                            size_t mask_size,
1262         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1263         __in                            unsigned int rng_count);
1264
1265 #endif  /* EFSYS_OPT_MAC_STATS */
1266
1267 #ifdef  __cplusplus
1268 }
1269 #endif
1270
1271 #endif  /* _SYS_EFX_IMPL_H */