drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 } efx_ev_ops_t;
 101
 102 typedef struct efx_tx_ops_s {
 103         efx_rc_t        (*etxo_init)(efx_nic_t *);
 104         void            (*etxo_fini)(efx_nic_t *);
 105         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 106                                         unsigned int, unsigned int,
 107                                         efsys_mem_t *, size_t,
 108                                         uint32_t, uint16_t,
 109                                         efx_evq_t *, efx_txq_t *,
 110                                         unsigned int *);
 111         void            (*etxo_qdestroy)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 113                                       unsigned int, unsigned int,
 114                                       unsigned int *);
 115         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 116         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 117         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 118         void            (*etxo_qenable)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 120         void            (*etxo_qpio_disable)(efx_txq_t *);
 121         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 122                                            size_t);
 123         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 124                                            unsigned int *);
 125         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 126                                       unsigned int, unsigned int,
 127                                       unsigned int *);
 128         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 129                                                 size_t, boolean_t,
 130                                                 efx_desc_t *);
 131         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 132                                                 uint32_t, uint8_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint16_t,
 136                                                 efx_desc_t *, int);
 137         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 138                                                 efx_desc_t *);
 139 } efx_tx_ops_t;
 140
 141 typedef struct efx_rx_ops_s {
 142         efx_rc_t        (*erxo_init)(efx_nic_t *);
 143         void            (*erxo_fini)(efx_nic_t *);
 144         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 145                                               uint16_t *);
 146         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 147                                       unsigned int, unsigned int,
 148                                       unsigned int);
 149         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 150         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 151         void            (*erxo_qenable)(efx_rxq_t *);
 152         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 153                                         unsigned int, efx_rxq_type_t,
 154                                         efsys_mem_t *, size_t, uint32_t,
 155                                         efx_evq_t *, efx_rxq_t *);
 156         void            (*erxo_qdestroy)(efx_rxq_t *);
 157 } efx_rx_ops_t;
 158
 159 typedef struct efx_mac_ops_s {
 160         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 161         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 162         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 163         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 164         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 165         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 166         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 167         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 168                                                       efx_rxq_t *, boolean_t);
 169         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 170 } efx_mac_ops_t;
 171
 172 typedef struct efx_phy_ops_s {
 173         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 174         efx_rc_t        (*epo_reset)(efx_nic_t *);
 175         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 176         efx_rc_t        (*epo_verify)(efx_nic_t *);
 177         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 178 } efx_phy_ops_t;
 179
 180 #if EFSYS_OPT_FILTER
 181 typedef struct efx_filter_ops_s {
 182         efx_rc_t        (*efo_init)(efx_nic_t *);
 183         void            (*efo_fini)(efx_nic_t *);
 184         efx_rc_t        (*efo_restore)(efx_nic_t *);
 185         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 186                                    boolean_t may_replace);
 187         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 188         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 189         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 190                                    boolean_t, boolean_t, boolean_t,
 191                                    uint8_t const *, uint32_t);
 192 } efx_filter_ops_t;
 193
 194 extern  __checkReturn   efx_rc_t
 195 efx_filter_reconfigure(
 196         __in                            efx_nic_t *enp,
 197         __in_ecount(6)                  uint8_t const *mac_addr,
 198         __in                            boolean_t all_unicst,
 199         __in                            boolean_t mulcst,
 200         __in                            boolean_t all_mulcst,
 201         __in                            boolean_t brdcst,
 202         __in_ecount(6*count)            uint8_t const *addrs,
 203         __in                            uint32_t count);
 204
 205 #endif /* EFSYS_OPT_FILTER */
 206
 207
 208 typedef struct efx_port_s {
 209         efx_mac_type_t          ep_mac_type;
 210         uint32_t                ep_phy_type;
 211         uint8_t                 ep_port;
 212         uint32_t                ep_mac_pdu;
 213         uint8_t                 ep_mac_addr[6];
 214         efx_link_mode_t         ep_link_mode;
 215         boolean_t               ep_all_unicst;
 216         boolean_t               ep_mulcst;
 217         boolean_t               ep_all_mulcst;
 218         boolean_t               ep_brdcst;
 219         unsigned int            ep_fcntl;
 220         boolean_t               ep_fcntl_autoneg;
 221         efx_oword_t             ep_multicst_hash[2];
 222         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 223                                                     EFX_MAC_MULTICAST_LIST_MAX];
 224         uint32_t                ep_mulcst_addr_count;
 225         efx_phy_media_type_t    ep_fixed_port_type;
 226         efx_phy_media_type_t    ep_module_type;
 227         uint32_t                ep_adv_cap_mask;
 228         uint32_t                ep_lp_cap_mask;
 229         uint32_t                ep_default_adv_cap_mask;
 230         uint32_t                ep_phy_cap_mask;
 231         boolean_t               ep_mac_drain;
 232         boolean_t               ep_mac_stats_pending;
 233         const efx_mac_ops_t     *ep_emop;
 234         const efx_phy_ops_t     *ep_epop;
 235 } efx_port_t;
 236
 237 typedef struct efx_mon_ops_s {
 238 } efx_mon_ops_t;
 239
 240 typedef struct efx_mon_s {
 241         efx_mon_type_t          em_type;
 242         const efx_mon_ops_t     *em_emop;
 243 } efx_mon_t;
 244
 245 typedef struct efx_intr_ops_s {
 246         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 247         void            (*eio_enable)(efx_nic_t *);
 248         void            (*eio_disable)(efx_nic_t *);
 249         void            (*eio_disable_unlocked)(efx_nic_t *);
 250         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 251         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 252         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 253                                  boolean_t *);
 254         void            (*eio_fatal)(efx_nic_t *);
 255         void            (*eio_fini)(efx_nic_t *);
 256 } efx_intr_ops_t;
 257
 258 typedef struct efx_intr_s {
 259         const efx_intr_ops_t    *ei_eiop;
 260         efsys_mem_t             *ei_esmp;
 261         efx_intr_type_t         ei_type;
 262         unsigned int            ei_level;
 263 } efx_intr_t;
 264
 265 typedef struct efx_nic_ops_s {
 266         efx_rc_t        (*eno_probe)(efx_nic_t *);
 267         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 268         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 269         efx_rc_t        (*eno_reset)(efx_nic_t *);
 270         efx_rc_t        (*eno_init)(efx_nic_t *);
 271         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 272         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 273                                         uint32_t *, size_t *);
 274         void            (*eno_fini)(efx_nic_t *);
 275         void            (*eno_unprobe)(efx_nic_t *);
 276 } efx_nic_ops_t;
 277
 278 #ifndef EFX_TXQ_LIMIT_TARGET
 279 #define EFX_TXQ_LIMIT_TARGET 259
 280 #endif
 281 #ifndef EFX_RXQ_LIMIT_TARGET
 282 #define EFX_RXQ_LIMIT_TARGET 512
 283 #endif
 284 #ifndef EFX_TXQ_DC_SIZE
 285 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 286 #endif
 287 #ifndef EFX_RXQ_DC_SIZE
 288 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 289 #endif
 290
 291 #if EFSYS_OPT_FILTER
 292
 293 #if EFSYS_OPT_SIENA
 294
 295 typedef struct siena_filter_spec_s {
 296         uint8_t         sfs_type;
 297         uint32_t        sfs_flags;
 298         uint32_t        sfs_dmaq_id;
 299         uint32_t        sfs_dword[3];
 300 } siena_filter_spec_t;
 301
 302 typedef enum siena_filter_type_e {
 303         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 304         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 305         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 306         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 307         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 308         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 309
 310         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 311         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 312         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 313         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 314         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 315         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 316
 317         EFX_SIENA_FILTER_NTYPES
 318 } siena_filter_type_t;
 319
 320 typedef enum siena_filter_tbl_id_e {
 321         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 322         EFX_SIENA_FILTER_TBL_RX_MAC,
 323         EFX_SIENA_FILTER_TBL_TX_IP,
 324         EFX_SIENA_FILTER_TBL_TX_MAC,
 325         EFX_SIENA_FILTER_NTBLS
 326 } siena_filter_tbl_id_t;
 327
 328 typedef struct siena_filter_tbl_s {
 329         int                     sft_size;       /* number of entries */
 330         int                     sft_used;       /* active count */
 331         uint32_t                *sft_bitmap;    /* active bitmap */
 332         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 333 } siena_filter_tbl_t;
 334
 335 typedef struct siena_filter_s {
 336         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 337         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 338 } siena_filter_t;
 339
 340 #endif  /* EFSYS_OPT_SIENA */
 341
 342 typedef struct efx_filter_s {
 343 #if EFSYS_OPT_SIENA
 344         siena_filter_t          *ef_siena_filter;
 345 #endif /* EFSYS_OPT_SIENA */
 346 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 347         ef10_filter_table_t     *ef_ef10_filter_table;
 348 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 349 } efx_filter_t;
 350
 351 #if EFSYS_OPT_SIENA
 352
 353 extern                  void
 354 siena_filter_tbl_clear(
 355         __in            efx_nic_t *enp,
 356         __in            siena_filter_tbl_id_t tbl);
 357
 358 #endif  /* EFSYS_OPT_SIENA */
 359
 360 #endif  /* EFSYS_OPT_FILTER */
 361
 362 #if EFSYS_OPT_MCDI
 363
 364 typedef struct efx_mcdi_ops_s {
 365         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 366         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 367                                         void *, size_t);
 368         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 369         boolean_t       (*emco_poll_response)(efx_nic_t *);
 370         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 371         void            (*emco_fini)(efx_nic_t *);
 372         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 373                                             efx_mcdi_feature_id_t, boolean_t *);
 374         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 375                                             uint32_t *);
 376 } efx_mcdi_ops_t;
 377
 378 typedef struct efx_mcdi_s {
 379         const efx_mcdi_ops_t            *em_emcop;
 380         const efx_mcdi_transport_t      *em_emtp;
 381         efx_mcdi_iface_t                em_emip;
 382 } efx_mcdi_t;
 383
 384 #endif /* EFSYS_OPT_MCDI */
 385
 386 typedef struct efx_drv_cfg_s {
 387         uint32_t                edc_min_vi_count;
 388         uint32_t                edc_max_vi_count;
 389
 390         uint32_t                edc_max_piobuf_count;
 391         uint32_t                edc_pio_alloc_size;
 392 } efx_drv_cfg_t;
 393
 394 struct efx_nic_s {
 395         uint32_t                en_magic;
 396         efx_family_t            en_family;
 397         uint32_t                en_features;
 398         efsys_identifier_t      *en_esip;
 399         efsys_lock_t            *en_eslp;
 400         efsys_bar_t             *en_esbp;
 401         unsigned int            en_mod_flags;
 402         unsigned int            en_reset_flags;
 403         efx_nic_cfg_t           en_nic_cfg;
 404         efx_drv_cfg_t           en_drv_cfg;
 405         efx_port_t              en_port;
 406         efx_mon_t               en_mon;
 407         efx_intr_t              en_intr;
 408         uint32_t                en_ev_qcount;
 409         uint32_t                en_rx_qcount;
 410         uint32_t                en_tx_qcount;
 411         const efx_nic_ops_t     *en_enop;
 412         const efx_ev_ops_t      *en_eevop;
 413         const efx_tx_ops_t      *en_etxop;
 414         const efx_rx_ops_t      *en_erxop;
 415 #if EFSYS_OPT_FILTER
 416         efx_filter_t            en_filter;
 417         const efx_filter_ops_t  *en_efop;
 418 #endif  /* EFSYS_OPT_FILTER */
 419 #if EFSYS_OPT_MCDI
 420         efx_mcdi_t              en_mcdi;
 421 #endif  /* EFSYS_OPT_MCDI */
 422         uint32_t                en_vport_id;
 423         union {
 424 #if EFSYS_OPT_SIENA
 425                 struct {
 426                         int                     enu_unused;
 427                 } siena;
 428 #endif  /* EFSYS_OPT_SIENA */
 429                 int     enu_unused;
 430         } en_u;
 431 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 432         union en_arch {
 433                 struct {
 434                         int                     ena_vi_base;
 435                         int                     ena_vi_count;
 436                         int                     ena_vi_shift;
 437                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 438                         uint32_t                ena_piobuf_count;
 439                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 440                         uint32_t                ena_pio_write_vi_base;
 441                         /* Memory BAR mapping regions */
 442                         uint32_t                ena_uc_mem_map_offset;
 443                         size_t                  ena_uc_mem_map_size;
 444                         uint32_t                ena_wc_mem_map_offset;
 445                         size_t                  ena_wc_mem_map_size;
 446                 } ef10;
 447         } en_arch;
 448 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 449 };
 450
 451
 452 #define EFX_NIC_MAGIC   0x02121996
 453
 454 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 455     const efx_ev_callbacks_t *, void *);
 456
 457 typedef struct efx_evq_rxq_state_s {
 458         unsigned int                    eers_rx_read_ptr;
 459         unsigned int                    eers_rx_mask;
 460 } efx_evq_rxq_state_t;
 461
 462 struct efx_evq_s {
 463         uint32_t                        ee_magic;
 464         efx_nic_t                       *ee_enp;
 465         unsigned int                    ee_index;
 466         unsigned int                    ee_mask;
 467         efsys_mem_t                     *ee_esmp;
 468
 469         efx_ev_handler_t                ee_rx;
 470         efx_ev_handler_t                ee_tx;
 471         efx_ev_handler_t                ee_driver;
 472         efx_ev_handler_t                ee_global;
 473         efx_ev_handler_t                ee_drv_gen;
 474 #if EFSYS_OPT_MCDI
 475         efx_ev_handler_t                ee_mcdi;
 476 #endif  /* EFSYS_OPT_MCDI */
 477
 478         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 479
 480         uint32_t                        ee_flags;
 481 };
 482
 483 #define EFX_EVQ_MAGIC   0x08081997
 484
 485 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 486
 487 struct efx_rxq_s {
 488         uint32_t                        er_magic;
 489         efx_nic_t                       *er_enp;
 490         efx_evq_t                       *er_eep;
 491         unsigned int                    er_index;
 492         unsigned int                    er_label;
 493         unsigned int                    er_mask;
 494         efsys_mem_t                     *er_esmp;
 495 };
 496
 497 #define EFX_RXQ_MAGIC   0x15022005
 498
 499 struct efx_txq_s {
 500         uint32_t                        et_magic;
 501         efx_nic_t                       *et_enp;
 502         unsigned int                    et_index;
 503         unsigned int                    et_mask;
 504         efsys_mem_t                     *et_esmp;
 505 #if EFSYS_OPT_HUNTINGTON
 506         uint32_t                        et_pio_bufnum;
 507         uint32_t                        et_pio_blknum;
 508         uint32_t                        et_pio_write_offset;
 509         uint32_t                        et_pio_offset;
 510         size_t                          et_pio_size;
 511 #endif
 512 };
 513
 514 #define EFX_TXQ_MAGIC   0x05092005
 515
 516 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 517         do {                                                            \
 518                 (_dst)[0] = (_src)[0];                                  \
 519                 (_dst)[1] = (_src)[1];                                  \
 520                 (_dst)[2] = (_src)[2];                                  \
 521                 (_dst)[3] = (_src)[3];                                  \
 522                 (_dst)[4] = (_src)[4];                                  \
 523                 (_dst)[5] = (_src)[5];                                  \
 524         _NOTE(CONSTANTCONDITION)                                        \
 525         } while (B_FALSE)
 526
 527 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 528         do {                                                            \
 529                 uint16_t *_d = (uint16_t *)(_dst);                      \
 530                 _d[0] = 0xffff;                                         \
 531                 _d[1] = 0xffff;                                         \
 532                 _d[2] = 0xffff;                                         \
 533         _NOTE(CONSTANTCONDITION)                                        \
 534         } while (B_FALSE)
 535
 536 #if EFSYS_OPT_CHECK_REG
 537 #define EFX_CHECK_REG(_enp, _reg)                                       \
 538         do {                                                            \
 539                 const char *name = #_reg;                               \
 540                 char min = name[4];                                     \
 541                 char max = name[5];                                     \
 542                 char rev;                                               \
 543                                                                         \
 544                 switch ((_enp)->en_family) {                            \
 545                 case EFX_FAMILY_SIENA:                                  \
 546                         rev = 'C';                                      \
 547                         break;                                          \
 548                                                                         \
 549                 case EFX_FAMILY_HUNTINGTON:                             \
 550                         rev = 'D';                                      \
 551                         break;                                          \
 552                                                                         \
 553                 case EFX_FAMILY_MEDFORD:                                \
 554                         rev = 'E';                                      \
 555                         break;                                          \
 556                                                                         \
 557                 default:                                                \
 558                         rev = '?';                                      \
 559                         break;                                          \
 560                 }                                                       \
 561                                                                         \
 562                 EFSYS_ASSERT3S(rev, >=, min);                           \
 563                 EFSYS_ASSERT3S(rev, <=, max);                           \
 564                                                                         \
 565         _NOTE(CONSTANTCONDITION)                                        \
 566         } while (B_FALSE)
 567 #else
 568 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 569         _NOTE(CONSTANTCONDITION)                                        \
 570         } while (B_FALSE)
 571 #endif
 572
 573 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 574         do {                                                            \
 575                 EFX_CHECK_REG((_enp), (_reg));                          \
 576                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 577                     (_edp), (_lock));                                   \
 578                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 579                     uint32_t, _reg ## _OFST,                            \
 580                     uint32_t, (_edp)->ed_u32[0]);                       \
 581         _NOTE(CONSTANTCONDITION)                                        \
 582         } while (B_FALSE)
 583
 584 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 585         do {                                                            \
 586                 EFX_CHECK_REG((_enp), (_reg));                          \
 587                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 588                     uint32_t, _reg ## _OFST,                            \
 589                     uint32_t, (_edp)->ed_u32[0]);                       \
 590                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 591                     (_edp), (_lock));                                   \
 592         _NOTE(CONSTANTCONDITION)                                        \
 593         } while (B_FALSE)
 594
 595 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 596         do {                                                            \
 597                 EFX_CHECK_REG((_enp), (_reg));                          \
 598                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 599                     (_eqp));                                            \
 600                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 601                     uint32_t, _reg ## _OFST,                            \
 602                     uint32_t, (_eqp)->eq_u32[1],                        \
 603                     uint32_t, (_eqp)->eq_u32[0]);                       \
 604         _NOTE(CONSTANTCONDITION)                                        \
 605         } while (B_FALSE)
 606
 607 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 608         do {                                                            \
 609                 EFX_CHECK_REG((_enp), (_reg));                          \
 610                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 611                     uint32_t, _reg ## _OFST,                            \
 612                     uint32_t, (_eqp)->eq_u32[1],                        \
 613                     uint32_t, (_eqp)->eq_u32[0]);                       \
 614                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 615                     (_eqp));                                            \
 616         _NOTE(CONSTANTCONDITION)                                        \
 617         } while (B_FALSE)
 618
 619 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 620         do {                                                            \
 621                 EFX_CHECK_REG((_enp), (_reg));                          \
 622                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 623                     (_eop), B_TRUE);                                    \
 624                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 625                     uint32_t, _reg ## _OFST,                            \
 626                     uint32_t, (_eop)->eo_u32[3],                        \
 627                     uint32_t, (_eop)->eo_u32[2],                        \
 628                     uint32_t, (_eop)->eo_u32[1],                        \
 629                     uint32_t, (_eop)->eo_u32[0]);                       \
 630         _NOTE(CONSTANTCONDITION)                                        \
 631         } while (B_FALSE)
 632
 633 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 634         do {                                                            \
 635                 EFX_CHECK_REG((_enp), (_reg));                          \
 636                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 637                     uint32_t, _reg ## _OFST,                            \
 638                     uint32_t, (_eop)->eo_u32[3],                        \
 639                     uint32_t, (_eop)->eo_u32[2],                        \
 640                     uint32_t, (_eop)->eo_u32[1],                        \
 641                     uint32_t, (_eop)->eo_u32[0]);                       \
 642                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 643                     (_eop), B_TRUE);                                    \
 644         _NOTE(CONSTANTCONDITION)                                        \
 645         } while (B_FALSE)
 646
 647 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 648         do {                                                            \
 649                 EFX_CHECK_REG((_enp), (_reg));                          \
 650                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 651                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 652                     (_edp), (_lock));                                   \
 653                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 654                     uint32_t, (_index),                                 \
 655                     uint32_t, _reg ## _OFST,                            \
 656                     uint32_t, (_edp)->ed_u32[0]);                       \
 657         _NOTE(CONSTANTCONDITION)                                        \
 658         } while (B_FALSE)
 659
 660 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 661         do {                                                            \
 662                 EFX_CHECK_REG((_enp), (_reg));                          \
 663                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 664                     uint32_t, (_index),                                 \
 665                     uint32_t, _reg ## _OFST,                            \
 666                     uint32_t, (_edp)->ed_u32[0]);                       \
 667                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 668                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 669                     (_edp), (_lock));                                   \
 670         _NOTE(CONSTANTCONDITION)                                        \
 671         } while (B_FALSE)
 672
 673 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 674         do {                                                            \
 675                 EFX_CHECK_REG((_enp), (_reg));                          \
 676                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 677                     uint32_t, (_index),                                 \
 678                     uint32_t, _reg ## _OFST,                            \
 679                     uint32_t, (_edp)->ed_u32[0]);                       \
 680                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 681                     (_reg ## _OFST +                                    \
 682                     (2 * sizeof (efx_dword_t)) +                        \
 683                     ((_index) * _reg ## _STEP)),                        \
 684                     (_edp), (_lock));                                   \
 685         _NOTE(CONSTANTCONDITION)                                        \
 686         } while (B_FALSE)
 687
 688 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 689         do {                                                            \
 690                 EFX_CHECK_REG((_enp), (_reg));                          \
 691                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 692                     uint32_t, (_index),                                 \
 693                     uint32_t, _reg ## _OFST,                            \
 694                     uint32_t, (_edp)->ed_u32[0]);                       \
 695                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 696                     (_reg ## _OFST +                                    \
 697                     (3 * sizeof (efx_dword_t)) +                        \
 698                     ((_index) * _reg ## _STEP)),                        \
 699                     (_edp), (_lock));                                   \
 700         _NOTE(CONSTANTCONDITION)                                        \
 701         } while (B_FALSE)
 702
 703 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 704         do {                                                            \
 705                 EFX_CHECK_REG((_enp), (_reg));                          \
 706                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 707                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 708                     (_eqp));                                            \
 709                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 710                     uint32_t, (_index),                                 \
 711                     uint32_t, _reg ## _OFST,                            \
 712                     uint32_t, (_eqp)->eq_u32[1],                        \
 713                     uint32_t, (_eqp)->eq_u32[0]);                       \
 714         _NOTE(CONSTANTCONDITION)                                        \
 715         } while (B_FALSE)
 716
 717 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 718         do {                                                            \
 719                 EFX_CHECK_REG((_enp), (_reg));                          \
 720                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 721                     uint32_t, (_index),                                 \
 722                     uint32_t, _reg ## _OFST,                            \
 723                     uint32_t, (_eqp)->eq_u32[1],                        \
 724                     uint32_t, (_eqp)->eq_u32[0]);                       \
 725                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 726                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 727                     (_eqp));                                            \
 728         _NOTE(CONSTANTCONDITION)                                        \
 729         } while (B_FALSE)
 730
 731 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 732         do {                                                            \
 733                 EFX_CHECK_REG((_enp), (_reg));                          \
 734                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 735                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 736                     (_eop), (_lock));                                   \
 737                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 738                     uint32_t, (_index),                                 \
 739                     uint32_t, _reg ## _OFST,                            \
 740                     uint32_t, (_eop)->eo_u32[3],                        \
 741                     uint32_t, (_eop)->eo_u32[2],                        \
 742                     uint32_t, (_eop)->eo_u32[1],                        \
 743                     uint32_t, (_eop)->eo_u32[0]);                       \
 744         _NOTE(CONSTANTCONDITION)                                        \
 745         } while (B_FALSE)
 746
 747 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 748         do {                                                            \
 749                 EFX_CHECK_REG((_enp), (_reg));                          \
 750                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 751                     uint32_t, (_index),                                 \
 752                     uint32_t, _reg ## _OFST,                            \
 753                     uint32_t, (_eop)->eo_u32[3],                        \
 754                     uint32_t, (_eop)->eo_u32[2],                        \
 755                     uint32_t, (_eop)->eo_u32[1],                        \
 756                     uint32_t, (_eop)->eo_u32[0]);                       \
 757                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 758                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 759                     (_eop), (_lock));                                   \
 760         _NOTE(CONSTANTCONDITION)                                        \
 761         } while (B_FALSE)
 762
 763 /*
 764  * Allow drivers to perform optimised 128-bit doorbell writes.
 765  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 766  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 767  * the need for locking in the host, and are the only ones known to be safe to
 768  * use 128-bites write with.
 769  */
 770 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 771         do {                                                            \
 772                 EFX_CHECK_REG((_enp), (_reg));                          \
 773                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 774                     const char *,                                       \
 775                     #_reg,                                              \
 776                     uint32_t, (_index),                                 \
 777                     uint32_t, _reg ## _OFST,                            \
 778                     uint32_t, (_eop)->eo_u32[3],                        \
 779                     uint32_t, (_eop)->eo_u32[2],                        \
 780                     uint32_t, (_eop)->eo_u32[1],                        \
 781                     uint32_t, (_eop)->eo_u32[0]);                       \
 782                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
 783                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 784                     (_eop));                                            \
 785         _NOTE(CONSTANTCONDITION)                                        \
 786         } while (B_FALSE)
 787
 788 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
 789         do {                                                            \
 790                 unsigned int _new = (_wptr);                            \
 791                 unsigned int _old = (_owptr);                           \
 792                                                                         \
 793                 if ((_new) >= (_old))                                   \
 794                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 795                             (_old) * sizeof (efx_desc_t),               \
 796                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
 797                 else                                                    \
 798                         /*                                              \
 799                          * It is cheaper to sync entire map than sync   \
 800                          * two parts especially when offset/size are    \
 801                          * ignored and entire map is synced in any case.\
 802                          */                                             \
 803                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 804                             0,                                          \
 805                             (_entries) * sizeof (efx_desc_t));          \
 806         _NOTE(CONSTANTCONDITION)                                        \
 807         } while (B_FALSE)
 808
 809 extern  __checkReturn   efx_rc_t
 810 efx_nic_biu_test(
 811         __in            efx_nic_t *enp);
 812
 813 extern  __checkReturn   efx_rc_t
 814 efx_mac_select(
 815         __in            efx_nic_t *enp);
 816
 817 extern  void
 818 efx_mac_multicast_hash_compute(
 819         __in_ecount(6*count)            uint8_t const *addrs,
 820         __in                            int count,
 821         __out                           efx_oword_t *hash_low,
 822         __out                           efx_oword_t *hash_high);
 823
 824 extern  __checkReturn   efx_rc_t
 825 efx_phy_probe(
 826         __in            efx_nic_t *enp);
 827
 828 extern                  void
 829 efx_phy_unprobe(
 830         __in            efx_nic_t *enp);
 831
 832 #if EFSYS_OPT_MCDI
 833
 834 extern  __checkReturn           efx_rc_t
 835 efx_mcdi_set_workaround(
 836         __in                    efx_nic_t *enp,
 837         __in                    uint32_t type,
 838         __in                    boolean_t enabled,
 839         __out_opt               uint32_t *flagsp);
 840
 841 extern  __checkReturn           efx_rc_t
 842 efx_mcdi_get_workarounds(
 843         __in                    efx_nic_t *enp,
 844         __out_opt               uint32_t *implementedp,
 845         __out_opt               uint32_t *enabledp);
 846
 847 #endif /* EFSYS_OPT_MCDI */
 848
 849 #ifdef  __cplusplus
 850 }
 851 #endif
 852
 853 #endif  /* _SYS_EFX_IMPL_H */