drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 } efx_ev_ops_t;
 101
 102 typedef struct efx_tx_ops_s {
 103         efx_rc_t        (*etxo_init)(efx_nic_t *);
 104         void            (*etxo_fini)(efx_nic_t *);
 105         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 106                                         unsigned int, unsigned int,
 107                                         efsys_mem_t *, size_t,
 108                                         uint32_t, uint16_t,
 109                                         efx_evq_t *, efx_txq_t *,
 110                                         unsigned int *);
 111         void            (*etxo_qdestroy)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 113                                       unsigned int, unsigned int,
 114                                       unsigned int *);
 115         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 116         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 117         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 118         void            (*etxo_qenable)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 120         void            (*etxo_qpio_disable)(efx_txq_t *);
 121         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 122                                            size_t);
 123         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 124                                            unsigned int *);
 125         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 126                                       unsigned int, unsigned int,
 127                                       unsigned int *);
 128         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 129                                                 size_t, boolean_t,
 130                                                 efx_desc_t *);
 131         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 132                                                 uint32_t, uint8_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint16_t,
 136                                                 efx_desc_t *, int);
 137         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 138                                                 efx_desc_t *);
 139 } efx_tx_ops_t;
 140
 141 typedef struct efx_rx_ops_s {
 142         efx_rc_t        (*erxo_init)(efx_nic_t *);
 143         void            (*erxo_fini)(efx_nic_t *);
 144         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 145                                               uint16_t *);
 146         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 147                                       unsigned int, unsigned int,
 148                                       unsigned int);
 149         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 150         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 151         void            (*erxo_qenable)(efx_rxq_t *);
 152         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 153                                         unsigned int, efx_rxq_type_t,
 154                                         efsys_mem_t *, size_t, uint32_t,
 155                                         efx_evq_t *, efx_rxq_t *);
 156         void            (*erxo_qdestroy)(efx_rxq_t *);
 157 } efx_rx_ops_t;
 158
 159 typedef struct efx_mac_ops_s {
 160         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 161         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 162         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 163         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 164         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 165         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 166         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 167         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 168                                                       efx_rxq_t *, boolean_t);
 169         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 170 } efx_mac_ops_t;
 171
 172 typedef struct efx_phy_ops_s {
 173         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 174         efx_rc_t        (*epo_reset)(efx_nic_t *);
 175         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 176         efx_rc_t        (*epo_verify)(efx_nic_t *);
 177         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 178 #if EFSYS_OPT_BIST
 179         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 180         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 181         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 182                                          efx_bist_result_t *, uint32_t *,
 183                                          unsigned long *, size_t);
 184         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 185 #endif  /* EFSYS_OPT_BIST */
 186 } efx_phy_ops_t;
 187
 188 #if EFSYS_OPT_FILTER
 189 typedef struct efx_filter_ops_s {
 190         efx_rc_t        (*efo_init)(efx_nic_t *);
 191         void            (*efo_fini)(efx_nic_t *);
 192         efx_rc_t        (*efo_restore)(efx_nic_t *);
 193         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 194                                    boolean_t may_replace);
 195         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 196         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 197         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 198                                    boolean_t, boolean_t, boolean_t,
 199                                    uint8_t const *, uint32_t);
 200 } efx_filter_ops_t;
 201
 202 extern  __checkReturn   efx_rc_t
 203 efx_filter_reconfigure(
 204         __in                            efx_nic_t *enp,
 205         __in_ecount(6)                  uint8_t const *mac_addr,
 206         __in                            boolean_t all_unicst,
 207         __in                            boolean_t mulcst,
 208         __in                            boolean_t all_mulcst,
 209         __in                            boolean_t brdcst,
 210         __in_ecount(6*count)            uint8_t const *addrs,
 211         __in                            uint32_t count);
 212
 213 #endif /* EFSYS_OPT_FILTER */
 214
 215
 216 typedef struct efx_port_s {
 217         efx_mac_type_t          ep_mac_type;
 218         uint32_t                ep_phy_type;
 219         uint8_t                 ep_port;
 220         uint32_t                ep_mac_pdu;
 221         uint8_t                 ep_mac_addr[6];
 222         efx_link_mode_t         ep_link_mode;
 223         boolean_t               ep_all_unicst;
 224         boolean_t               ep_mulcst;
 225         boolean_t               ep_all_mulcst;
 226         boolean_t               ep_brdcst;
 227         unsigned int            ep_fcntl;
 228         boolean_t               ep_fcntl_autoneg;
 229         efx_oword_t             ep_multicst_hash[2];
 230         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 231                                                     EFX_MAC_MULTICAST_LIST_MAX];
 232         uint32_t                ep_mulcst_addr_count;
 233         efx_phy_media_type_t    ep_fixed_port_type;
 234         efx_phy_media_type_t    ep_module_type;
 235         uint32_t                ep_adv_cap_mask;
 236         uint32_t                ep_lp_cap_mask;
 237         uint32_t                ep_default_adv_cap_mask;
 238         uint32_t                ep_phy_cap_mask;
 239         boolean_t               ep_mac_drain;
 240         boolean_t               ep_mac_stats_pending;
 241 #if EFSYS_OPT_BIST
 242         efx_bist_type_t         ep_current_bist;
 243 #endif
 244         const efx_mac_ops_t     *ep_emop;
 245         const efx_phy_ops_t     *ep_epop;
 246 } efx_port_t;
 247
 248 typedef struct efx_mon_ops_s {
 249 } efx_mon_ops_t;
 250
 251 typedef struct efx_mon_s {
 252         efx_mon_type_t          em_type;
 253         const efx_mon_ops_t     *em_emop;
 254 } efx_mon_t;
 255
 256 typedef struct efx_intr_ops_s {
 257         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 258         void            (*eio_enable)(efx_nic_t *);
 259         void            (*eio_disable)(efx_nic_t *);
 260         void            (*eio_disable_unlocked)(efx_nic_t *);
 261         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 262         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 263         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 264                                  boolean_t *);
 265         void            (*eio_fatal)(efx_nic_t *);
 266         void            (*eio_fini)(efx_nic_t *);
 267 } efx_intr_ops_t;
 268
 269 typedef struct efx_intr_s {
 270         const efx_intr_ops_t    *ei_eiop;
 271         efsys_mem_t             *ei_esmp;
 272         efx_intr_type_t         ei_type;
 273         unsigned int            ei_level;
 274 } efx_intr_t;
 275
 276 typedef struct efx_nic_ops_s {
 277         efx_rc_t        (*eno_probe)(efx_nic_t *);
 278         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 279         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 280         efx_rc_t        (*eno_reset)(efx_nic_t *);
 281         efx_rc_t        (*eno_init)(efx_nic_t *);
 282         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 283         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 284                                         uint32_t *, size_t *);
 285 #if EFSYS_OPT_DIAG
 286         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 287 #endif  /* EFSYS_OPT_DIAG */
 288         void            (*eno_fini)(efx_nic_t *);
 289         void            (*eno_unprobe)(efx_nic_t *);
 290 } efx_nic_ops_t;
 291
 292 #ifndef EFX_TXQ_LIMIT_TARGET
 293 #define EFX_TXQ_LIMIT_TARGET 259
 294 #endif
 295 #ifndef EFX_RXQ_LIMIT_TARGET
 296 #define EFX_RXQ_LIMIT_TARGET 512
 297 #endif
 298 #ifndef EFX_TXQ_DC_SIZE
 299 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 300 #endif
 301 #ifndef EFX_RXQ_DC_SIZE
 302 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 303 #endif
 304
 305 #if EFSYS_OPT_FILTER
 306
 307 #if EFSYS_OPT_SIENA
 308
 309 typedef struct siena_filter_spec_s {
 310         uint8_t         sfs_type;
 311         uint32_t        sfs_flags;
 312         uint32_t        sfs_dmaq_id;
 313         uint32_t        sfs_dword[3];
 314 } siena_filter_spec_t;
 315
 316 typedef enum siena_filter_type_e {
 317         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 318         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 319         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 320         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 321         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 322         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 323
 324         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 325         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 326         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 327         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 328         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 329         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 330
 331         EFX_SIENA_FILTER_NTYPES
 332 } siena_filter_type_t;
 333
 334 typedef enum siena_filter_tbl_id_e {
 335         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 336         EFX_SIENA_FILTER_TBL_RX_MAC,
 337         EFX_SIENA_FILTER_TBL_TX_IP,
 338         EFX_SIENA_FILTER_TBL_TX_MAC,
 339         EFX_SIENA_FILTER_NTBLS
 340 } siena_filter_tbl_id_t;
 341
 342 typedef struct siena_filter_tbl_s {
 343         int                     sft_size;       /* number of entries */
 344         int                     sft_used;       /* active count */
 345         uint32_t                *sft_bitmap;    /* active bitmap */
 346         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 347 } siena_filter_tbl_t;
 348
 349 typedef struct siena_filter_s {
 350         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 351         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 352 } siena_filter_t;
 353
 354 #endif  /* EFSYS_OPT_SIENA */
 355
 356 typedef struct efx_filter_s {
 357 #if EFSYS_OPT_SIENA
 358         siena_filter_t          *ef_siena_filter;
 359 #endif /* EFSYS_OPT_SIENA */
 360 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 361         ef10_filter_table_t     *ef_ef10_filter_table;
 362 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 363 } efx_filter_t;
 364
 365 #if EFSYS_OPT_SIENA
 366
 367 extern                  void
 368 siena_filter_tbl_clear(
 369         __in            efx_nic_t *enp,
 370         __in            siena_filter_tbl_id_t tbl);
 371
 372 #endif  /* EFSYS_OPT_SIENA */
 373
 374 #endif  /* EFSYS_OPT_FILTER */
 375
 376 #if EFSYS_OPT_MCDI
 377
 378 typedef struct efx_mcdi_ops_s {
 379         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 380         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 381                                         void *, size_t);
 382         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 383         boolean_t       (*emco_poll_response)(efx_nic_t *);
 384         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 385         void            (*emco_fini)(efx_nic_t *);
 386         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 387                                             efx_mcdi_feature_id_t, boolean_t *);
 388         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 389                                             uint32_t *);
 390 } efx_mcdi_ops_t;
 391
 392 typedef struct efx_mcdi_s {
 393         const efx_mcdi_ops_t            *em_emcop;
 394         const efx_mcdi_transport_t      *em_emtp;
 395         efx_mcdi_iface_t                em_emip;
 396 } efx_mcdi_t;
 397
 398 #endif /* EFSYS_OPT_MCDI */
 399
 400 typedef struct efx_drv_cfg_s {
 401         uint32_t                edc_min_vi_count;
 402         uint32_t                edc_max_vi_count;
 403
 404         uint32_t                edc_max_piobuf_count;
 405         uint32_t                edc_pio_alloc_size;
 406 } efx_drv_cfg_t;
 407
 408 struct efx_nic_s {
 409         uint32_t                en_magic;
 410         efx_family_t            en_family;
 411         uint32_t                en_features;
 412         efsys_identifier_t      *en_esip;
 413         efsys_lock_t            *en_eslp;
 414         efsys_bar_t             *en_esbp;
 415         unsigned int            en_mod_flags;
 416         unsigned int            en_reset_flags;
 417         efx_nic_cfg_t           en_nic_cfg;
 418         efx_drv_cfg_t           en_drv_cfg;
 419         efx_port_t              en_port;
 420         efx_mon_t               en_mon;
 421         efx_intr_t              en_intr;
 422         uint32_t                en_ev_qcount;
 423         uint32_t                en_rx_qcount;
 424         uint32_t                en_tx_qcount;
 425         const efx_nic_ops_t     *en_enop;
 426         const efx_ev_ops_t      *en_eevop;
 427         const efx_tx_ops_t      *en_etxop;
 428         const efx_rx_ops_t      *en_erxop;
 429 #if EFSYS_OPT_FILTER
 430         efx_filter_t            en_filter;
 431         const efx_filter_ops_t  *en_efop;
 432 #endif  /* EFSYS_OPT_FILTER */
 433 #if EFSYS_OPT_MCDI
 434         efx_mcdi_t              en_mcdi;
 435 #endif  /* EFSYS_OPT_MCDI */
 436         uint32_t                en_vport_id;
 437         union {
 438 #if EFSYS_OPT_SIENA
 439                 struct {
 440                         int                     enu_unused;
 441                 } siena;
 442 #endif  /* EFSYS_OPT_SIENA */
 443                 int     enu_unused;
 444         } en_u;
 445 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 446         union en_arch {
 447                 struct {
 448                         int                     ena_vi_base;
 449                         int                     ena_vi_count;
 450                         int                     ena_vi_shift;
 451                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 452                         uint32_t                ena_piobuf_count;
 453                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 454                         uint32_t                ena_pio_write_vi_base;
 455                         /* Memory BAR mapping regions */
 456                         uint32_t                ena_uc_mem_map_offset;
 457                         size_t                  ena_uc_mem_map_size;
 458                         uint32_t                ena_wc_mem_map_offset;
 459                         size_t                  ena_wc_mem_map_size;
 460                 } ef10;
 461         } en_arch;
 462 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 463 };
 464
 465
 466 #define EFX_NIC_MAGIC   0x02121996
 467
 468 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 469     const efx_ev_callbacks_t *, void *);
 470
 471 typedef struct efx_evq_rxq_state_s {
 472         unsigned int                    eers_rx_read_ptr;
 473         unsigned int                    eers_rx_mask;
 474 } efx_evq_rxq_state_t;
 475
 476 struct efx_evq_s {
 477         uint32_t                        ee_magic;
 478         efx_nic_t                       *ee_enp;
 479         unsigned int                    ee_index;
 480         unsigned int                    ee_mask;
 481         efsys_mem_t                     *ee_esmp;
 482
 483         efx_ev_handler_t                ee_rx;
 484         efx_ev_handler_t                ee_tx;
 485         efx_ev_handler_t                ee_driver;
 486         efx_ev_handler_t                ee_global;
 487         efx_ev_handler_t                ee_drv_gen;
 488 #if EFSYS_OPT_MCDI
 489         efx_ev_handler_t                ee_mcdi;
 490 #endif  /* EFSYS_OPT_MCDI */
 491
 492         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 493
 494         uint32_t                        ee_flags;
 495 };
 496
 497 #define EFX_EVQ_MAGIC   0x08081997
 498
 499 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 500
 501 struct efx_rxq_s {
 502         uint32_t                        er_magic;
 503         efx_nic_t                       *er_enp;
 504         efx_evq_t                       *er_eep;
 505         unsigned int                    er_index;
 506         unsigned int                    er_label;
 507         unsigned int                    er_mask;
 508         efsys_mem_t                     *er_esmp;
 509 };
 510
 511 #define EFX_RXQ_MAGIC   0x15022005
 512
 513 struct efx_txq_s {
 514         uint32_t                        et_magic;
 515         efx_nic_t                       *et_enp;
 516         unsigned int                    et_index;
 517         unsigned int                    et_mask;
 518         efsys_mem_t                     *et_esmp;
 519 #if EFSYS_OPT_HUNTINGTON
 520         uint32_t                        et_pio_bufnum;
 521         uint32_t                        et_pio_blknum;
 522         uint32_t                        et_pio_write_offset;
 523         uint32_t                        et_pio_offset;
 524         size_t                          et_pio_size;
 525 #endif
 526 };
 527
 528 #define EFX_TXQ_MAGIC   0x05092005
 529
 530 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 531         do {                                                            \
 532                 (_dst)[0] = (_src)[0];                                  \
 533                 (_dst)[1] = (_src)[1];                                  \
 534                 (_dst)[2] = (_src)[2];                                  \
 535                 (_dst)[3] = (_src)[3];                                  \
 536                 (_dst)[4] = (_src)[4];                                  \
 537                 (_dst)[5] = (_src)[5];                                  \
 538         _NOTE(CONSTANTCONDITION)                                        \
 539         } while (B_FALSE)
 540
 541 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 542         do {                                                            \
 543                 uint16_t *_d = (uint16_t *)(_dst);                      \
 544                 _d[0] = 0xffff;                                         \
 545                 _d[1] = 0xffff;                                         \
 546                 _d[2] = 0xffff;                                         \
 547         _NOTE(CONSTANTCONDITION)                                        \
 548         } while (B_FALSE)
 549
 550 #if EFSYS_OPT_CHECK_REG
 551 #define EFX_CHECK_REG(_enp, _reg)                                       \
 552         do {                                                            \
 553                 const char *name = #_reg;                               \
 554                 char min = name[4];                                     \
 555                 char max = name[5];                                     \
 556                 char rev;                                               \
 557                                                                         \
 558                 switch ((_enp)->en_family) {                            \
 559                 case EFX_FAMILY_SIENA:                                  \
 560                         rev = 'C';                                      \
 561                         break;                                          \
 562                                                                         \
 563                 case EFX_FAMILY_HUNTINGTON:                             \
 564                         rev = 'D';                                      \
 565                         break;                                          \
 566                                                                         \
 567                 case EFX_FAMILY_MEDFORD:                                \
 568                         rev = 'E';                                      \
 569                         break;                                          \
 570                                                                         \
 571                 default:                                                \
 572                         rev = '?';                                      \
 573                         break;                                          \
 574                 }                                                       \
 575                                                                         \
 576                 EFSYS_ASSERT3S(rev, >=, min);                           \
 577                 EFSYS_ASSERT3S(rev, <=, max);                           \
 578                                                                         \
 579         _NOTE(CONSTANTCONDITION)                                        \
 580         } while (B_FALSE)
 581 #else
 582 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 583         _NOTE(CONSTANTCONDITION)                                        \
 584         } while (B_FALSE)
 585 #endif
 586
 587 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 588         do {                                                            \
 589                 EFX_CHECK_REG((_enp), (_reg));                          \
 590                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 591                     (_edp), (_lock));                                   \
 592                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 593                     uint32_t, _reg ## _OFST,                            \
 594                     uint32_t, (_edp)->ed_u32[0]);                       \
 595         _NOTE(CONSTANTCONDITION)                                        \
 596         } while (B_FALSE)
 597
 598 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 599         do {                                                            \
 600                 EFX_CHECK_REG((_enp), (_reg));                          \
 601                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 602                     uint32_t, _reg ## _OFST,                            \
 603                     uint32_t, (_edp)->ed_u32[0]);                       \
 604                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 605                     (_edp), (_lock));                                   \
 606         _NOTE(CONSTANTCONDITION)                                        \
 607         } while (B_FALSE)
 608
 609 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 610         do {                                                            \
 611                 EFX_CHECK_REG((_enp), (_reg));                          \
 612                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 613                     (_eqp));                                            \
 614                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 615                     uint32_t, _reg ## _OFST,                            \
 616                     uint32_t, (_eqp)->eq_u32[1],                        \
 617                     uint32_t, (_eqp)->eq_u32[0]);                       \
 618         _NOTE(CONSTANTCONDITION)                                        \
 619         } while (B_FALSE)
 620
 621 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 622         do {                                                            \
 623                 EFX_CHECK_REG((_enp), (_reg));                          \
 624                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 625                     uint32_t, _reg ## _OFST,                            \
 626                     uint32_t, (_eqp)->eq_u32[1],                        \
 627                     uint32_t, (_eqp)->eq_u32[0]);                       \
 628                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 629                     (_eqp));                                            \
 630         _NOTE(CONSTANTCONDITION)                                        \
 631         } while (B_FALSE)
 632
 633 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 634         do {                                                            \
 635                 EFX_CHECK_REG((_enp), (_reg));                          \
 636                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 637                     (_eop), B_TRUE);                                    \
 638                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 639                     uint32_t, _reg ## _OFST,                            \
 640                     uint32_t, (_eop)->eo_u32[3],                        \
 641                     uint32_t, (_eop)->eo_u32[2],                        \
 642                     uint32_t, (_eop)->eo_u32[1],                        \
 643                     uint32_t, (_eop)->eo_u32[0]);                       \
 644         _NOTE(CONSTANTCONDITION)                                        \
 645         } while (B_FALSE)
 646
 647 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 648         do {                                                            \
 649                 EFX_CHECK_REG((_enp), (_reg));                          \
 650                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 651                     uint32_t, _reg ## _OFST,                            \
 652                     uint32_t, (_eop)->eo_u32[3],                        \
 653                     uint32_t, (_eop)->eo_u32[2],                        \
 654                     uint32_t, (_eop)->eo_u32[1],                        \
 655                     uint32_t, (_eop)->eo_u32[0]);                       \
 656                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 657                     (_eop), B_TRUE);                                    \
 658         _NOTE(CONSTANTCONDITION)                                        \
 659         } while (B_FALSE)
 660
 661 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 662         do {                                                            \
 663                 EFX_CHECK_REG((_enp), (_reg));                          \
 664                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 665                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 666                     (_edp), (_lock));                                   \
 667                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 668                     uint32_t, (_index),                                 \
 669                     uint32_t, _reg ## _OFST,                            \
 670                     uint32_t, (_edp)->ed_u32[0]);                       \
 671         _NOTE(CONSTANTCONDITION)                                        \
 672         } while (B_FALSE)
 673
 674 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 675         do {                                                            \
 676                 EFX_CHECK_REG((_enp), (_reg));                          \
 677                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 678                     uint32_t, (_index),                                 \
 679                     uint32_t, _reg ## _OFST,                            \
 680                     uint32_t, (_edp)->ed_u32[0]);                       \
 681                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 682                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 683                     (_edp), (_lock));                                   \
 684         _NOTE(CONSTANTCONDITION)                                        \
 685         } while (B_FALSE)
 686
 687 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 688         do {                                                            \
 689                 EFX_CHECK_REG((_enp), (_reg));                          \
 690                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 691                     uint32_t, (_index),                                 \
 692                     uint32_t, _reg ## _OFST,                            \
 693                     uint32_t, (_edp)->ed_u32[0]);                       \
 694                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 695                     (_reg ## _OFST +                                    \
 696                     (2 * sizeof (efx_dword_t)) +                        \
 697                     ((_index) * _reg ## _STEP)),                        \
 698                     (_edp), (_lock));                                   \
 699         _NOTE(CONSTANTCONDITION)                                        \
 700         } while (B_FALSE)
 701
 702 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 703         do {                                                            \
 704                 EFX_CHECK_REG((_enp), (_reg));                          \
 705                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 706                     uint32_t, (_index),                                 \
 707                     uint32_t, _reg ## _OFST,                            \
 708                     uint32_t, (_edp)->ed_u32[0]);                       \
 709                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 710                     (_reg ## _OFST +                                    \
 711                     (3 * sizeof (efx_dword_t)) +                        \
 712                     ((_index) * _reg ## _STEP)),                        \
 713                     (_edp), (_lock));                                   \
 714         _NOTE(CONSTANTCONDITION)                                        \
 715         } while (B_FALSE)
 716
 717 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 718         do {                                                            \
 719                 EFX_CHECK_REG((_enp), (_reg));                          \
 720                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 721                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 722                     (_eqp));                                            \
 723                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 724                     uint32_t, (_index),                                 \
 725                     uint32_t, _reg ## _OFST,                            \
 726                     uint32_t, (_eqp)->eq_u32[1],                        \
 727                     uint32_t, (_eqp)->eq_u32[0]);                       \
 728         _NOTE(CONSTANTCONDITION)                                        \
 729         } while (B_FALSE)
 730
 731 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 732         do {                                                            \
 733                 EFX_CHECK_REG((_enp), (_reg));                          \
 734                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 735                     uint32_t, (_index),                                 \
 736                     uint32_t, _reg ## _OFST,                            \
 737                     uint32_t, (_eqp)->eq_u32[1],                        \
 738                     uint32_t, (_eqp)->eq_u32[0]);                       \
 739                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 740                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 741                     (_eqp));                                            \
 742         _NOTE(CONSTANTCONDITION)                                        \
 743         } while (B_FALSE)
 744
 745 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 746         do {                                                            \
 747                 EFX_CHECK_REG((_enp), (_reg));                          \
 748                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 749                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 750                     (_eop), (_lock));                                   \
 751                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 752                     uint32_t, (_index),                                 \
 753                     uint32_t, _reg ## _OFST,                            \
 754                     uint32_t, (_eop)->eo_u32[3],                        \
 755                     uint32_t, (_eop)->eo_u32[2],                        \
 756                     uint32_t, (_eop)->eo_u32[1],                        \
 757                     uint32_t, (_eop)->eo_u32[0]);                       \
 758         _NOTE(CONSTANTCONDITION)                                        \
 759         } while (B_FALSE)
 760
 761 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 762         do {                                                            \
 763                 EFX_CHECK_REG((_enp), (_reg));                          \
 764                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 765                     uint32_t, (_index),                                 \
 766                     uint32_t, _reg ## _OFST,                            \
 767                     uint32_t, (_eop)->eo_u32[3],                        \
 768                     uint32_t, (_eop)->eo_u32[2],                        \
 769                     uint32_t, (_eop)->eo_u32[1],                        \
 770                     uint32_t, (_eop)->eo_u32[0]);                       \
 771                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 772                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 773                     (_eop), (_lock));                                   \
 774         _NOTE(CONSTANTCONDITION)                                        \
 775         } while (B_FALSE)
 776
 777 /*
 778  * Allow drivers to perform optimised 128-bit doorbell writes.
 779  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 780  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 781  * the need for locking in the host, and are the only ones known to be safe to
 782  * use 128-bites write with.
 783  */
 784 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 785         do {                                                            \
 786                 EFX_CHECK_REG((_enp), (_reg));                          \
 787                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 788                     const char *,                                       \
 789                     #_reg,                                              \
 790                     uint32_t, (_index),                                 \
 791                     uint32_t, _reg ## _OFST,                            \
 792                     uint32_t, (_eop)->eo_u32[3],                        \
 793                     uint32_t, (_eop)->eo_u32[2],                        \
 794                     uint32_t, (_eop)->eo_u32[1],                        \
 795                     uint32_t, (_eop)->eo_u32[0]);                       \
 796                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
 797                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 798                     (_eop));                                            \
 799         _NOTE(CONSTANTCONDITION)                                        \
 800         } while (B_FALSE)
 801
 802 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
 803         do {                                                            \
 804                 unsigned int _new = (_wptr);                            \
 805                 unsigned int _old = (_owptr);                           \
 806                                                                         \
 807                 if ((_new) >= (_old))                                   \
 808                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 809                             (_old) * sizeof (efx_desc_t),               \
 810                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
 811                 else                                                    \
 812                         /*                                              \
 813                          * It is cheaper to sync entire map than sync   \
 814                          * two parts especially when offset/size are    \
 815                          * ignored and entire map is synced in any case.\
 816                          */                                             \
 817                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 818                             0,                                          \
 819                             (_entries) * sizeof (efx_desc_t));          \
 820         _NOTE(CONSTANTCONDITION)                                        \
 821         } while (B_FALSE)
 822
 823 extern  __checkReturn   efx_rc_t
 824 efx_nic_biu_test(
 825         __in            efx_nic_t *enp);
 826
 827 extern  __checkReturn   efx_rc_t
 828 efx_mac_select(
 829         __in            efx_nic_t *enp);
 830
 831 extern  void
 832 efx_mac_multicast_hash_compute(
 833         __in_ecount(6*count)            uint8_t const *addrs,
 834         __in                            int count,
 835         __out                           efx_oword_t *hash_low,
 836         __out                           efx_oword_t *hash_high);
 837
 838 extern  __checkReturn   efx_rc_t
 839 efx_phy_probe(
 840         __in            efx_nic_t *enp);
 841
 842 extern                  void
 843 efx_phy_unprobe(
 844         __in            efx_nic_t *enp);
 845
 846 #if EFSYS_OPT_DIAG
 847
 848 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
 849
 850 typedef struct efx_register_set_s {
 851         unsigned int            address;
 852         unsigned int            step;
 853         unsigned int            rows;
 854         efx_oword_t             mask;
 855 } efx_register_set_t;
 856
 857 extern  __checkReturn   efx_rc_t
 858 efx_nic_test_registers(
 859         __in            efx_nic_t *enp,
 860         __in            efx_register_set_t *rsp,
 861         __in            size_t count);
 862
 863 extern  __checkReturn   efx_rc_t
 864 efx_nic_test_tables(
 865         __in            efx_nic_t *enp,
 866         __in            efx_register_set_t *rsp,
 867         __in            efx_pattern_type_t pattern,
 868         __in            size_t count);
 869
 870 #endif  /* EFSYS_OPT_DIAG */
 871
 872 #if EFSYS_OPT_MCDI
 873
 874 extern  __checkReturn           efx_rc_t
 875 efx_mcdi_set_workaround(
 876         __in                    efx_nic_t *enp,
 877         __in                    uint32_t type,
 878         __in                    boolean_t enabled,
 879         __out_opt               uint32_t *flagsp);
 880
 881 extern  __checkReturn           efx_rc_t
 882 efx_mcdi_get_workarounds(
 883         __in                    efx_nic_t *enp,
 884         __out_opt               uint32_t *implementedp,
 885         __out_opt               uint32_t *enabledp);
 886
 887 #endif /* EFSYS_OPT_MCDI */
 888
 889 #ifdef  __cplusplus
 890 }
 891 #endif
 892
 893 #endif  /* _SYS_EFX_IMPL_H */