drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #if EFSYS_OPT_MCDI
  14 #include "efx_mcdi.h"
  15 #endif  /* EFSYS_OPT_MCDI */
  16
  17 /* FIXME: Add definition for driver generated software events */
  18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  20 #endif
  21
  22
  23 #if EFSYS_OPT_SIENA
  24 #include "siena_impl.h"
  25 #endif  /* EFSYS_OPT_SIENA */
  26
  27 #if EFSYS_OPT_HUNTINGTON
  28 #include "hunt_impl.h"
  29 #endif  /* EFSYS_OPT_HUNTINGTON */
  30
  31 #if EFSYS_OPT_MEDFORD
  32 #include "medford_impl.h"
  33 #endif  /* EFSYS_OPT_MEDFORD */
  34
  35 #if EFSYS_OPT_MEDFORD2
  36 #include "medford2_impl.h"
  37 #endif  /* EFSYS_OPT_MEDFORD2 */
  38
  39 #if EFX_OPTS_EF10()
  40 #include "ef10_impl.h"
  41 #endif  /* EFX_OPTS_EF10() */
  42
  43 #ifdef  __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define EFX_MOD_MCDI            0x00000001
  48 #define EFX_MOD_PROBE           0x00000002
  49 #define EFX_MOD_NVRAM           0x00000004
  50 #define EFX_MOD_VPD             0x00000008
  51 #define EFX_MOD_NIC             0x00000010
  52 #define EFX_MOD_INTR            0x00000020
  53 #define EFX_MOD_EV              0x00000040
  54 #define EFX_MOD_RX              0x00000080
  55 #define EFX_MOD_TX              0x00000100
  56 #define EFX_MOD_PORT            0x00000200
  57 #define EFX_MOD_MON             0x00000400
  58 #define EFX_MOD_FILTER          0x00001000
  59 #define EFX_MOD_LIC             0x00002000
  60 #define EFX_MOD_TUNNEL          0x00004000
  61 #define EFX_MOD_EVB             0x00008000
  62 #define EFX_MOD_PROXY           0x00010000
  63
  64 #define EFX_RESET_PHY           0x00000001
  65 #define EFX_RESET_RXQ_ERR       0x00000002
  66 #define EFX_RESET_TXQ_ERR       0x00000004
  67 #define EFX_RESET_HW_UNAVAIL    0x00000008
  68
  69 typedef enum efx_mac_type_e {
  70         EFX_MAC_INVALID = 0,
  71         EFX_MAC_SIENA,
  72         EFX_MAC_HUNTINGTON,
  73         EFX_MAC_MEDFORD,
  74         EFX_MAC_MEDFORD2,
  75         EFX_MAC_NTYPES
  76 } efx_mac_type_t;
  77
  78 typedef struct efx_ev_ops_s {
  79         efx_rc_t        (*eevo_init)(efx_nic_t *);
  80         void            (*eevo_fini)(efx_nic_t *);
  81         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  82                                           efsys_mem_t *, size_t, uint32_t,
  83                                           uint32_t, uint32_t, efx_evq_t *);
  84         void            (*eevo_qdestroy)(efx_evq_t *);
  85         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  86         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  87         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  88 #if EFSYS_OPT_QSTATS
  89         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  90 #endif
  91 } efx_ev_ops_t;
  92
  93 typedef struct efx_tx_ops_s {
  94         efx_rc_t        (*etxo_init)(efx_nic_t *);
  95         void            (*etxo_fini)(efx_nic_t *);
  96         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  97                                         unsigned int, unsigned int,
  98                                         efsys_mem_t *, size_t,
  99                                         uint32_t, uint16_t,
 100                                         efx_evq_t *, efx_txq_t *,
 101                                         unsigned int *);
 102         void            (*etxo_qdestroy)(efx_txq_t *);
 103         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 104                                       unsigned int, unsigned int,
 105                                       unsigned int *);
 106         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 107         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 108         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 109         void            (*etxo_qenable)(efx_txq_t *);
 110         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 111         void            (*etxo_qpio_disable)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 113                                            size_t);
 114         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 115                                            unsigned int *);
 116         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 117                                       unsigned int, unsigned int,
 118                                       unsigned int *);
 119         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 120                                                 size_t, boolean_t,
 121                                                 efx_desc_t *);
 122         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 123                                                 uint32_t, uint8_t,
 124                                                 efx_desc_t *);
 125         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 126                                                 uint16_t, uint32_t, uint16_t,
 127                                                 efx_desc_t *, int);
 128         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 129                                                 efx_desc_t *);
 130         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 131                                                 efx_desc_t *);
 132 #if EFSYS_OPT_QSTATS
 133         void            (*etxo_qstats_update)(efx_txq_t *,
 134                                               efsys_stat_t *);
 135 #endif
 136 } efx_tx_ops_t;
 137
 138 typedef union efx_rxq_type_data_u {
 139         struct {
 140                 size_t          ed_buf_size;
 141         } ertd_default;
 142 #if EFSYS_OPT_RX_PACKED_STREAM
 143         struct {
 144                 uint32_t        eps_buf_size;
 145         } ertd_packed_stream;
 146 #endif
 147 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 148         struct {
 149                 uint32_t        eessb_bufs_per_desc;
 150                 uint32_t        eessb_max_dma_len;
 151                 uint32_t        eessb_buf_stride;
 152                 uint32_t        eessb_hol_block_timeout;
 153         } ertd_es_super_buffer;
 154 #endif
 155 } efx_rxq_type_data_t;
 156
 157 typedef struct efx_rx_ops_s {
 158         efx_rc_t        (*erxo_init)(efx_nic_t *);
 159         void            (*erxo_fini)(efx_nic_t *);
 160 #if EFSYS_OPT_RX_SCATTER
 161         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 162 #endif
 163 #if EFSYS_OPT_RX_SCALE
 164         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 165                                                     efx_rx_scale_context_type_t,
 166                                                     uint32_t, uint32_t *);
 167         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 168         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 169                                                efx_rx_hash_alg_t,
 170                                                efx_rx_hash_type_t, boolean_t);
 171         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 172                                               uint8_t *, size_t);
 173         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 174                                               unsigned int *, size_t);
 175         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 176                                             uint8_t *);
 177 #endif /* EFSYS_OPT_RX_SCALE */
 178         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 179                                               uint16_t *);
 180         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 181                                       unsigned int, unsigned int,
 182                                       unsigned int);
 183         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 184 #if EFSYS_OPT_RX_PACKED_STREAM
 185         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 186         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 187                                                 uint32_t, uint32_t,
 188                                                 uint16_t *, uint32_t *, uint32_t *);
 189 #endif
 190         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 191         void            (*erxo_qenable)(efx_rxq_t *);
 192         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 193                                         unsigned int, efx_rxq_type_t,
 194                                         const efx_rxq_type_data_t *,
 195                                         efsys_mem_t *, size_t, uint32_t,
 196                                         unsigned int,
 197                                         efx_evq_t *, efx_rxq_t *);
 198         void            (*erxo_qdestroy)(efx_rxq_t *);
 199 } efx_rx_ops_t;
 200
 201 typedef struct efx_mac_ops_s {
 202         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 203         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 204         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 205         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 206         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 207         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 208         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 209         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 210                                                       efx_rxq_t *, boolean_t);
 211         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 212 #if EFSYS_OPT_LOOPBACK
 213         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 214                                             efx_loopback_type_t);
 215 #endif  /* EFSYS_OPT_LOOPBACK */
 216 #if EFSYS_OPT_MAC_STATS
 217         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 218         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 219         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 220         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 221                                               uint16_t, boolean_t);
 222         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 223                                             efsys_stat_t *, uint32_t *);
 224 #endif  /* EFSYS_OPT_MAC_STATS */
 225 } efx_mac_ops_t;
 226
 227 typedef struct efx_phy_ops_s {
 228         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 229         efx_rc_t        (*epo_reset)(efx_nic_t *);
 230         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 231         efx_rc_t        (*epo_verify)(efx_nic_t *);
 232         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 233         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 234 #if EFSYS_OPT_PHY_STATS
 235         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 236                                             uint32_t *);
 237 #endif  /* EFSYS_OPT_PHY_STATS */
 238 #if EFSYS_OPT_BIST
 239         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 240         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 241         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 242                                          efx_bist_result_t *, uint32_t *,
 243                                          unsigned long *, size_t);
 244         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 245 #endif  /* EFSYS_OPT_BIST */
 246 } efx_phy_ops_t;
 247
 248 #if EFSYS_OPT_FILTER
 249
 250 /*
 251  * Policy for replacing existing filter when inserting a new one.
 252  * Note that all policies allow for storing the new lower priority
 253  * filters as overridden by existing higher priority ones. It is needed
 254  * to restore the lower priority filters on higher priority ones removal.
 255  */
 256 typedef enum efx_filter_replacement_policy_e {
 257         /* Cannot replace existing filter */
 258         EFX_FILTER_REPLACEMENT_NEVER,
 259         /* Higher priority filters can replace lower priotiry ones */
 260         EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY,
 261         /*
 262          * Higher priority filters can replace lower priority ones and
 263          * equal priority filters can replace each other.
 264          */
 265         EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY,
 266 } efx_filter_replacement_policy_t;
 267
 268 typedef struct efx_filter_ops_s {
 269         efx_rc_t        (*efo_init)(efx_nic_t *);
 270         void            (*efo_fini)(efx_nic_t *);
 271         efx_rc_t        (*efo_restore)(efx_nic_t *);
 272         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 273                                    efx_filter_replacement_policy_t policy);
 274         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 275         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 276                                    size_t, size_t *);
 277         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 278                                    boolean_t, boolean_t, boolean_t,
 279                                    uint8_t const *, uint32_t);
 280 } efx_filter_ops_t;
 281
 282 extern  __checkReturn   efx_rc_t
 283 efx_filter_reconfigure(
 284         __in                            efx_nic_t *enp,
 285         __in_ecount(6)                  uint8_t const *mac_addr,
 286         __in                            boolean_t all_unicst,
 287         __in                            boolean_t mulcst,
 288         __in                            boolean_t all_mulcst,
 289         __in                            boolean_t brdcst,
 290         __in_ecount(6*count)            uint8_t const *addrs,
 291         __in                            uint32_t count);
 292
 293 #endif /* EFSYS_OPT_FILTER */
 294
 295 #if EFSYS_OPT_TUNNEL
 296 typedef struct efx_tunnel_ops_s {
 297         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 298         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 299 } efx_tunnel_ops_t;
 300 #endif /* EFSYS_OPT_TUNNEL */
 301
 302 typedef struct efx_port_s {
 303         efx_mac_type_t          ep_mac_type;
 304         uint32_t                ep_phy_type;
 305         uint8_t                 ep_port;
 306         uint32_t                ep_mac_pdu;
 307         uint8_t                 ep_mac_addr[6];
 308         efx_link_mode_t         ep_link_mode;
 309         boolean_t               ep_all_unicst;
 310         boolean_t               ep_all_unicst_inserted;
 311         boolean_t               ep_mulcst;
 312         boolean_t               ep_all_mulcst;
 313         boolean_t               ep_all_mulcst_inserted;
 314         boolean_t               ep_brdcst;
 315         unsigned int            ep_fcntl;
 316         boolean_t               ep_fcntl_autoneg;
 317         efx_oword_t             ep_multicst_hash[2];
 318         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 319                                                     EFX_MAC_MULTICAST_LIST_MAX];
 320         uint32_t                ep_mulcst_addr_count;
 321 #if EFSYS_OPT_LOOPBACK
 322         efx_loopback_type_t     ep_loopback_type;
 323         efx_link_mode_t         ep_loopback_link_mode;
 324 #endif  /* EFSYS_OPT_LOOPBACK */
 325 #if EFSYS_OPT_PHY_FLAGS
 326         uint32_t                ep_phy_flags;
 327 #endif  /* EFSYS_OPT_PHY_FLAGS */
 328 #if EFSYS_OPT_PHY_LED_CONTROL
 329         efx_phy_led_mode_t      ep_phy_led_mode;
 330 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 331         efx_phy_media_type_t    ep_fixed_port_type;
 332         efx_phy_media_type_t    ep_module_type;
 333         uint32_t                ep_adv_cap_mask;
 334         uint32_t                ep_lp_cap_mask;
 335         uint32_t                ep_default_adv_cap_mask;
 336         uint32_t                ep_phy_cap_mask;
 337         boolean_t               ep_mac_drain;
 338 #if EFSYS_OPT_BIST
 339         efx_bist_type_t         ep_current_bist;
 340 #endif
 341         const efx_mac_ops_t     *ep_emop;
 342         const efx_phy_ops_t     *ep_epop;
 343 } efx_port_t;
 344
 345 typedef struct efx_mon_ops_s {
 346 #if EFSYS_OPT_MON_STATS
 347         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 348                                             efx_mon_stat_value_t *);
 349         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 350                                              efx_mon_stat_limits_t *);
 351 #endif  /* EFSYS_OPT_MON_STATS */
 352 } efx_mon_ops_t;
 353
 354 typedef struct efx_mon_s {
 355         efx_mon_type_t          em_type;
 356         const efx_mon_ops_t     *em_emop;
 357 } efx_mon_t;
 358
 359 typedef struct efx_intr_ops_s {
 360         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 361         void            (*eio_enable)(efx_nic_t *);
 362         void            (*eio_disable)(efx_nic_t *);
 363         void            (*eio_disable_unlocked)(efx_nic_t *);
 364         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 365         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 366         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 367                                  boolean_t *);
 368         void            (*eio_fatal)(efx_nic_t *);
 369         void            (*eio_fini)(efx_nic_t *);
 370 } efx_intr_ops_t;
 371
 372 typedef struct efx_intr_s {
 373         const efx_intr_ops_t    *ei_eiop;
 374         efsys_mem_t             *ei_esmp;
 375         efx_intr_type_t         ei_type;
 376         unsigned int            ei_level;
 377 } efx_intr_t;
 378
 379 typedef struct efx_nic_ops_s {
 380         efx_rc_t        (*eno_probe)(efx_nic_t *);
 381         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 382         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 383         efx_rc_t        (*eno_reset)(efx_nic_t *);
 384         efx_rc_t        (*eno_init)(efx_nic_t *);
 385         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 386         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 387                                         uint32_t *, size_t *);
 388         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 389         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 390 #if EFSYS_OPT_DIAG
 391         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 392 #endif  /* EFSYS_OPT_DIAG */
 393         void            (*eno_fini)(efx_nic_t *);
 394         void            (*eno_unprobe)(efx_nic_t *);
 395 } efx_nic_ops_t;
 396
 397 #ifndef EFX_TXQ_LIMIT_TARGET
 398 #define EFX_TXQ_LIMIT_TARGET 259
 399 #endif
 400 #ifndef EFX_RXQ_LIMIT_TARGET
 401 #define EFX_RXQ_LIMIT_TARGET 512
 402 #endif
 403
 404
 405 #if EFSYS_OPT_FILTER
 406
 407 #if EFSYS_OPT_SIENA
 408
 409 typedef struct siena_filter_spec_s {
 410         uint8_t         sfs_type;
 411         uint32_t        sfs_flags;
 412         uint32_t        sfs_dmaq_id;
 413         uint32_t        sfs_dword[3];
 414 } siena_filter_spec_t;
 415
 416 typedef enum siena_filter_type_e {
 417         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 418         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 419         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 420         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 421         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 422         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 423
 424         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 425         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 426         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 427         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 428         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 429         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 430
 431         EFX_SIENA_FILTER_NTYPES
 432 } siena_filter_type_t;
 433
 434 typedef enum siena_filter_tbl_id_e {
 435         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 436         EFX_SIENA_FILTER_TBL_RX_MAC,
 437         EFX_SIENA_FILTER_TBL_TX_IP,
 438         EFX_SIENA_FILTER_TBL_TX_MAC,
 439         EFX_SIENA_FILTER_NTBLS
 440 } siena_filter_tbl_id_t;
 441
 442 typedef struct siena_filter_tbl_s {
 443         int                     sft_size;       /* number of entries */
 444         int                     sft_used;       /* active count */
 445         uint32_t                *sft_bitmap;    /* active bitmap */
 446         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 447 } siena_filter_tbl_t;
 448
 449 typedef struct siena_filter_s {
 450         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 451         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 452 } siena_filter_t;
 453
 454 #endif  /* EFSYS_OPT_SIENA */
 455
 456 typedef struct efx_filter_s {
 457 #if EFSYS_OPT_SIENA
 458         siena_filter_t          *ef_siena_filter;
 459 #endif /* EFSYS_OPT_SIENA */
 460 #if EFX_OPTS_EF10()
 461         ef10_filter_table_t     *ef_ef10_filter_table;
 462 #endif /* EFX_OPTS_EF10() */
 463 } efx_filter_t;
 464
 465 #if EFSYS_OPT_SIENA
 466
 467 extern                  void
 468 siena_filter_tbl_clear(
 469         __in            efx_nic_t *enp,
 470         __in            siena_filter_tbl_id_t tbl);
 471
 472 #endif  /* EFSYS_OPT_SIENA */
 473
 474 #endif  /* EFSYS_OPT_FILTER */
 475
 476 #if EFSYS_OPT_MCDI
 477
 478 #define EFX_TUNNEL_MAXNENTRIES  (16)
 479
 480 #if EFSYS_OPT_TUNNEL
 481
 482 typedef struct efx_tunnel_udp_entry_s {
 483         uint16_t                        etue_port; /* host/cpu-endian */
 484         uint16_t                        etue_protocol;
 485 } efx_tunnel_udp_entry_t;
 486
 487 typedef struct efx_tunnel_cfg_s {
 488         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 489         unsigned int            etc_udp_entries_num;
 490 } efx_tunnel_cfg_t;
 491
 492 #endif /* EFSYS_OPT_TUNNEL */
 493
 494 typedef struct efx_mcdi_ops_s {
 495         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 496         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 497                                         void *, size_t);
 498         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 499         boolean_t       (*emco_poll_response)(efx_nic_t *);
 500         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 501         void            (*emco_fini)(efx_nic_t *);
 502         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 503                                             efx_mcdi_feature_id_t, boolean_t *);
 504         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 505                                             uint32_t *);
 506 } efx_mcdi_ops_t;
 507
 508 typedef struct efx_mcdi_s {
 509         const efx_mcdi_ops_t            *em_emcop;
 510         const efx_mcdi_transport_t      *em_emtp;
 511         efx_mcdi_iface_t                em_emip;
 512 } efx_mcdi_t;
 513
 514 #endif /* EFSYS_OPT_MCDI */
 515
 516 #if EFSYS_OPT_NVRAM
 517
 518 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 519 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 520
 521 typedef struct efx_nvram_ops_s {
 522 #if EFSYS_OPT_DIAG
 523         efx_rc_t        (*envo_test)(efx_nic_t *);
 524 #endif  /* EFSYS_OPT_DIAG */
 525         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 526                                             uint32_t *);
 527         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 528                                             efx_nvram_info_t *);
 529         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 530         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 531                                             unsigned int, caddr_t, size_t);
 532         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 533                                             unsigned int, caddr_t, size_t);
 534         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 535                                             unsigned int, size_t);
 536         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 537                                             unsigned int, caddr_t, size_t);
 538         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 539                                             uint32_t *);
 540         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 541                                             uint32_t *, uint16_t *);
 542         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 543                                             uint16_t *);
 544         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 545                                             caddr_t, size_t);
 546 } efx_nvram_ops_t;
 547 #endif /* EFSYS_OPT_NVRAM */
 548
 549 #if EFSYS_OPT_VPD
 550 typedef struct efx_vpd_ops_s {
 551         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 552         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 553         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 554         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 555         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 556         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 557                                         efx_vpd_value_t *);
 558         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 559                                         efx_vpd_value_t *);
 560         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 561                                         efx_vpd_value_t *, unsigned int *);
 562         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 563         void            (*evpdo_fini)(efx_nic_t *);
 564 } efx_vpd_ops_t;
 565 #endif  /* EFSYS_OPT_VPD */
 566
 567 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 568
 569         __checkReturn           efx_rc_t
 570 efx_mcdi_nvram_partitions(
 571         __in                    efx_nic_t *enp,
 572         __out_bcount(size)      caddr_t data,
 573         __in                    size_t size,
 574         __out                   unsigned int *npartnp);
 575
 576         __checkReturn           efx_rc_t
 577 efx_mcdi_nvram_metadata(
 578         __in                    efx_nic_t *enp,
 579         __in                    uint32_t partn,
 580         __out                   uint32_t *subtypep,
 581         __out_ecount(4)         uint16_t version[4],
 582         __out_bcount_opt(size)  char *descp,
 583         __in                    size_t size);
 584
 585         __checkReturn           efx_rc_t
 586 efx_mcdi_nvram_info(
 587         __in                    efx_nic_t *enp,
 588         __in                    uint32_t partn,
 589         __out                   efx_nvram_info_t *eni);
 590
 591         __checkReturn           efx_rc_t
 592 efx_mcdi_nvram_update_start(
 593         __in                    efx_nic_t *enp,
 594         __in                    uint32_t partn);
 595
 596         __checkReturn           efx_rc_t
 597 efx_mcdi_nvram_read(
 598         __in                    efx_nic_t *enp,
 599         __in                    uint32_t partn,
 600         __in                    uint32_t offset,
 601         __out_bcount(size)      caddr_t data,
 602         __in                    size_t size,
 603         __in                    uint32_t mode);
 604
 605         __checkReturn           efx_rc_t
 606 efx_mcdi_nvram_erase(
 607         __in                    efx_nic_t *enp,
 608         __in                    uint32_t partn,
 609         __in                    uint32_t offset,
 610         __in                    size_t size);
 611
 612         __checkReturn           efx_rc_t
 613 efx_mcdi_nvram_write(
 614         __in                    efx_nic_t *enp,
 615         __in                    uint32_t partn,
 616         __in                    uint32_t offset,
 617         __in_bcount(size)       caddr_t data,
 618         __in                    size_t size);
 619
 620 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 621 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 622
 623         __checkReturn           efx_rc_t
 624 efx_mcdi_nvram_update_finish(
 625         __in                    efx_nic_t *enp,
 626         __in                    uint32_t partn,
 627         __in                    boolean_t reboot,
 628         __in                    uint32_t flags,
 629         __out_opt               uint32_t *verify_resultp);
 630
 631 #if EFSYS_OPT_DIAG
 632
 633         __checkReturn           efx_rc_t
 634 efx_mcdi_nvram_test(
 635         __in                    efx_nic_t *enp,
 636         __in                    uint32_t partn);
 637
 638 #endif  /* EFSYS_OPT_DIAG */
 639
 640 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 641
 642 #if EFSYS_OPT_LICENSING
 643
 644 typedef struct efx_lic_ops_s {
 645         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 646         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 647         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 648         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 649                                       size_t *, uint8_t *);
 650         efx_rc_t        (*elo_find_start)
 651                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 652         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 653                                 uint32_t, uint32_t *);
 654         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 655                                 uint32_t, uint32_t *, uint32_t *);
 656         boolean_t       (*elo_validate_key)(efx_nic_t *,
 657                                 caddr_t, uint32_t);
 658         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 659                                 caddr_t, size_t, uint32_t, uint32_t,
 660                                 caddr_t, size_t, uint32_t *);
 661         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 662                                 caddr_t, size_t, uint32_t,
 663                                 caddr_t, uint32_t, uint32_t *);
 664         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 665                                 caddr_t, size_t, uint32_t,
 666                                 uint32_t, uint32_t, uint32_t *);
 667         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 668                                 caddr_t, size_t);
 669         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 670                                 caddr_t, size_t);
 671 } efx_lic_ops_t;
 672
 673 #endif
 674
 675 #if EFSYS_OPT_EVB
 676
 677 struct efx_vswitch_s {
 678         efx_nic_t               *ev_enp;
 679         efx_vswitch_id_t        ev_vswitch_id;
 680         uint32_t                ev_num_vports;
 681         /*
 682          * Vport configuration array: index 0 to store PF configuration
 683          * and next ev_num_vports-1 entries hold VFs configuration.
 684          */
 685         efx_vport_config_t      *ev_evcp;
 686 };
 687
 688 typedef struct efx_evb_ops_s {
 689         efx_rc_t        (*eeo_init)(efx_nic_t *);
 690         void            (*eeo_fini)(efx_nic_t *);
 691         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 692         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 693         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 694                                                 efx_vport_type_t, uint16_t,
 695                                                 boolean_t, efx_vport_id_t *);
 696         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 697                                                 efx_vport_id_t);
 698         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 699                                                 efx_vport_id_t, uint8_t *);
 700         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 701                                                 efx_vport_id_t, uint8_t *);
 702         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 703                                                 efx_vport_id_t);
 704         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 705                                                 efx_vport_id_t);
 706         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 707                                                 efx_vport_id_t, uint32_t);
 708         efx_rc_t        (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
 709                                                         efx_vport_id_t,
 710                                                         uint16_t *, uint8_t *,
 711                                                         boolean_t *);
 712         efx_rc_t        (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
 713                                                 efx_vport_id_t, efsys_mem_t *);
 714 } efx_evb_ops_t;
 715
 716 extern __checkReturn    boolean_t
 717 efx_is_zero_eth_addr(
 718         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 719
 720 #endif /* EFSYS_OPT_EVB */
 721
 722 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 723
 724 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 725
 726
 727 typedef struct efx_proxy_ops_s {
 728         efx_rc_t        (*epo_init)(efx_nic_t *);
 729         void            (*epo_fini)(efx_nic_t *);
 730         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 731                                         efsys_mem_t *, efsys_mem_t *,
 732                                         uint32_t, uint32_t *, size_t);
 733         efx_rc_t        (*epo_disable)(efx_nic_t *);
 734         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 735                                         uint32_t, uint32_t, uint32_t);
 736         efx_rc_t        (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
 737                                         uint32_t, uint32_t);
 738         efx_rc_t        (*epo_complete_request)(efx_nic_t *, uint32_t,
 739                                         uint32_t, uint32_t);
 740         efx_rc_t        (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
 741         efx_rc_t        (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
 742                                         uint32_t, uint32_t *);
 743 } efx_proxy_ops_t;
 744
 745 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 746
 747 #define EFX_DRV_VER_MAX         20
 748
 749 typedef struct efx_drv_cfg_s {
 750         uint32_t                edc_min_vi_count;
 751         uint32_t                edc_max_vi_count;
 752
 753         uint32_t                edc_max_piobuf_count;
 754         uint32_t                edc_pio_alloc_size;
 755 } efx_drv_cfg_t;
 756
 757 struct efx_nic_s {
 758         uint32_t                en_magic;
 759         efx_family_t            en_family;
 760         uint32_t                en_features;
 761         efsys_identifier_t      *en_esip;
 762         efsys_lock_t            *en_eslp;
 763         efsys_bar_t             *en_esbp;
 764         unsigned int            en_mod_flags;
 765         unsigned int            en_reset_flags;
 766         efx_nic_cfg_t           en_nic_cfg;
 767         efx_drv_cfg_t           en_drv_cfg;
 768         efx_port_t              en_port;
 769         efx_mon_t               en_mon;
 770         efx_intr_t              en_intr;
 771         uint32_t                en_ev_qcount;
 772         uint32_t                en_rx_qcount;
 773         uint32_t                en_tx_qcount;
 774         const efx_nic_ops_t     *en_enop;
 775         const efx_ev_ops_t      *en_eevop;
 776         const efx_tx_ops_t      *en_etxop;
 777         const efx_rx_ops_t      *en_erxop;
 778         efx_fw_variant_t        efv;
 779         char                    en_drv_version[EFX_DRV_VER_MAX];
 780 #if EFSYS_OPT_FILTER
 781         efx_filter_t            en_filter;
 782         const efx_filter_ops_t  *en_efop;
 783 #endif  /* EFSYS_OPT_FILTER */
 784 #if EFSYS_OPT_TUNNEL
 785         efx_tunnel_cfg_t        en_tunnel_cfg;
 786         const efx_tunnel_ops_t  *en_etop;
 787 #endif /* EFSYS_OPT_TUNNEL */
 788 #if EFSYS_OPT_MCDI
 789         efx_mcdi_t              en_mcdi;
 790 #endif  /* EFSYS_OPT_MCDI */
 791 #if EFSYS_OPT_NVRAM
 792         uint32_t                en_nvram_partn_locked;
 793         const efx_nvram_ops_t   *en_envop;
 794 #endif  /* EFSYS_OPT_NVRAM */
 795 #if EFSYS_OPT_VPD
 796         const efx_vpd_ops_t     *en_evpdop;
 797 #endif  /* EFSYS_OPT_VPD */
 798 #if EFSYS_OPT_RX_SCALE
 799         efx_rx_hash_support_t           en_hash_support;
 800         efx_rx_scale_context_type_t     en_rss_context_type;
 801         uint32_t                        en_rss_context;
 802 #endif  /* EFSYS_OPT_RX_SCALE */
 803         uint32_t                en_vport_id;
 804 #if EFSYS_OPT_LICENSING
 805         const efx_lic_ops_t     *en_elop;
 806         boolean_t               en_licensing_supported;
 807 #endif
 808         union {
 809 #if EFSYS_OPT_SIENA
 810                 struct {
 811 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 812                         unsigned int            enu_partn_mask;
 813 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 814 #if EFSYS_OPT_VPD
 815                         caddr_t                 enu_svpd;
 816                         size_t                  enu_svpd_length;
 817 #endif  /* EFSYS_OPT_VPD */
 818                         int                     enu_unused;
 819                 } siena;
 820 #endif  /* EFSYS_OPT_SIENA */
 821                 int     enu_unused;
 822         } en_u;
 823 #if EFX_OPTS_EF10()
 824         union en_arch {
 825                 struct {
 826                         int                     ena_vi_base;
 827                         int                     ena_vi_count;
 828                         int                     ena_vi_shift;
 829 #if EFSYS_OPT_VPD
 830                         caddr_t                 ena_svpd;
 831                         size_t                  ena_svpd_length;
 832 #endif  /* EFSYS_OPT_VPD */
 833                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 834                         uint32_t                ena_piobuf_count;
 835                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 836                         uint32_t                ena_pio_write_vi_base;
 837                         /* Memory BAR mapping regions */
 838                         uint32_t                ena_uc_mem_map_offset;
 839                         size_t                  ena_uc_mem_map_size;
 840                         uint32_t                ena_wc_mem_map_offset;
 841                         size_t                  ena_wc_mem_map_size;
 842                 } ef10;
 843         } en_arch;
 844 #endif  /* EFX_OPTS_EF10() */
 845 #if EFSYS_OPT_EVB
 846         const efx_evb_ops_t     *en_eeop;
 847         struct efx_vswitch_s    *en_vswitchp;
 848 #endif  /* EFSYS_OPT_EVB */
 849 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 850         const efx_proxy_ops_t   *en_epop;
 851 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 852 };
 853
 854 #define EFX_FAMILY_IS_EF10(_enp) \
 855         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 856          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 857          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 858
 859
 860 #define EFX_NIC_MAGIC   0x02121996
 861
 862 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 863     const efx_ev_callbacks_t *, void *);
 864
 865 typedef struct efx_evq_rxq_state_s {
 866         unsigned int                    eers_rx_read_ptr;
 867         unsigned int                    eers_rx_mask;
 868 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 869         unsigned int                    eers_rx_stream_npackets;
 870         boolean_t                       eers_rx_packed_stream;
 871 #endif
 872 #if EFSYS_OPT_RX_PACKED_STREAM
 873         unsigned int                    eers_rx_packed_stream_credits;
 874 #endif
 875 } efx_evq_rxq_state_t;
 876
 877 struct efx_evq_s {
 878         uint32_t                        ee_magic;
 879         uint32_t                        ee_flags;
 880         efx_nic_t                       *ee_enp;
 881         unsigned int                    ee_index;
 882         unsigned int                    ee_mask;
 883         efsys_mem_t                     *ee_esmp;
 884 #if EFSYS_OPT_QSTATS
 885         uint32_t                        ee_stat[EV_NQSTATS];
 886 #endif  /* EFSYS_OPT_QSTATS */
 887
 888         efx_ev_handler_t                ee_rx;
 889         efx_ev_handler_t                ee_tx;
 890         efx_ev_handler_t                ee_driver;
 891         efx_ev_handler_t                ee_global;
 892         efx_ev_handler_t                ee_drv_gen;
 893 #if EFSYS_OPT_MCDI
 894         efx_ev_handler_t                ee_mcdi;
 895 #endif  /* EFSYS_OPT_MCDI */
 896
 897         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 898 };
 899
 900 #define EFX_EVQ_MAGIC   0x08081997
 901
 902 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 903
 904 #if EFSYS_OPT_QSTATS
 905 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
 906         do {                                                            \
 907                 (_eep)->ee_stat[_stat]++;                               \
 908         _NOTE(CONSTANTCONDITION)                                        \
 909         } while (B_FALSE)
 910 #else
 911 #define EFX_EV_QSTAT_INCR(_eep, _stat)
 912 #endif
 913
 914 struct efx_rxq_s {
 915         uint32_t                        er_magic;
 916         efx_nic_t                       *er_enp;
 917         efx_evq_t                       *er_eep;
 918         unsigned int                    er_index;
 919         unsigned int                    er_label;
 920         unsigned int                    er_mask;
 921         size_t                          er_buf_size;
 922         efsys_mem_t                     *er_esmp;
 923         efx_evq_rxq_state_t             *er_ev_qstate;
 924 };
 925
 926 #define EFX_RXQ_MAGIC   0x15022005
 927
 928 struct efx_txq_s {
 929         uint32_t                        et_magic;
 930         efx_nic_t                       *et_enp;
 931         unsigned int                    et_index;
 932         unsigned int                    et_mask;
 933         efsys_mem_t                     *et_esmp;
 934 #if EFSYS_OPT_HUNTINGTON
 935         uint32_t                        et_pio_bufnum;
 936         uint32_t                        et_pio_blknum;
 937         uint32_t                        et_pio_write_offset;
 938         uint32_t                        et_pio_offset;
 939         size_t                          et_pio_size;
 940 #endif
 941 #if EFSYS_OPT_QSTATS
 942         uint32_t                        et_stat[TX_NQSTATS];
 943 #endif  /* EFSYS_OPT_QSTATS */
 944 };
 945
 946 #define EFX_TXQ_MAGIC   0x05092005
 947
 948 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 949         do {                                                            \
 950                 (_dst)[0] = (_src)[0];                                  \
 951                 (_dst)[1] = (_src)[1];                                  \
 952                 (_dst)[2] = (_src)[2];                                  \
 953                 (_dst)[3] = (_src)[3];                                  \
 954                 (_dst)[4] = (_src)[4];                                  \
 955                 (_dst)[5] = (_src)[5];                                  \
 956         _NOTE(CONSTANTCONDITION)                                        \
 957         } while (B_FALSE)
 958
 959 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 960         do {                                                            \
 961                 uint16_t *_d = (uint16_t *)(_dst);                      \
 962                 _d[0] = 0xffff;                                         \
 963                 _d[1] = 0xffff;                                         \
 964                 _d[2] = 0xffff;                                         \
 965         _NOTE(CONSTANTCONDITION)                                        \
 966         } while (B_FALSE)
 967
 968 #if EFSYS_OPT_CHECK_REG
 969 #define EFX_CHECK_REG(_enp, _reg)                                       \
 970         do {                                                            \
 971                 const char *name = #_reg;                               \
 972                 char min = name[4];                                     \
 973                 char max = name[5];                                     \
 974                 char rev;                                               \
 975                                                                         \
 976                 switch ((_enp)->en_family) {                            \
 977                 case EFX_FAMILY_SIENA:                                  \
 978                         rev = 'C';                                      \
 979                         break;                                          \
 980                                                                         \
 981                 case EFX_FAMILY_HUNTINGTON:                             \
 982                         rev = 'D';                                      \
 983                         break;                                          \
 984                                                                         \
 985                 case EFX_FAMILY_MEDFORD:                                \
 986                         rev = 'E';                                      \
 987                         break;                                          \
 988                                                                         \
 989                 case EFX_FAMILY_MEDFORD2:                               \
 990                         rev = 'F';                                      \
 991                         break;                                          \
 992                                                                         \
 993                 default:                                                \
 994                         rev = '?';                                      \
 995                         break;                                          \
 996                 }                                                       \
 997                                                                         \
 998                 EFSYS_ASSERT3S(rev, >=, min);                           \
 999                 EFSYS_ASSERT3S(rev, <=, max);                           \
1000                                                                         \
1001         _NOTE(CONSTANTCONDITION)                                        \
1002         } while (B_FALSE)
1003 #else
1004 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
1005         _NOTE(CONSTANTCONDITION)                                        \
1006         } while (B_FALSE)
1007 #endif
1008
1009 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
1010         do {                                                            \
1011                 EFX_CHECK_REG((_enp), (_reg));                          \
1012                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
1013                     (_edp), (_lock));                                   \
1014                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
1015                     uint32_t, _reg ## _OFST,                            \
1016                     uint32_t, (_edp)->ed_u32[0]);                       \
1017         _NOTE(CONSTANTCONDITION)                                        \
1018         } while (B_FALSE)
1019
1020 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
1021         do {                                                            \
1022                 EFX_CHECK_REG((_enp), (_reg));                          \
1023                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
1024                     uint32_t, _reg ## _OFST,                            \
1025                     uint32_t, (_edp)->ed_u32[0]);                       \
1026                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
1027                     (_edp), (_lock));                                   \
1028         _NOTE(CONSTANTCONDITION)                                        \
1029         } while (B_FALSE)
1030
1031 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
1032         do {                                                            \
1033                 EFX_CHECK_REG((_enp), (_reg));                          \
1034                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1035                     (_eqp));                                            \
1036                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1037                     uint32_t, _reg ## _OFST,                            \
1038                     uint32_t, (_eqp)->eq_u32[1],                        \
1039                     uint32_t, (_eqp)->eq_u32[0]);                       \
1040         _NOTE(CONSTANTCONDITION)                                        \
1041         } while (B_FALSE)
1042
1043 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1044         do {                                                            \
1045                 EFX_CHECK_REG((_enp), (_reg));                          \
1046                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1047                     uint32_t, _reg ## _OFST,                            \
1048                     uint32_t, (_eqp)->eq_u32[1],                        \
1049                     uint32_t, (_eqp)->eq_u32[0]);                       \
1050                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1051                     (_eqp));                                            \
1052         _NOTE(CONSTANTCONDITION)                                        \
1053         } while (B_FALSE)
1054
1055 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1056         do {                                                            \
1057                 EFX_CHECK_REG((_enp), (_reg));                          \
1058                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1059                     (_eop), B_TRUE);                                    \
1060                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1061                     uint32_t, _reg ## _OFST,                            \
1062                     uint32_t, (_eop)->eo_u32[3],                        \
1063                     uint32_t, (_eop)->eo_u32[2],                        \
1064                     uint32_t, (_eop)->eo_u32[1],                        \
1065                     uint32_t, (_eop)->eo_u32[0]);                       \
1066         _NOTE(CONSTANTCONDITION)                                        \
1067         } while (B_FALSE)
1068
1069 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1070         do {                                                            \
1071                 EFX_CHECK_REG((_enp), (_reg));                          \
1072                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1073                     uint32_t, _reg ## _OFST,                            \
1074                     uint32_t, (_eop)->eo_u32[3],                        \
1075                     uint32_t, (_eop)->eo_u32[2],                        \
1076                     uint32_t, (_eop)->eo_u32[1],                        \
1077                     uint32_t, (_eop)->eo_u32[0]);                       \
1078                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1079                     (_eop), B_TRUE);                                    \
1080         _NOTE(CONSTANTCONDITION)                                        \
1081         } while (B_FALSE)
1082
1083 /*
1084  * Accessors for memory BAR non-VI tables.
1085  *
1086  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1087  * to ensure the correct runtime VI window size is used on Medford2.
1088  *
1089  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1090  */
1091
1092 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1093         do {                                                            \
1094                 EFX_CHECK_REG((_enp), (_reg));                          \
1095                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1096                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1097                     (_edp), (_lock));                                   \
1098                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1099                     uint32_t, (_index),                                 \
1100                     uint32_t, _reg ## _OFST,                            \
1101                     uint32_t, (_edp)->ed_u32[0]);                       \
1102         _NOTE(CONSTANTCONDITION)                                        \
1103         } while (B_FALSE)
1104
1105 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1106         do {                                                            \
1107                 EFX_CHECK_REG((_enp), (_reg));                          \
1108                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1109                     uint32_t, (_index),                                 \
1110                     uint32_t, _reg ## _OFST,                            \
1111                     uint32_t, (_edp)->ed_u32[0]);                       \
1112                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1113                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1114                     (_edp), (_lock));                                   \
1115         _NOTE(CONSTANTCONDITION)                                        \
1116         } while (B_FALSE)
1117
1118 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1119         do {                                                            \
1120                 EFX_CHECK_REG((_enp), (_reg));                          \
1121                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1122                     uint32_t, (_index),                                 \
1123                     uint32_t, _reg ## _OFST,                            \
1124                     uint32_t, (_edp)->ed_u32[0]);                       \
1125                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1126                     (_reg ## _OFST +                                    \
1127                     (3 * sizeof (efx_dword_t)) +                        \
1128                     ((_index) * _reg ## _STEP)),                        \
1129                     (_edp), (_lock));                                   \
1130         _NOTE(CONSTANTCONDITION)                                        \
1131         } while (B_FALSE)
1132
1133 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1134         do {                                                            \
1135                 EFX_CHECK_REG((_enp), (_reg));                          \
1136                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1137                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1138                     (_eqp));                                            \
1139                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1140                     uint32_t, (_index),                                 \
1141                     uint32_t, _reg ## _OFST,                            \
1142                     uint32_t, (_eqp)->eq_u32[1],                        \
1143                     uint32_t, (_eqp)->eq_u32[0]);                       \
1144         _NOTE(CONSTANTCONDITION)                                        \
1145         } while (B_FALSE)
1146
1147 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1148         do {                                                            \
1149                 EFX_CHECK_REG((_enp), (_reg));                          \
1150                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1151                     uint32_t, (_index),                                 \
1152                     uint32_t, _reg ## _OFST,                            \
1153                     uint32_t, (_eqp)->eq_u32[1],                        \
1154                     uint32_t, (_eqp)->eq_u32[0]);                       \
1155                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1156                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1157                     (_eqp));                                            \
1158         _NOTE(CONSTANTCONDITION)                                        \
1159         } while (B_FALSE)
1160
1161 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1162         do {                                                            \
1163                 EFX_CHECK_REG((_enp), (_reg));                          \
1164                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1165                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1166                     (_eop), (_lock));                                   \
1167                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1168                     uint32_t, (_index),                                 \
1169                     uint32_t, _reg ## _OFST,                            \
1170                     uint32_t, (_eop)->eo_u32[3],                        \
1171                     uint32_t, (_eop)->eo_u32[2],                        \
1172                     uint32_t, (_eop)->eo_u32[1],                        \
1173                     uint32_t, (_eop)->eo_u32[0]);                       \
1174         _NOTE(CONSTANTCONDITION)                                        \
1175         } while (B_FALSE)
1176
1177 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1178         do {                                                            \
1179                 EFX_CHECK_REG((_enp), (_reg));                          \
1180                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1181                     uint32_t, (_index),                                 \
1182                     uint32_t, _reg ## _OFST,                            \
1183                     uint32_t, (_eop)->eo_u32[3],                        \
1184                     uint32_t, (_eop)->eo_u32[2],                        \
1185                     uint32_t, (_eop)->eo_u32[1],                        \
1186                     uint32_t, (_eop)->eo_u32[0]);                       \
1187                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1188                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1189                     (_eop), (_lock));                                   \
1190         _NOTE(CONSTANTCONDITION)                                        \
1191         } while (B_FALSE)
1192
1193 /*
1194  * Accessors for memory BAR per-VI registers.
1195  *
1196  * The VI window size is 8KB for Medford and all earlier controllers.
1197  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1198  */
1199
1200 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1201         do {                                                            \
1202                 EFX_CHECK_REG((_enp), (_reg));                          \
1203                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1204                     ((_reg ## _OFST) +                                  \
1205                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1206                     (_edp), (_lock));                                   \
1207                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1208                     uint32_t, (_index),                                 \
1209                     uint32_t, _reg ## _OFST,                            \
1210                     uint32_t, (_edp)->ed_u32[0]);                       \
1211         _NOTE(CONSTANTCONDITION)                                        \
1212         } while (B_FALSE)
1213
1214 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1215         do {                                                            \
1216                 EFX_CHECK_REG((_enp), (_reg));                          \
1217                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1218                     uint32_t, (_index),                                 \
1219                     uint32_t, _reg ## _OFST,                            \
1220                     uint32_t, (_edp)->ed_u32[0]);                       \
1221                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1222                     ((_reg ## _OFST) +                                  \
1223                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1224                     (_edp), (_lock));                                   \
1225         _NOTE(CONSTANTCONDITION)                                        \
1226         } while (B_FALSE)
1227
1228 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1229         do {                                                            \
1230                 EFX_CHECK_REG((_enp), (_reg));                          \
1231                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1232                     uint32_t, (_index),                                 \
1233                     uint32_t, _reg ## _OFST,                            \
1234                     uint32_t, (_edp)->ed_u32[0]);                       \
1235                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1236                     ((_reg ## _OFST) +                                  \
1237                     (2 * sizeof (efx_dword_t)) +                        \
1238                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1239                     (_edp), (_lock));                                   \
1240         _NOTE(CONSTANTCONDITION)                                        \
1241         } while (B_FALSE)
1242
1243 /*
1244  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1245  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1246  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1247  * the need for locking in the host, and are the only ones known to be safe to
1248  * use 128-bites write with.
1249  */
1250 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1251         do {                                                            \
1252                 EFX_CHECK_REG((_enp), (_reg));                          \
1253                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1254                     const char *, #_reg,                                \
1255                     uint32_t, (_index),                                 \
1256                     uint32_t, _reg ## _OFST,                            \
1257                     uint32_t, (_eop)->eo_u32[3],                        \
1258                     uint32_t, (_eop)->eo_u32[2],                        \
1259                     uint32_t, (_eop)->eo_u32[1],                        \
1260                     uint32_t, (_eop)->eo_u32[0]);                       \
1261                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1262                     (_reg ## _OFST +                                    \
1263                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1264                     (_eop));                                            \
1265         _NOTE(CONSTANTCONDITION)                                        \
1266         } while (B_FALSE)
1267
1268 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1269         do {                                                            \
1270                 unsigned int _new = (_wptr);                            \
1271                 unsigned int _old = (_owptr);                           \
1272                                                                         \
1273                 if ((_new) >= (_old))                                   \
1274                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1275                             (_old) * sizeof (efx_desc_t),               \
1276                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1277                 else                                                    \
1278                         /*                                              \
1279                          * It is cheaper to sync entire map than sync   \
1280                          * two parts especially when offset/size are    \
1281                          * ignored and entire map is synced in any case.\
1282                          */                                             \
1283                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1284                             0,                                          \
1285                             (_entries) * sizeof (efx_desc_t));          \
1286         _NOTE(CONSTANTCONDITION)                                        \
1287         } while (B_FALSE)
1288
1289 extern  __checkReturn   efx_rc_t
1290 efx_mac_select(
1291         __in            efx_nic_t *enp);
1292
1293 extern  void
1294 efx_mac_multicast_hash_compute(
1295         __in_ecount(6*count)            uint8_t const *addrs,
1296         __in                            int count,
1297         __out                           efx_oword_t *hash_low,
1298         __out                           efx_oword_t *hash_high);
1299
1300 extern  __checkReturn   efx_rc_t
1301 efx_phy_probe(
1302         __in            efx_nic_t *enp);
1303
1304 extern                  void
1305 efx_phy_unprobe(
1306         __in            efx_nic_t *enp);
1307
1308 #if EFSYS_OPT_VPD
1309
1310 /* VPD utility functions */
1311
1312 extern  __checkReturn           efx_rc_t
1313 efx_vpd_hunk_length(
1314         __in_bcount(size)       caddr_t data,
1315         __in                    size_t size,
1316         __out                   size_t *lengthp);
1317
1318 extern  __checkReturn           efx_rc_t
1319 efx_vpd_hunk_verify(
1320         __in_bcount(size)       caddr_t data,
1321         __in                    size_t size,
1322         __out_opt               boolean_t *cksummedp);
1323
1324 extern  __checkReturn           efx_rc_t
1325 efx_vpd_hunk_reinit(
1326         __in_bcount(size)       caddr_t data,
1327         __in                    size_t size,
1328         __in                    boolean_t wantpid);
1329
1330 extern  __checkReturn           efx_rc_t
1331 efx_vpd_hunk_get(
1332         __in_bcount(size)       caddr_t data,
1333         __in                    size_t size,
1334         __in                    efx_vpd_tag_t tag,
1335         __in                    efx_vpd_keyword_t keyword,
1336         __out                   unsigned int *payloadp,
1337         __out                   uint8_t *paylenp);
1338
1339 extern  __checkReturn                   efx_rc_t
1340 efx_vpd_hunk_next(
1341         __in_bcount(size)               caddr_t data,
1342         __in                            size_t size,
1343         __out                           efx_vpd_tag_t *tagp,
1344         __out                           efx_vpd_keyword_t *keyword,
1345         __out_opt                       unsigned int *payloadp,
1346         __out_opt                       uint8_t *paylenp,
1347         __inout                         unsigned int *contp);
1348
1349 extern  __checkReturn           efx_rc_t
1350 efx_vpd_hunk_set(
1351         __in_bcount(size)       caddr_t data,
1352         __in                    size_t size,
1353         __in                    efx_vpd_value_t *evvp);
1354
1355 #endif  /* EFSYS_OPT_VPD */
1356
1357 #if EFSYS_OPT_MCDI
1358
1359 extern  __checkReturn           efx_rc_t
1360 efx_mcdi_set_workaround(
1361         __in                    efx_nic_t *enp,
1362         __in                    uint32_t type,
1363         __in                    boolean_t enabled,
1364         __out_opt               uint32_t *flagsp);
1365
1366 extern  __checkReturn           efx_rc_t
1367 efx_mcdi_get_workarounds(
1368         __in                    efx_nic_t *enp,
1369         __out_opt               uint32_t *implementedp,
1370         __out_opt               uint32_t *enabledp);
1371
1372 #endif /* EFSYS_OPT_MCDI */
1373
1374 #if EFSYS_OPT_MAC_STATS
1375
1376 /*
1377  * Closed range of stats (i.e. the first and the last are included).
1378  * The last must be greater or equal (if the range is one item only) to
1379  * the first.
1380  */
1381 struct efx_mac_stats_range {
1382         efx_mac_stat_t          first;
1383         efx_mac_stat_t          last;
1384 };
1385
1386 typedef enum efx_stats_action_e {
1387         EFX_STATS_CLEAR,
1388         EFX_STATS_UPLOAD,
1389         EFX_STATS_ENABLE_NOEVENTS,
1390         EFX_STATS_ENABLE_EVENTS,
1391         EFX_STATS_DISABLE,
1392 } efx_stats_action_t;
1393
1394 extern                                  efx_rc_t
1395 efx_mac_stats_mask_add_ranges(
1396         __inout_bcount(mask_size)       uint32_t *maskp,
1397         __in                            size_t mask_size,
1398         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1399         __in                            unsigned int rng_count);
1400
1401 extern  __checkReturn   efx_rc_t
1402 efx_mcdi_mac_stats(
1403         __in            efx_nic_t *enp,
1404         __in            uint32_t vport_id,
1405         __in_opt        efsys_mem_t *esmp,
1406         __in            efx_stats_action_t action,
1407         __in            uint16_t period_ms);
1408
1409 #endif  /* EFSYS_OPT_MAC_STATS */
1410
1411 #ifdef  __cplusplus
1412 }
1413 #endif
1414
1415 #endif  /* _SYS_EFX_IMPL_H */