2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
48 #define EFX_MOD_MCDI 0x00000001
49 #define EFX_MOD_PROBE 0x00000002
50 #define EFX_MOD_NVRAM 0x00000004
51 #define EFX_MOD_VPD 0x00000008
52 #define EFX_MOD_NIC 0x00000010
53 #define EFX_MOD_INTR 0x00000020
54 #define EFX_MOD_EV 0x00000040
55 #define EFX_MOD_RX 0x00000080
56 #define EFX_MOD_TX 0x00000100
57 #define EFX_MOD_PORT 0x00000200
58 #define EFX_MOD_MON 0x00000400
59 #define EFX_MOD_FILTER 0x00001000
60 #define EFX_MOD_LIC 0x00002000
62 #define EFX_RESET_PHY 0x00000001
63 #define EFX_RESET_RXQ_ERR 0x00000002
64 #define EFX_RESET_TXQ_ERR 0x00000004
66 typedef enum efx_mac_type_e {
74 typedef struct efx_ev_ops_s {
75 efx_rc_t (*eevo_init)(efx_nic_t *);
76 void (*eevo_fini)(efx_nic_t *);
77 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
78 efsys_mem_t *, size_t, uint32_t,
79 uint32_t, uint32_t, efx_evq_t *);
80 void (*eevo_qdestroy)(efx_evq_t *);
81 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
82 void (*eevo_qpost)(efx_evq_t *, uint16_t);
83 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
86 typedef struct efx_tx_ops_s {
87 efx_rc_t (*etxo_init)(efx_nic_t *);
88 void (*etxo_fini)(efx_nic_t *);
89 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
90 unsigned int, unsigned int,
91 efsys_mem_t *, size_t,
93 efx_evq_t *, efx_txq_t *,
95 void (*etxo_qdestroy)(efx_txq_t *);
96 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
97 unsigned int, unsigned int,
99 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
100 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
101 efx_rc_t (*etxo_qflush)(efx_txq_t *);
102 void (*etxo_qenable)(efx_txq_t *);
103 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
104 void (*etxo_qpio_disable)(efx_txq_t *);
105 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
107 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
109 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
110 unsigned int, unsigned int,
112 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
115 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
118 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
121 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
125 typedef struct efx_rx_ops_s {
126 efx_rc_t (*erxo_init)(efx_nic_t *);
127 void (*erxo_fini)(efx_nic_t *);
128 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
130 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
131 unsigned int, unsigned int,
133 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
134 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
135 void (*erxo_qenable)(efx_rxq_t *);
136 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
137 unsigned int, efx_rxq_type_t,
138 efsys_mem_t *, size_t, uint32_t,
139 efx_evq_t *, efx_rxq_t *);
140 void (*erxo_qdestroy)(efx_rxq_t *);
143 typedef struct efx_mac_ops_s {
144 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
145 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
146 efx_rc_t (*emo_addr_set)(efx_nic_t *);
147 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
148 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
149 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
150 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
151 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
152 efx_rxq_t *, boolean_t);
153 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
156 typedef struct efx_phy_ops_s {
157 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
158 efx_rc_t (*epo_reset)(efx_nic_t *);
159 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
160 efx_rc_t (*epo_verify)(efx_nic_t *);
161 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
165 typedef struct efx_filter_ops_s {
166 efx_rc_t (*efo_init)(efx_nic_t *);
167 void (*efo_fini)(efx_nic_t *);
168 efx_rc_t (*efo_restore)(efx_nic_t *);
169 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
170 boolean_t may_replace);
171 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
172 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
173 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
174 boolean_t, boolean_t, boolean_t,
175 uint8_t const *, uint32_t);
178 extern __checkReturn efx_rc_t
179 efx_filter_reconfigure(
181 __in_ecount(6) uint8_t const *mac_addr,
182 __in boolean_t all_unicst,
183 __in boolean_t mulcst,
184 __in boolean_t all_mulcst,
185 __in boolean_t brdcst,
186 __in_ecount(6*count) uint8_t const *addrs,
187 __in uint32_t count);
189 #endif /* EFSYS_OPT_FILTER */
192 typedef struct efx_port_s {
193 efx_mac_type_t ep_mac_type;
194 uint32_t ep_phy_type;
197 uint8_t ep_mac_addr[6];
198 efx_link_mode_t ep_link_mode;
199 boolean_t ep_all_unicst;
201 boolean_t ep_all_mulcst;
203 unsigned int ep_fcntl;
204 boolean_t ep_fcntl_autoneg;
205 efx_oword_t ep_multicst_hash[2];
206 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
207 EFX_MAC_MULTICAST_LIST_MAX];
208 uint32_t ep_mulcst_addr_count;
209 efx_phy_media_type_t ep_fixed_port_type;
210 efx_phy_media_type_t ep_module_type;
211 uint32_t ep_adv_cap_mask;
212 uint32_t ep_lp_cap_mask;
213 uint32_t ep_default_adv_cap_mask;
214 uint32_t ep_phy_cap_mask;
215 boolean_t ep_mac_drain;
216 boolean_t ep_mac_stats_pending;
217 const efx_mac_ops_t *ep_emop;
218 const efx_phy_ops_t *ep_epop;
221 typedef struct efx_mon_ops_s {
224 typedef struct efx_mon_s {
225 efx_mon_type_t em_type;
226 const efx_mon_ops_t *em_emop;
229 typedef struct efx_intr_ops_s {
230 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
231 void (*eio_enable)(efx_nic_t *);
232 void (*eio_disable)(efx_nic_t *);
233 void (*eio_disable_unlocked)(efx_nic_t *);
234 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
235 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
236 void (*eio_status_message)(efx_nic_t *, unsigned int,
238 void (*eio_fatal)(efx_nic_t *);
239 void (*eio_fini)(efx_nic_t *);
242 typedef struct efx_intr_s {
243 const efx_intr_ops_t *ei_eiop;
244 efsys_mem_t *ei_esmp;
245 efx_intr_type_t ei_type;
246 unsigned int ei_level;
249 typedef struct efx_nic_ops_s {
250 efx_rc_t (*eno_probe)(efx_nic_t *);
251 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
252 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
253 efx_rc_t (*eno_reset)(efx_nic_t *);
254 efx_rc_t (*eno_init)(efx_nic_t *);
255 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
256 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
257 uint32_t *, size_t *);
258 void (*eno_fini)(efx_nic_t *);
259 void (*eno_unprobe)(efx_nic_t *);
262 #ifndef EFX_TXQ_LIMIT_TARGET
263 #define EFX_TXQ_LIMIT_TARGET 259
265 #ifndef EFX_RXQ_LIMIT_TARGET
266 #define EFX_RXQ_LIMIT_TARGET 512
268 #ifndef EFX_TXQ_DC_SIZE
269 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
271 #ifndef EFX_RXQ_DC_SIZE
272 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
277 typedef struct efx_filter_s {
280 #endif /* EFSYS_OPT_FILTER */
284 typedef struct efx_mcdi_ops_s {
285 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
286 void (*emco_send_request)(efx_nic_t *, void *, size_t,
288 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
289 boolean_t (*emco_poll_response)(efx_nic_t *);
290 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
291 void (*emco_fini)(efx_nic_t *);
292 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
293 efx_mcdi_feature_id_t, boolean_t *);
294 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
298 typedef struct efx_mcdi_s {
299 const efx_mcdi_ops_t *em_emcop;
300 const efx_mcdi_transport_t *em_emtp;
301 efx_mcdi_iface_t em_emip;
304 #endif /* EFSYS_OPT_MCDI */
306 typedef struct efx_drv_cfg_s {
307 uint32_t edc_min_vi_count;
308 uint32_t edc_max_vi_count;
310 uint32_t edc_max_piobuf_count;
311 uint32_t edc_pio_alloc_size;
316 efx_family_t en_family;
317 uint32_t en_features;
318 efsys_identifier_t *en_esip;
319 efsys_lock_t *en_eslp;
320 efsys_bar_t *en_esbp;
321 unsigned int en_mod_flags;
322 unsigned int en_reset_flags;
323 efx_nic_cfg_t en_nic_cfg;
324 efx_drv_cfg_t en_drv_cfg;
328 uint32_t en_ev_qcount;
329 uint32_t en_rx_qcount;
330 uint32_t en_tx_qcount;
331 const efx_nic_ops_t *en_enop;
332 const efx_ev_ops_t *en_eevop;
333 const efx_tx_ops_t *en_etxop;
334 const efx_rx_ops_t *en_erxop;
336 efx_filter_t en_filter;
337 const efx_filter_ops_t *en_efop;
338 #endif /* EFSYS_OPT_FILTER */
341 #endif /* EFSYS_OPT_MCDI */
342 uint32_t en_vport_id;
349 #define EFX_NIC_MAGIC 0x02121996
351 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
352 const efx_ev_callbacks_t *, void *);
354 typedef struct efx_evq_rxq_state_s {
355 unsigned int eers_rx_read_ptr;
356 unsigned int eers_rx_mask;
357 } efx_evq_rxq_state_t;
362 unsigned int ee_index;
363 unsigned int ee_mask;
364 efsys_mem_t *ee_esmp;
366 efx_ev_handler_t ee_rx;
367 efx_ev_handler_t ee_tx;
368 efx_ev_handler_t ee_driver;
369 efx_ev_handler_t ee_global;
370 efx_ev_handler_t ee_drv_gen;
372 efx_ev_handler_t ee_mcdi;
373 #endif /* EFSYS_OPT_MCDI */
375 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
380 #define EFX_EVQ_MAGIC 0x08081997
382 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
388 unsigned int er_index;
389 unsigned int er_label;
390 unsigned int er_mask;
391 efsys_mem_t *er_esmp;
394 #define EFX_RXQ_MAGIC 0x15022005
399 unsigned int et_index;
400 unsigned int et_mask;
401 efsys_mem_t *et_esmp;
404 #define EFX_TXQ_MAGIC 0x05092005
406 #define EFX_MAC_ADDR_COPY(_dst, _src) \
408 (_dst)[0] = (_src)[0]; \
409 (_dst)[1] = (_src)[1]; \
410 (_dst)[2] = (_src)[2]; \
411 (_dst)[3] = (_src)[3]; \
412 (_dst)[4] = (_src)[4]; \
413 (_dst)[5] = (_src)[5]; \
414 _NOTE(CONSTANTCONDITION) \
417 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
419 uint16_t *_d = (uint16_t *)(_dst); \
423 _NOTE(CONSTANTCONDITION) \
426 #if EFSYS_OPT_CHECK_REG
427 #define EFX_CHECK_REG(_enp, _reg) \
429 const char *name = #_reg; \
430 char min = name[4]; \
431 char max = name[5]; \
434 switch ((_enp)->en_family) { \
435 case EFX_FAMILY_SIENA: \
439 case EFX_FAMILY_HUNTINGTON: \
443 case EFX_FAMILY_MEDFORD: \
452 EFSYS_ASSERT3S(rev, >=, min); \
453 EFSYS_ASSERT3S(rev, <=, max); \
455 _NOTE(CONSTANTCONDITION) \
458 #define EFX_CHECK_REG(_enp, _reg) do { \
459 _NOTE(CONSTANTCONDITION) \
463 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
465 EFX_CHECK_REG((_enp), (_reg)); \
466 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
468 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
469 uint32_t, _reg ## _OFST, \
470 uint32_t, (_edp)->ed_u32[0]); \
471 _NOTE(CONSTANTCONDITION) \
474 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
476 EFX_CHECK_REG((_enp), (_reg)); \
477 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
478 uint32_t, _reg ## _OFST, \
479 uint32_t, (_edp)->ed_u32[0]); \
480 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
482 _NOTE(CONSTANTCONDITION) \
485 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
487 EFX_CHECK_REG((_enp), (_reg)); \
488 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
490 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
491 uint32_t, _reg ## _OFST, \
492 uint32_t, (_eqp)->eq_u32[1], \
493 uint32_t, (_eqp)->eq_u32[0]); \
494 _NOTE(CONSTANTCONDITION) \
497 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
499 EFX_CHECK_REG((_enp), (_reg)); \
500 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
501 uint32_t, _reg ## _OFST, \
502 uint32_t, (_eqp)->eq_u32[1], \
503 uint32_t, (_eqp)->eq_u32[0]); \
504 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
506 _NOTE(CONSTANTCONDITION) \
509 #define EFX_BAR_READO(_enp, _reg, _eop) \
511 EFX_CHECK_REG((_enp), (_reg)); \
512 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
514 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
515 uint32_t, _reg ## _OFST, \
516 uint32_t, (_eop)->eo_u32[3], \
517 uint32_t, (_eop)->eo_u32[2], \
518 uint32_t, (_eop)->eo_u32[1], \
519 uint32_t, (_eop)->eo_u32[0]); \
520 _NOTE(CONSTANTCONDITION) \
523 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
525 EFX_CHECK_REG((_enp), (_reg)); \
526 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
527 uint32_t, _reg ## _OFST, \
528 uint32_t, (_eop)->eo_u32[3], \
529 uint32_t, (_eop)->eo_u32[2], \
530 uint32_t, (_eop)->eo_u32[1], \
531 uint32_t, (_eop)->eo_u32[0]); \
532 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
534 _NOTE(CONSTANTCONDITION) \
537 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
539 EFX_CHECK_REG((_enp), (_reg)); \
540 EFSYS_BAR_READD((_enp)->en_esbp, \
541 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
543 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
544 uint32_t, (_index), \
545 uint32_t, _reg ## _OFST, \
546 uint32_t, (_edp)->ed_u32[0]); \
547 _NOTE(CONSTANTCONDITION) \
550 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
552 EFX_CHECK_REG((_enp), (_reg)); \
553 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
554 uint32_t, (_index), \
555 uint32_t, _reg ## _OFST, \
556 uint32_t, (_edp)->ed_u32[0]); \
557 EFSYS_BAR_WRITED((_enp)->en_esbp, \
558 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
560 _NOTE(CONSTANTCONDITION) \
563 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
565 EFX_CHECK_REG((_enp), (_reg)); \
566 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
567 uint32_t, (_index), \
568 uint32_t, _reg ## _OFST, \
569 uint32_t, (_edp)->ed_u32[0]); \
570 EFSYS_BAR_WRITED((_enp)->en_esbp, \
572 (2 * sizeof (efx_dword_t)) + \
573 ((_index) * _reg ## _STEP)), \
575 _NOTE(CONSTANTCONDITION) \
578 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
580 EFX_CHECK_REG((_enp), (_reg)); \
581 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
582 uint32_t, (_index), \
583 uint32_t, _reg ## _OFST, \
584 uint32_t, (_edp)->ed_u32[0]); \
585 EFSYS_BAR_WRITED((_enp)->en_esbp, \
587 (3 * sizeof (efx_dword_t)) + \
588 ((_index) * _reg ## _STEP)), \
590 _NOTE(CONSTANTCONDITION) \
593 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
595 EFX_CHECK_REG((_enp), (_reg)); \
596 EFSYS_BAR_READQ((_enp)->en_esbp, \
597 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
599 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
600 uint32_t, (_index), \
601 uint32_t, _reg ## _OFST, \
602 uint32_t, (_eqp)->eq_u32[1], \
603 uint32_t, (_eqp)->eq_u32[0]); \
604 _NOTE(CONSTANTCONDITION) \
607 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
609 EFX_CHECK_REG((_enp), (_reg)); \
610 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
611 uint32_t, (_index), \
612 uint32_t, _reg ## _OFST, \
613 uint32_t, (_eqp)->eq_u32[1], \
614 uint32_t, (_eqp)->eq_u32[0]); \
615 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
616 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
618 _NOTE(CONSTANTCONDITION) \
621 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
623 EFX_CHECK_REG((_enp), (_reg)); \
624 EFSYS_BAR_READO((_enp)->en_esbp, \
625 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
627 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
628 uint32_t, (_index), \
629 uint32_t, _reg ## _OFST, \
630 uint32_t, (_eop)->eo_u32[3], \
631 uint32_t, (_eop)->eo_u32[2], \
632 uint32_t, (_eop)->eo_u32[1], \
633 uint32_t, (_eop)->eo_u32[0]); \
634 _NOTE(CONSTANTCONDITION) \
637 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
639 EFX_CHECK_REG((_enp), (_reg)); \
640 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
641 uint32_t, (_index), \
642 uint32_t, _reg ## _OFST, \
643 uint32_t, (_eop)->eo_u32[3], \
644 uint32_t, (_eop)->eo_u32[2], \
645 uint32_t, (_eop)->eo_u32[1], \
646 uint32_t, (_eop)->eo_u32[0]); \
647 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
648 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
650 _NOTE(CONSTANTCONDITION) \
654 * Allow drivers to perform optimised 128-bit doorbell writes.
655 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
656 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
657 * the need for locking in the host, and are the only ones known to be safe to
658 * use 128-bites write with.
660 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
662 EFX_CHECK_REG((_enp), (_reg)); \
663 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
666 uint32_t, (_index), \
667 uint32_t, _reg ## _OFST, \
668 uint32_t, (_eop)->eo_u32[3], \
669 uint32_t, (_eop)->eo_u32[2], \
670 uint32_t, (_eop)->eo_u32[1], \
671 uint32_t, (_eop)->eo_u32[0]); \
672 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
673 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
675 _NOTE(CONSTANTCONDITION) \
678 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
680 unsigned int _new = (_wptr); \
681 unsigned int _old = (_owptr); \
683 if ((_new) >= (_old)) \
684 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
685 (_old) * sizeof (efx_desc_t), \
686 ((_new) - (_old)) * sizeof (efx_desc_t)); \
689 * It is cheaper to sync entire map than sync \
690 * two parts especially when offset/size are \
691 * ignored and entire map is synced in any case.\
693 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
695 (_entries) * sizeof (efx_desc_t)); \
696 _NOTE(CONSTANTCONDITION) \
699 extern __checkReturn efx_rc_t
701 __in efx_nic_t *enp);
703 extern __checkReturn efx_rc_t
705 __in efx_nic_t *enp);
708 efx_mac_multicast_hash_compute(
709 __in_ecount(6*count) uint8_t const *addrs,
711 __out efx_oword_t *hash_low,
712 __out efx_oword_t *hash_high);
714 extern __checkReturn efx_rc_t
716 __in efx_nic_t *enp);
720 __in efx_nic_t *enp);
724 extern __checkReturn efx_rc_t
725 efx_mcdi_set_workaround(
728 __in boolean_t enabled,
729 __out_opt uint32_t *flagsp);
731 extern __checkReturn efx_rc_t
732 efx_mcdi_get_workarounds(
734 __out_opt uint32_t *implementedp,
735 __out_opt uint32_t *enabledp);
737 #endif /* EFSYS_OPT_MCDI */
743 #endif /* _SYS_EFX_IMPL_H */