2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_FILTER 0x00001000
76 #define EFX_MOD_LIC 0x00002000
78 #define EFX_RESET_PHY 0x00000001
79 #define EFX_RESET_RXQ_ERR 0x00000002
80 #define EFX_RESET_TXQ_ERR 0x00000004
82 typedef enum efx_mac_type_e {
90 typedef struct efx_ev_ops_s {
91 efx_rc_t (*eevo_init)(efx_nic_t *);
92 void (*eevo_fini)(efx_nic_t *);
93 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
94 efsys_mem_t *, size_t, uint32_t,
95 uint32_t, uint32_t, efx_evq_t *);
96 void (*eevo_qdestroy)(efx_evq_t *);
97 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
98 void (*eevo_qpost)(efx_evq_t *, uint16_t);
99 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
101 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
105 typedef struct efx_tx_ops_s {
106 efx_rc_t (*etxo_init)(efx_nic_t *);
107 void (*etxo_fini)(efx_nic_t *);
108 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
109 unsigned int, unsigned int,
110 efsys_mem_t *, size_t,
112 efx_evq_t *, efx_txq_t *,
114 void (*etxo_qdestroy)(efx_txq_t *);
115 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
116 unsigned int, unsigned int,
118 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
119 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
120 efx_rc_t (*etxo_qflush)(efx_txq_t *);
121 void (*etxo_qenable)(efx_txq_t *);
122 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
123 void (*etxo_qpio_disable)(efx_txq_t *);
124 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
126 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
128 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
129 unsigned int, unsigned int,
131 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143 void (*etxo_qstats_update)(efx_txq_t *,
148 typedef struct efx_rx_ops_s {
149 efx_rc_t (*erxo_init)(efx_nic_t *);
150 void (*erxo_fini)(efx_nic_t *);
151 #if EFSYS_OPT_RX_SCATTER
152 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
154 #if EFSYS_OPT_RX_SCALE
155 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
156 efx_rx_scale_context_type_t,
157 uint32_t, uint32_t *);
158 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
159 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
160 efx_rx_hash_type_t, boolean_t);
161 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
162 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
164 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
166 #endif /* EFSYS_OPT_RX_SCALE */
167 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
169 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
170 unsigned int, unsigned int,
172 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
173 #if EFSYS_OPT_RX_PACKED_STREAM
174 void (*erxo_qps_update_credits)(efx_rxq_t *);
175 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
177 uint16_t *, uint32_t *, uint32_t *);
179 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
180 void (*erxo_qenable)(efx_rxq_t *);
181 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
182 unsigned int, efx_rxq_type_t,
183 efsys_mem_t *, size_t, uint32_t,
184 efx_evq_t *, efx_rxq_t *);
185 void (*erxo_qdestroy)(efx_rxq_t *);
188 typedef struct efx_mac_ops_s {
189 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
190 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
191 efx_rc_t (*emo_addr_set)(efx_nic_t *);
192 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
193 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
194 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
195 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
196 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
197 efx_rxq_t *, boolean_t);
198 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
199 #if EFSYS_OPT_LOOPBACK
200 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
201 efx_loopback_type_t);
202 #endif /* EFSYS_OPT_LOOPBACK */
203 #if EFSYS_OPT_MAC_STATS
204 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
205 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
206 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
207 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
208 uint16_t, boolean_t);
209 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
210 efsys_stat_t *, uint32_t *);
211 #endif /* EFSYS_OPT_MAC_STATS */
214 typedef struct efx_phy_ops_s {
215 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
216 efx_rc_t (*epo_reset)(efx_nic_t *);
217 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
218 efx_rc_t (*epo_verify)(efx_nic_t *);
219 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
220 #if EFSYS_OPT_PHY_STATS
221 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
223 #endif /* EFSYS_OPT_PHY_STATS */
225 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
226 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
227 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
228 efx_bist_result_t *, uint32_t *,
229 unsigned long *, size_t);
230 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
231 #endif /* EFSYS_OPT_BIST */
235 typedef struct efx_filter_ops_s {
236 efx_rc_t (*efo_init)(efx_nic_t *);
237 void (*efo_fini)(efx_nic_t *);
238 efx_rc_t (*efo_restore)(efx_nic_t *);
239 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
240 boolean_t may_replace);
241 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
242 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
244 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
245 boolean_t, boolean_t, boolean_t,
246 uint8_t const *, uint32_t);
249 extern __checkReturn efx_rc_t
250 efx_filter_reconfigure(
252 __in_ecount(6) uint8_t const *mac_addr,
253 __in boolean_t all_unicst,
254 __in boolean_t mulcst,
255 __in boolean_t all_mulcst,
256 __in boolean_t brdcst,
257 __in_ecount(6*count) uint8_t const *addrs,
258 __in uint32_t count);
260 #endif /* EFSYS_OPT_FILTER */
263 typedef struct efx_port_s {
264 efx_mac_type_t ep_mac_type;
265 uint32_t ep_phy_type;
268 uint8_t ep_mac_addr[6];
269 efx_link_mode_t ep_link_mode;
270 boolean_t ep_all_unicst;
272 boolean_t ep_all_mulcst;
274 unsigned int ep_fcntl;
275 boolean_t ep_fcntl_autoneg;
276 efx_oword_t ep_multicst_hash[2];
277 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
278 EFX_MAC_MULTICAST_LIST_MAX];
279 uint32_t ep_mulcst_addr_count;
280 #if EFSYS_OPT_LOOPBACK
281 efx_loopback_type_t ep_loopback_type;
282 efx_link_mode_t ep_loopback_link_mode;
283 #endif /* EFSYS_OPT_LOOPBACK */
284 #if EFSYS_OPT_PHY_FLAGS
285 uint32_t ep_phy_flags;
286 #endif /* EFSYS_OPT_PHY_FLAGS */
287 #if EFSYS_OPT_PHY_LED_CONTROL
288 efx_phy_led_mode_t ep_phy_led_mode;
289 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
290 efx_phy_media_type_t ep_fixed_port_type;
291 efx_phy_media_type_t ep_module_type;
292 uint32_t ep_adv_cap_mask;
293 uint32_t ep_lp_cap_mask;
294 uint32_t ep_default_adv_cap_mask;
295 uint32_t ep_phy_cap_mask;
296 boolean_t ep_mac_drain;
297 boolean_t ep_mac_stats_pending;
299 efx_bist_type_t ep_current_bist;
301 const efx_mac_ops_t *ep_emop;
302 const efx_phy_ops_t *ep_epop;
305 typedef struct efx_mon_ops_s {
306 #if EFSYS_OPT_MON_STATS
307 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
308 efx_mon_stat_value_t *);
309 #endif /* EFSYS_OPT_MON_STATS */
312 typedef struct efx_mon_s {
313 efx_mon_type_t em_type;
314 const efx_mon_ops_t *em_emop;
317 typedef struct efx_intr_ops_s {
318 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
319 void (*eio_enable)(efx_nic_t *);
320 void (*eio_disable)(efx_nic_t *);
321 void (*eio_disable_unlocked)(efx_nic_t *);
322 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
323 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
324 void (*eio_status_message)(efx_nic_t *, unsigned int,
326 void (*eio_fatal)(efx_nic_t *);
327 void (*eio_fini)(efx_nic_t *);
330 typedef struct efx_intr_s {
331 const efx_intr_ops_t *ei_eiop;
332 efsys_mem_t *ei_esmp;
333 efx_intr_type_t ei_type;
334 unsigned int ei_level;
337 typedef struct efx_nic_ops_s {
338 efx_rc_t (*eno_probe)(efx_nic_t *);
339 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
340 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
341 efx_rc_t (*eno_reset)(efx_nic_t *);
342 efx_rc_t (*eno_init)(efx_nic_t *);
343 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
344 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
345 uint32_t *, size_t *);
347 efx_rc_t (*eno_register_test)(efx_nic_t *);
348 #endif /* EFSYS_OPT_DIAG */
349 void (*eno_fini)(efx_nic_t *);
350 void (*eno_unprobe)(efx_nic_t *);
353 #ifndef EFX_TXQ_LIMIT_TARGET
354 #define EFX_TXQ_LIMIT_TARGET 259
356 #ifndef EFX_RXQ_LIMIT_TARGET
357 #define EFX_RXQ_LIMIT_TARGET 512
359 #ifndef EFX_TXQ_DC_SIZE
360 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
362 #ifndef EFX_RXQ_DC_SIZE
363 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
370 typedef struct siena_filter_spec_s {
373 uint32_t sfs_dmaq_id;
374 uint32_t sfs_dword[3];
375 } siena_filter_spec_t;
377 typedef enum siena_filter_type_e {
378 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
379 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
380 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
381 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
382 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
383 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
385 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
386 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
387 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
388 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
389 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
390 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
392 EFX_SIENA_FILTER_NTYPES
393 } siena_filter_type_t;
395 typedef enum siena_filter_tbl_id_e {
396 EFX_SIENA_FILTER_TBL_RX_IP = 0,
397 EFX_SIENA_FILTER_TBL_RX_MAC,
398 EFX_SIENA_FILTER_TBL_TX_IP,
399 EFX_SIENA_FILTER_TBL_TX_MAC,
400 EFX_SIENA_FILTER_NTBLS
401 } siena_filter_tbl_id_t;
403 typedef struct siena_filter_tbl_s {
404 int sft_size; /* number of entries */
405 int sft_used; /* active count */
406 uint32_t *sft_bitmap; /* active bitmap */
407 siena_filter_spec_t *sft_spec; /* array of saved specs */
408 } siena_filter_tbl_t;
410 typedef struct siena_filter_s {
411 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
412 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
415 #endif /* EFSYS_OPT_SIENA */
417 typedef struct efx_filter_s {
419 siena_filter_t *ef_siena_filter;
420 #endif /* EFSYS_OPT_SIENA */
421 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
422 ef10_filter_table_t *ef_ef10_filter_table;
423 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
429 siena_filter_tbl_clear(
431 __in siena_filter_tbl_id_t tbl);
433 #endif /* EFSYS_OPT_SIENA */
435 #endif /* EFSYS_OPT_FILTER */
439 typedef struct efx_mcdi_ops_s {
440 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
441 void (*emco_send_request)(efx_nic_t *, void *, size_t,
443 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
444 boolean_t (*emco_poll_response)(efx_nic_t *);
445 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
446 void (*emco_fini)(efx_nic_t *);
447 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
448 efx_mcdi_feature_id_t, boolean_t *);
449 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
453 typedef struct efx_mcdi_s {
454 const efx_mcdi_ops_t *em_emcop;
455 const efx_mcdi_transport_t *em_emtp;
456 efx_mcdi_iface_t em_emip;
459 #endif /* EFSYS_OPT_MCDI */
462 typedef struct efx_nvram_ops_s {
464 efx_rc_t (*envo_test)(efx_nic_t *);
465 #endif /* EFSYS_OPT_DIAG */
466 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
468 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
469 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
470 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
471 unsigned int, caddr_t, size_t);
472 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
473 unsigned int, size_t);
474 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
475 unsigned int, caddr_t, size_t);
476 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
477 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
478 uint32_t *, uint16_t *);
479 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
481 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
484 #endif /* EFSYS_OPT_NVRAM */
487 typedef struct efx_vpd_ops_s {
488 efx_rc_t (*evpdo_init)(efx_nic_t *);
489 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
490 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
491 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
492 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
493 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
495 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
497 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
498 efx_vpd_value_t *, unsigned int *);
499 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
500 void (*evpdo_fini)(efx_nic_t *);
502 #endif /* EFSYS_OPT_VPD */
504 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
506 __checkReturn efx_rc_t
507 efx_mcdi_nvram_partitions(
509 __out_bcount(size) caddr_t data,
511 __out unsigned int *npartnp);
513 __checkReturn efx_rc_t
514 efx_mcdi_nvram_metadata(
517 __out uint32_t *subtypep,
518 __out_ecount(4) uint16_t version[4],
519 __out_bcount_opt(size) char *descp,
522 __checkReturn efx_rc_t
526 __out_opt size_t *sizep,
527 __out_opt uint32_t *addressp,
528 __out_opt uint32_t *erase_sizep,
529 __out_opt uint32_t *write_sizep);
531 __checkReturn efx_rc_t
532 efx_mcdi_nvram_update_start(
534 __in uint32_t partn);
536 __checkReturn efx_rc_t
540 __in uint32_t offset,
541 __out_bcount(size) caddr_t data,
545 __checkReturn efx_rc_t
546 efx_mcdi_nvram_erase(
549 __in uint32_t offset,
552 __checkReturn efx_rc_t
553 efx_mcdi_nvram_write(
556 __in uint32_t offset,
557 __out_bcount(size) caddr_t data,
560 __checkReturn efx_rc_t
561 efx_mcdi_nvram_update_finish(
564 __in boolean_t reboot,
565 __out_opt uint32_t *resultp);
569 __checkReturn efx_rc_t
572 __in uint32_t partn);
574 #endif /* EFSYS_OPT_DIAG */
576 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
578 #if EFSYS_OPT_LICENSING
580 typedef struct efx_lic_ops_s {
581 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
582 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
583 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
584 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
585 size_t *, uint8_t *);
586 efx_rc_t (*elo_find_start)
587 (efx_nic_t *, caddr_t, size_t, uint32_t *);
588 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
589 uint32_t, uint32_t *);
590 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
591 uint32_t, uint32_t *, uint32_t *);
592 boolean_t (*elo_validate_key)(efx_nic_t *,
594 efx_rc_t (*elo_read_key)(efx_nic_t *,
595 caddr_t, size_t, uint32_t, uint32_t,
596 caddr_t, size_t, uint32_t *);
597 efx_rc_t (*elo_write_key)(efx_nic_t *,
598 caddr_t, size_t, uint32_t,
599 caddr_t, uint32_t, uint32_t *);
600 efx_rc_t (*elo_delete_key)(efx_nic_t *,
601 caddr_t, size_t, uint32_t,
602 uint32_t, uint32_t, uint32_t *);
603 efx_rc_t (*elo_create_partition)(efx_nic_t *,
605 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
611 typedef struct efx_drv_cfg_s {
612 uint32_t edc_min_vi_count;
613 uint32_t edc_max_vi_count;
615 uint32_t edc_max_piobuf_count;
616 uint32_t edc_pio_alloc_size;
621 efx_family_t en_family;
622 uint32_t en_features;
623 efsys_identifier_t *en_esip;
624 efsys_lock_t *en_eslp;
625 efsys_bar_t *en_esbp;
626 unsigned int en_mod_flags;
627 unsigned int en_reset_flags;
628 efx_nic_cfg_t en_nic_cfg;
629 efx_drv_cfg_t en_drv_cfg;
633 uint32_t en_ev_qcount;
634 uint32_t en_rx_qcount;
635 uint32_t en_tx_qcount;
636 const efx_nic_ops_t *en_enop;
637 const efx_ev_ops_t *en_eevop;
638 const efx_tx_ops_t *en_etxop;
639 const efx_rx_ops_t *en_erxop;
641 efx_filter_t en_filter;
642 const efx_filter_ops_t *en_efop;
643 #endif /* EFSYS_OPT_FILTER */
646 #endif /* EFSYS_OPT_MCDI */
648 efx_nvram_type_t en_nvram_locked;
649 const efx_nvram_ops_t *en_envop;
650 #endif /* EFSYS_OPT_NVRAM */
652 const efx_vpd_ops_t *en_evpdop;
653 #endif /* EFSYS_OPT_VPD */
654 #if EFSYS_OPT_RX_SCALE
655 efx_rx_hash_support_t en_hash_support;
656 efx_rx_scale_context_type_t en_rss_context_type;
657 uint32_t en_rss_context;
658 #endif /* EFSYS_OPT_RX_SCALE */
659 uint32_t en_vport_id;
660 #if EFSYS_OPT_LICENSING
661 const efx_lic_ops_t *en_elop;
662 boolean_t en_licensing_supported;
667 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
668 unsigned int enu_partn_mask;
669 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
672 size_t enu_svpd_length;
673 #endif /* EFSYS_OPT_VPD */
676 #endif /* EFSYS_OPT_SIENA */
679 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
687 size_t ena_svpd_length;
688 #endif /* EFSYS_OPT_VPD */
689 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
690 uint32_t ena_piobuf_count;
691 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
692 uint32_t ena_pio_write_vi_base;
693 /* Memory BAR mapping regions */
694 uint32_t ena_uc_mem_map_offset;
695 size_t ena_uc_mem_map_size;
696 uint32_t ena_wc_mem_map_offset;
697 size_t ena_wc_mem_map_size;
700 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
704 #define EFX_NIC_MAGIC 0x02121996
706 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
707 const efx_ev_callbacks_t *, void *);
709 typedef struct efx_evq_rxq_state_s {
710 unsigned int eers_rx_read_ptr;
711 unsigned int eers_rx_mask;
712 #if EFSYS_OPT_RX_PACKED_STREAM
713 unsigned int eers_rx_stream_npackets;
714 boolean_t eers_rx_packed_stream;
715 unsigned int eers_rx_packed_stream_credits;
717 } efx_evq_rxq_state_t;
722 unsigned int ee_index;
723 unsigned int ee_mask;
724 efsys_mem_t *ee_esmp;
726 uint32_t ee_stat[EV_NQSTATS];
727 #endif /* EFSYS_OPT_QSTATS */
729 efx_ev_handler_t ee_rx;
730 efx_ev_handler_t ee_tx;
731 efx_ev_handler_t ee_driver;
732 efx_ev_handler_t ee_global;
733 efx_ev_handler_t ee_drv_gen;
735 efx_ev_handler_t ee_mcdi;
736 #endif /* EFSYS_OPT_MCDI */
738 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
743 #define EFX_EVQ_MAGIC 0x08081997
745 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
751 unsigned int er_index;
752 unsigned int er_label;
753 unsigned int er_mask;
754 efsys_mem_t *er_esmp;
757 #define EFX_RXQ_MAGIC 0x15022005
762 unsigned int et_index;
763 unsigned int et_mask;
764 efsys_mem_t *et_esmp;
765 #if EFSYS_OPT_HUNTINGTON
766 uint32_t et_pio_bufnum;
767 uint32_t et_pio_blknum;
768 uint32_t et_pio_write_offset;
769 uint32_t et_pio_offset;
773 uint32_t et_stat[TX_NQSTATS];
774 #endif /* EFSYS_OPT_QSTATS */
777 #define EFX_TXQ_MAGIC 0x05092005
779 #define EFX_MAC_ADDR_COPY(_dst, _src) \
781 (_dst)[0] = (_src)[0]; \
782 (_dst)[1] = (_src)[1]; \
783 (_dst)[2] = (_src)[2]; \
784 (_dst)[3] = (_src)[3]; \
785 (_dst)[4] = (_src)[4]; \
786 (_dst)[5] = (_src)[5]; \
787 _NOTE(CONSTANTCONDITION) \
790 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
792 uint16_t *_d = (uint16_t *)(_dst); \
796 _NOTE(CONSTANTCONDITION) \
799 #if EFSYS_OPT_CHECK_REG
800 #define EFX_CHECK_REG(_enp, _reg) \
802 const char *name = #_reg; \
803 char min = name[4]; \
804 char max = name[5]; \
807 switch ((_enp)->en_family) { \
808 case EFX_FAMILY_SIENA: \
812 case EFX_FAMILY_HUNTINGTON: \
816 case EFX_FAMILY_MEDFORD: \
825 EFSYS_ASSERT3S(rev, >=, min); \
826 EFSYS_ASSERT3S(rev, <=, max); \
828 _NOTE(CONSTANTCONDITION) \
831 #define EFX_CHECK_REG(_enp, _reg) do { \
832 _NOTE(CONSTANTCONDITION) \
836 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
838 EFX_CHECK_REG((_enp), (_reg)); \
839 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
841 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
842 uint32_t, _reg ## _OFST, \
843 uint32_t, (_edp)->ed_u32[0]); \
844 _NOTE(CONSTANTCONDITION) \
847 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
849 EFX_CHECK_REG((_enp), (_reg)); \
850 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
851 uint32_t, _reg ## _OFST, \
852 uint32_t, (_edp)->ed_u32[0]); \
853 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
855 _NOTE(CONSTANTCONDITION) \
858 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
860 EFX_CHECK_REG((_enp), (_reg)); \
861 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
863 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
864 uint32_t, _reg ## _OFST, \
865 uint32_t, (_eqp)->eq_u32[1], \
866 uint32_t, (_eqp)->eq_u32[0]); \
867 _NOTE(CONSTANTCONDITION) \
870 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
872 EFX_CHECK_REG((_enp), (_reg)); \
873 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
874 uint32_t, _reg ## _OFST, \
875 uint32_t, (_eqp)->eq_u32[1], \
876 uint32_t, (_eqp)->eq_u32[0]); \
877 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
879 _NOTE(CONSTANTCONDITION) \
882 #define EFX_BAR_READO(_enp, _reg, _eop) \
884 EFX_CHECK_REG((_enp), (_reg)); \
885 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
887 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
888 uint32_t, _reg ## _OFST, \
889 uint32_t, (_eop)->eo_u32[3], \
890 uint32_t, (_eop)->eo_u32[2], \
891 uint32_t, (_eop)->eo_u32[1], \
892 uint32_t, (_eop)->eo_u32[0]); \
893 _NOTE(CONSTANTCONDITION) \
896 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
898 EFX_CHECK_REG((_enp), (_reg)); \
899 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
900 uint32_t, _reg ## _OFST, \
901 uint32_t, (_eop)->eo_u32[3], \
902 uint32_t, (_eop)->eo_u32[2], \
903 uint32_t, (_eop)->eo_u32[1], \
904 uint32_t, (_eop)->eo_u32[0]); \
905 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
907 _NOTE(CONSTANTCONDITION) \
910 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
912 EFX_CHECK_REG((_enp), (_reg)); \
913 EFSYS_BAR_READD((_enp)->en_esbp, \
914 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
916 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
917 uint32_t, (_index), \
918 uint32_t, _reg ## _OFST, \
919 uint32_t, (_edp)->ed_u32[0]); \
920 _NOTE(CONSTANTCONDITION) \
923 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
925 EFX_CHECK_REG((_enp), (_reg)); \
926 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
927 uint32_t, (_index), \
928 uint32_t, _reg ## _OFST, \
929 uint32_t, (_edp)->ed_u32[0]); \
930 EFSYS_BAR_WRITED((_enp)->en_esbp, \
931 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
933 _NOTE(CONSTANTCONDITION) \
936 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
938 EFX_CHECK_REG((_enp), (_reg)); \
939 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
940 uint32_t, (_index), \
941 uint32_t, _reg ## _OFST, \
942 uint32_t, (_edp)->ed_u32[0]); \
943 EFSYS_BAR_WRITED((_enp)->en_esbp, \
945 (2 * sizeof (efx_dword_t)) + \
946 ((_index) * _reg ## _STEP)), \
948 _NOTE(CONSTANTCONDITION) \
951 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
953 EFX_CHECK_REG((_enp), (_reg)); \
954 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
955 uint32_t, (_index), \
956 uint32_t, _reg ## _OFST, \
957 uint32_t, (_edp)->ed_u32[0]); \
958 EFSYS_BAR_WRITED((_enp)->en_esbp, \
960 (3 * sizeof (efx_dword_t)) + \
961 ((_index) * _reg ## _STEP)), \
963 _NOTE(CONSTANTCONDITION) \
966 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
968 EFX_CHECK_REG((_enp), (_reg)); \
969 EFSYS_BAR_READQ((_enp)->en_esbp, \
970 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
972 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
973 uint32_t, (_index), \
974 uint32_t, _reg ## _OFST, \
975 uint32_t, (_eqp)->eq_u32[1], \
976 uint32_t, (_eqp)->eq_u32[0]); \
977 _NOTE(CONSTANTCONDITION) \
980 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
982 EFX_CHECK_REG((_enp), (_reg)); \
983 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
984 uint32_t, (_index), \
985 uint32_t, _reg ## _OFST, \
986 uint32_t, (_eqp)->eq_u32[1], \
987 uint32_t, (_eqp)->eq_u32[0]); \
988 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
989 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
991 _NOTE(CONSTANTCONDITION) \
994 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
996 EFX_CHECK_REG((_enp), (_reg)); \
997 EFSYS_BAR_READO((_enp)->en_esbp, \
998 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1000 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1001 uint32_t, (_index), \
1002 uint32_t, _reg ## _OFST, \
1003 uint32_t, (_eop)->eo_u32[3], \
1004 uint32_t, (_eop)->eo_u32[2], \
1005 uint32_t, (_eop)->eo_u32[1], \
1006 uint32_t, (_eop)->eo_u32[0]); \
1007 _NOTE(CONSTANTCONDITION) \
1010 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1012 EFX_CHECK_REG((_enp), (_reg)); \
1013 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1014 uint32_t, (_index), \
1015 uint32_t, _reg ## _OFST, \
1016 uint32_t, (_eop)->eo_u32[3], \
1017 uint32_t, (_eop)->eo_u32[2], \
1018 uint32_t, (_eop)->eo_u32[1], \
1019 uint32_t, (_eop)->eo_u32[0]); \
1020 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1021 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1023 _NOTE(CONSTANTCONDITION) \
1027 * Allow drivers to perform optimised 128-bit doorbell writes.
1028 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1029 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1030 * the need for locking in the host, and are the only ones known to be safe to
1031 * use 128-bites write with.
1033 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1035 EFX_CHECK_REG((_enp), (_reg)); \
1036 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1039 uint32_t, (_index), \
1040 uint32_t, _reg ## _OFST, \
1041 uint32_t, (_eop)->eo_u32[3], \
1042 uint32_t, (_eop)->eo_u32[2], \
1043 uint32_t, (_eop)->eo_u32[1], \
1044 uint32_t, (_eop)->eo_u32[0]); \
1045 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1046 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1048 _NOTE(CONSTANTCONDITION) \
1051 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1053 unsigned int _new = (_wptr); \
1054 unsigned int _old = (_owptr); \
1056 if ((_new) >= (_old)) \
1057 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1058 (_old) * sizeof (efx_desc_t), \
1059 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1062 * It is cheaper to sync entire map than sync \
1063 * two parts especially when offset/size are \
1064 * ignored and entire map is synced in any case.\
1066 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1068 (_entries) * sizeof (efx_desc_t)); \
1069 _NOTE(CONSTANTCONDITION) \
1072 extern __checkReturn efx_rc_t
1074 __in efx_nic_t *enp);
1076 extern __checkReturn efx_rc_t
1078 __in efx_nic_t *enp);
1081 efx_mac_multicast_hash_compute(
1082 __in_ecount(6*count) uint8_t const *addrs,
1084 __out efx_oword_t *hash_low,
1085 __out efx_oword_t *hash_high);
1087 extern __checkReturn efx_rc_t
1089 __in efx_nic_t *enp);
1093 __in efx_nic_t *enp);
1097 /* VPD utility functions */
1099 extern __checkReturn efx_rc_t
1100 efx_vpd_hunk_length(
1101 __in_bcount(size) caddr_t data,
1103 __out size_t *lengthp);
1105 extern __checkReturn efx_rc_t
1106 efx_vpd_hunk_verify(
1107 __in_bcount(size) caddr_t data,
1109 __out_opt boolean_t *cksummedp);
1111 extern __checkReturn efx_rc_t
1112 efx_vpd_hunk_reinit(
1113 __in_bcount(size) caddr_t data,
1115 __in boolean_t wantpid);
1117 extern __checkReturn efx_rc_t
1119 __in_bcount(size) caddr_t data,
1121 __in efx_vpd_tag_t tag,
1122 __in efx_vpd_keyword_t keyword,
1123 __out unsigned int *payloadp,
1124 __out uint8_t *paylenp);
1126 extern __checkReturn efx_rc_t
1128 __in_bcount(size) caddr_t data,
1130 __out efx_vpd_tag_t *tagp,
1131 __out efx_vpd_keyword_t *keyword,
1132 __out_opt unsigned int *payloadp,
1133 __out_opt uint8_t *paylenp,
1134 __inout unsigned int *contp);
1136 extern __checkReturn efx_rc_t
1138 __in_bcount(size) caddr_t data,
1140 __in efx_vpd_value_t *evvp);
1142 #endif /* EFSYS_OPT_VPD */
1146 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1148 typedef struct efx_register_set_s {
1149 unsigned int address;
1153 } efx_register_set_t;
1155 extern __checkReturn efx_rc_t
1156 efx_nic_test_registers(
1157 __in efx_nic_t *enp,
1158 __in efx_register_set_t *rsp,
1161 extern __checkReturn efx_rc_t
1162 efx_nic_test_tables(
1163 __in efx_nic_t *enp,
1164 __in efx_register_set_t *rsp,
1165 __in efx_pattern_type_t pattern,
1168 #endif /* EFSYS_OPT_DIAG */
1172 extern __checkReturn efx_rc_t
1173 efx_mcdi_set_workaround(
1174 __in efx_nic_t *enp,
1176 __in boolean_t enabled,
1177 __out_opt uint32_t *flagsp);
1179 extern __checkReturn efx_rc_t
1180 efx_mcdi_get_workarounds(
1181 __in efx_nic_t *enp,
1182 __out_opt uint32_t *implementedp,
1183 __out_opt uint32_t *enabledp);
1185 #endif /* EFSYS_OPT_MCDI */
1187 #if EFSYS_OPT_MAC_STATS
1190 * Closed range of stats (i.e. the first and the last are included).
1191 * The last must be greater or equal (if the range is one item only) to
1194 struct efx_mac_stats_range {
1195 efx_mac_stat_t first;
1196 efx_mac_stat_t last;
1200 efx_mac_stats_mask_add_ranges(
1201 __inout_bcount(mask_size) uint32_t *maskp,
1202 __in size_t mask_size,
1203 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1204 __in unsigned int rng_count);
1206 #endif /* EFSYS_OPT_MAC_STATS */
1212 #endif /* _SYS_EFX_IMPL_H */