1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
14 /* FIXME: Add definition for driver generated software events */
15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
21 #include "siena_impl.h"
22 #endif /* EFSYS_OPT_SIENA */
24 #if EFSYS_OPT_HUNTINGTON
25 #include "hunt_impl.h"
26 #endif /* EFSYS_OPT_HUNTINGTON */
29 #include "medford_impl.h"
30 #endif /* EFSYS_OPT_MEDFORD */
32 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
33 #include "ef10_impl.h"
34 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
40 #define EFX_MOD_MCDI 0x00000001
41 #define EFX_MOD_PROBE 0x00000002
42 #define EFX_MOD_NVRAM 0x00000004
43 #define EFX_MOD_VPD 0x00000008
44 #define EFX_MOD_NIC 0x00000010
45 #define EFX_MOD_INTR 0x00000020
46 #define EFX_MOD_EV 0x00000040
47 #define EFX_MOD_RX 0x00000080
48 #define EFX_MOD_TX 0x00000100
49 #define EFX_MOD_PORT 0x00000200
50 #define EFX_MOD_MON 0x00000400
51 #define EFX_MOD_FILTER 0x00001000
52 #define EFX_MOD_LIC 0x00002000
53 #define EFX_MOD_TUNNEL 0x00004000
55 #define EFX_RESET_PHY 0x00000001
56 #define EFX_RESET_RXQ_ERR 0x00000002
57 #define EFX_RESET_TXQ_ERR 0x00000004
59 typedef enum efx_mac_type_e {
67 typedef struct efx_ev_ops_s {
68 efx_rc_t (*eevo_init)(efx_nic_t *);
69 void (*eevo_fini)(efx_nic_t *);
70 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
71 efsys_mem_t *, size_t, uint32_t,
72 uint32_t, uint32_t, efx_evq_t *);
73 void (*eevo_qdestroy)(efx_evq_t *);
74 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
75 void (*eevo_qpost)(efx_evq_t *, uint16_t);
76 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
78 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
82 typedef struct efx_tx_ops_s {
83 efx_rc_t (*etxo_init)(efx_nic_t *);
84 void (*etxo_fini)(efx_nic_t *);
85 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
86 unsigned int, unsigned int,
87 efsys_mem_t *, size_t,
89 efx_evq_t *, efx_txq_t *,
91 void (*etxo_qdestroy)(efx_txq_t *);
92 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
93 unsigned int, unsigned int,
95 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
96 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
97 efx_rc_t (*etxo_qflush)(efx_txq_t *);
98 void (*etxo_qenable)(efx_txq_t *);
99 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
100 void (*etxo_qpio_disable)(efx_txq_t *);
101 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
103 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
105 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
106 unsigned int, unsigned int,
108 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
111 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
114 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
117 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
120 void (*etxo_qstats_update)(efx_txq_t *,
125 typedef struct efx_rx_ops_s {
126 efx_rc_t (*erxo_init)(efx_nic_t *);
127 void (*erxo_fini)(efx_nic_t *);
128 #if EFSYS_OPT_RX_SCATTER
129 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
131 #if EFSYS_OPT_RX_SCALE
132 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
133 efx_rx_scale_context_type_t,
134 uint32_t, uint32_t *);
135 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
136 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
138 efx_rx_hash_type_t, boolean_t);
139 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
141 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
142 unsigned int *, size_t);
143 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
145 #endif /* EFSYS_OPT_RX_SCALE */
146 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
148 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
149 unsigned int, unsigned int,
151 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
152 #if EFSYS_OPT_RX_PACKED_STREAM
153 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
154 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
156 uint16_t *, uint32_t *, uint32_t *);
158 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
159 void (*erxo_qenable)(efx_rxq_t *);
160 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
161 unsigned int, efx_rxq_type_t, uint32_t,
162 efsys_mem_t *, size_t, uint32_t,
164 efx_evq_t *, efx_rxq_t *);
165 void (*erxo_qdestroy)(efx_rxq_t *);
168 typedef struct efx_mac_ops_s {
169 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
170 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
171 efx_rc_t (*emo_addr_set)(efx_nic_t *);
172 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
173 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
174 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
175 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
176 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
177 efx_rxq_t *, boolean_t);
178 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
179 #if EFSYS_OPT_LOOPBACK
180 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
181 efx_loopback_type_t);
182 #endif /* EFSYS_OPT_LOOPBACK */
183 #if EFSYS_OPT_MAC_STATS
184 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
185 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
186 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
187 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
188 uint16_t, boolean_t);
189 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
190 efsys_stat_t *, uint32_t *);
191 #endif /* EFSYS_OPT_MAC_STATS */
194 typedef struct efx_phy_ops_s {
195 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
196 efx_rc_t (*epo_reset)(efx_nic_t *);
197 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
198 efx_rc_t (*epo_verify)(efx_nic_t *);
199 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
200 #if EFSYS_OPT_PHY_STATS
201 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
203 #endif /* EFSYS_OPT_PHY_STATS */
205 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
206 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
207 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
208 efx_bist_result_t *, uint32_t *,
209 unsigned long *, size_t);
210 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
211 #endif /* EFSYS_OPT_BIST */
215 typedef struct efx_filter_ops_s {
216 efx_rc_t (*efo_init)(efx_nic_t *);
217 void (*efo_fini)(efx_nic_t *);
218 efx_rc_t (*efo_restore)(efx_nic_t *);
219 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
220 boolean_t may_replace);
221 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
222 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
224 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
225 boolean_t, boolean_t, boolean_t,
226 uint8_t const *, uint32_t);
229 extern __checkReturn efx_rc_t
230 efx_filter_reconfigure(
232 __in_ecount(6) uint8_t const *mac_addr,
233 __in boolean_t all_unicst,
234 __in boolean_t mulcst,
235 __in boolean_t all_mulcst,
236 __in boolean_t brdcst,
237 __in_ecount(6*count) uint8_t const *addrs,
238 __in uint32_t count);
240 #endif /* EFSYS_OPT_FILTER */
243 typedef struct efx_tunnel_ops_s {
244 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
245 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
247 #endif /* EFSYS_OPT_TUNNEL */
249 typedef struct efx_port_s {
250 efx_mac_type_t ep_mac_type;
251 uint32_t ep_phy_type;
254 uint8_t ep_mac_addr[6];
255 efx_link_mode_t ep_link_mode;
256 boolean_t ep_all_unicst;
258 boolean_t ep_all_mulcst;
260 unsigned int ep_fcntl;
261 boolean_t ep_fcntl_autoneg;
262 efx_oword_t ep_multicst_hash[2];
263 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
264 EFX_MAC_MULTICAST_LIST_MAX];
265 uint32_t ep_mulcst_addr_count;
266 #if EFSYS_OPT_LOOPBACK
267 efx_loopback_type_t ep_loopback_type;
268 efx_link_mode_t ep_loopback_link_mode;
269 #endif /* EFSYS_OPT_LOOPBACK */
270 #if EFSYS_OPT_PHY_FLAGS
271 uint32_t ep_phy_flags;
272 #endif /* EFSYS_OPT_PHY_FLAGS */
273 #if EFSYS_OPT_PHY_LED_CONTROL
274 efx_phy_led_mode_t ep_phy_led_mode;
275 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
276 efx_phy_media_type_t ep_fixed_port_type;
277 efx_phy_media_type_t ep_module_type;
278 uint32_t ep_adv_cap_mask;
279 uint32_t ep_lp_cap_mask;
280 uint32_t ep_default_adv_cap_mask;
281 uint32_t ep_phy_cap_mask;
282 boolean_t ep_mac_drain;
284 efx_bist_type_t ep_current_bist;
286 const efx_mac_ops_t *ep_emop;
287 const efx_phy_ops_t *ep_epop;
290 typedef struct efx_mon_ops_s {
291 #if EFSYS_OPT_MON_STATS
292 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
293 efx_mon_stat_value_t *);
294 #endif /* EFSYS_OPT_MON_STATS */
297 typedef struct efx_mon_s {
298 efx_mon_type_t em_type;
299 const efx_mon_ops_t *em_emop;
302 typedef struct efx_intr_ops_s {
303 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
304 void (*eio_enable)(efx_nic_t *);
305 void (*eio_disable)(efx_nic_t *);
306 void (*eio_disable_unlocked)(efx_nic_t *);
307 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
308 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
309 void (*eio_status_message)(efx_nic_t *, unsigned int,
311 void (*eio_fatal)(efx_nic_t *);
312 void (*eio_fini)(efx_nic_t *);
315 typedef struct efx_intr_s {
316 const efx_intr_ops_t *ei_eiop;
317 efsys_mem_t *ei_esmp;
318 efx_intr_type_t ei_type;
319 unsigned int ei_level;
322 typedef struct efx_nic_ops_s {
323 efx_rc_t (*eno_probe)(efx_nic_t *);
324 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
325 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
326 efx_rc_t (*eno_reset)(efx_nic_t *);
327 efx_rc_t (*eno_init)(efx_nic_t *);
328 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
329 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
330 uint32_t *, size_t *);
332 efx_rc_t (*eno_register_test)(efx_nic_t *);
333 #endif /* EFSYS_OPT_DIAG */
334 void (*eno_fini)(efx_nic_t *);
335 void (*eno_unprobe)(efx_nic_t *);
338 #ifndef EFX_TXQ_LIMIT_TARGET
339 #define EFX_TXQ_LIMIT_TARGET 259
341 #ifndef EFX_RXQ_LIMIT_TARGET
342 #define EFX_RXQ_LIMIT_TARGET 512
350 typedef struct siena_filter_spec_s {
353 uint32_t sfs_dmaq_id;
354 uint32_t sfs_dword[3];
355 } siena_filter_spec_t;
357 typedef enum siena_filter_type_e {
358 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
359 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
360 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
361 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
362 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
363 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
365 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
366 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
367 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
368 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
369 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
370 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
372 EFX_SIENA_FILTER_NTYPES
373 } siena_filter_type_t;
375 typedef enum siena_filter_tbl_id_e {
376 EFX_SIENA_FILTER_TBL_RX_IP = 0,
377 EFX_SIENA_FILTER_TBL_RX_MAC,
378 EFX_SIENA_FILTER_TBL_TX_IP,
379 EFX_SIENA_FILTER_TBL_TX_MAC,
380 EFX_SIENA_FILTER_NTBLS
381 } siena_filter_tbl_id_t;
383 typedef struct siena_filter_tbl_s {
384 int sft_size; /* number of entries */
385 int sft_used; /* active count */
386 uint32_t *sft_bitmap; /* active bitmap */
387 siena_filter_spec_t *sft_spec; /* array of saved specs */
388 } siena_filter_tbl_t;
390 typedef struct siena_filter_s {
391 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
392 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
395 #endif /* EFSYS_OPT_SIENA */
397 typedef struct efx_filter_s {
399 siena_filter_t *ef_siena_filter;
400 #endif /* EFSYS_OPT_SIENA */
401 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
402 ef10_filter_table_t *ef_ef10_filter_table;
403 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
409 siena_filter_tbl_clear(
411 __in siena_filter_tbl_id_t tbl);
413 #endif /* EFSYS_OPT_SIENA */
415 #endif /* EFSYS_OPT_FILTER */
419 #define EFX_TUNNEL_MAXNENTRIES (16)
423 typedef struct efx_tunnel_udp_entry_s {
424 uint16_t etue_port; /* host/cpu-endian */
425 uint16_t etue_protocol;
426 } efx_tunnel_udp_entry_t;
428 typedef struct efx_tunnel_cfg_s {
429 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
430 unsigned int etc_udp_entries_num;
433 #endif /* EFSYS_OPT_TUNNEL */
435 typedef struct efx_mcdi_ops_s {
436 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
437 void (*emco_send_request)(efx_nic_t *, void *, size_t,
439 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
440 boolean_t (*emco_poll_response)(efx_nic_t *);
441 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
442 void (*emco_fini)(efx_nic_t *);
443 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
444 efx_mcdi_feature_id_t, boolean_t *);
445 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
449 typedef struct efx_mcdi_s {
450 const efx_mcdi_ops_t *em_emcop;
451 const efx_mcdi_transport_t *em_emtp;
452 efx_mcdi_iface_t em_emip;
455 #endif /* EFSYS_OPT_MCDI */
459 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
460 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
462 typedef struct efx_nvram_ops_s {
464 efx_rc_t (*envo_test)(efx_nic_t *);
465 #endif /* EFSYS_OPT_DIAG */
466 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
468 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
469 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
470 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
471 unsigned int, caddr_t, size_t);
472 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
473 unsigned int, caddr_t, size_t);
474 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
475 unsigned int, size_t);
476 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
477 unsigned int, caddr_t, size_t);
478 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
480 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
481 uint32_t *, uint16_t *);
482 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
484 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
487 #endif /* EFSYS_OPT_NVRAM */
490 typedef struct efx_vpd_ops_s {
491 efx_rc_t (*evpdo_init)(efx_nic_t *);
492 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
493 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
494 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
495 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
496 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
498 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
500 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
501 efx_vpd_value_t *, unsigned int *);
502 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
503 void (*evpdo_fini)(efx_nic_t *);
505 #endif /* EFSYS_OPT_VPD */
507 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
509 __checkReturn efx_rc_t
510 efx_mcdi_nvram_partitions(
512 __out_bcount(size) caddr_t data,
514 __out unsigned int *npartnp);
516 __checkReturn efx_rc_t
517 efx_mcdi_nvram_metadata(
520 __out uint32_t *subtypep,
521 __out_ecount(4) uint16_t version[4],
522 __out_bcount_opt(size) char *descp,
525 __checkReturn efx_rc_t
529 __out_opt size_t *sizep,
530 __out_opt uint32_t *addressp,
531 __out_opt uint32_t *erase_sizep,
532 __out_opt uint32_t *write_sizep);
534 __checkReturn efx_rc_t
535 efx_mcdi_nvram_update_start(
537 __in uint32_t partn);
539 __checkReturn efx_rc_t
543 __in uint32_t offset,
544 __out_bcount(size) caddr_t data,
548 __checkReturn efx_rc_t
549 efx_mcdi_nvram_erase(
552 __in uint32_t offset,
555 __checkReturn efx_rc_t
556 efx_mcdi_nvram_write(
559 __in uint32_t offset,
560 __out_bcount(size) caddr_t data,
563 __checkReturn efx_rc_t
564 efx_mcdi_nvram_update_finish(
567 __in boolean_t reboot,
568 __out_opt uint32_t *verify_resultp);
572 __checkReturn efx_rc_t
575 __in uint32_t partn);
577 #endif /* EFSYS_OPT_DIAG */
579 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
581 #if EFSYS_OPT_LICENSING
583 typedef struct efx_lic_ops_s {
584 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
585 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
586 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
587 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
588 size_t *, uint8_t *);
589 efx_rc_t (*elo_find_start)
590 (efx_nic_t *, caddr_t, size_t, uint32_t *);
591 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
592 uint32_t, uint32_t *);
593 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
594 uint32_t, uint32_t *, uint32_t *);
595 boolean_t (*elo_validate_key)(efx_nic_t *,
597 efx_rc_t (*elo_read_key)(efx_nic_t *,
598 caddr_t, size_t, uint32_t, uint32_t,
599 caddr_t, size_t, uint32_t *);
600 efx_rc_t (*elo_write_key)(efx_nic_t *,
601 caddr_t, size_t, uint32_t,
602 caddr_t, uint32_t, uint32_t *);
603 efx_rc_t (*elo_delete_key)(efx_nic_t *,
604 caddr_t, size_t, uint32_t,
605 uint32_t, uint32_t, uint32_t *);
606 efx_rc_t (*elo_create_partition)(efx_nic_t *,
608 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
614 typedef struct efx_drv_cfg_s {
615 uint32_t edc_min_vi_count;
616 uint32_t edc_max_vi_count;
618 uint32_t edc_max_piobuf_count;
619 uint32_t edc_pio_alloc_size;
624 efx_family_t en_family;
625 uint32_t en_features;
626 efsys_identifier_t *en_esip;
627 efsys_lock_t *en_eslp;
628 efsys_bar_t *en_esbp;
629 unsigned int en_mod_flags;
630 unsigned int en_reset_flags;
631 efx_nic_cfg_t en_nic_cfg;
632 efx_drv_cfg_t en_drv_cfg;
636 uint32_t en_ev_qcount;
637 uint32_t en_rx_qcount;
638 uint32_t en_tx_qcount;
639 const efx_nic_ops_t *en_enop;
640 const efx_ev_ops_t *en_eevop;
641 const efx_tx_ops_t *en_etxop;
642 const efx_rx_ops_t *en_erxop;
644 efx_filter_t en_filter;
645 const efx_filter_ops_t *en_efop;
646 #endif /* EFSYS_OPT_FILTER */
648 efx_tunnel_cfg_t en_tunnel_cfg;
649 const efx_tunnel_ops_t *en_etop;
650 #endif /* EFSYS_OPT_TUNNEL */
653 #endif /* EFSYS_OPT_MCDI */
655 uint32_t en_nvram_partn_locked;
656 const efx_nvram_ops_t *en_envop;
657 #endif /* EFSYS_OPT_NVRAM */
659 const efx_vpd_ops_t *en_evpdop;
660 #endif /* EFSYS_OPT_VPD */
661 #if EFSYS_OPT_RX_SCALE
662 efx_rx_hash_support_t en_hash_support;
663 efx_rx_scale_context_type_t en_rss_context_type;
664 uint32_t en_rss_context;
665 #endif /* EFSYS_OPT_RX_SCALE */
666 uint32_t en_vport_id;
667 #if EFSYS_OPT_LICENSING
668 const efx_lic_ops_t *en_elop;
669 boolean_t en_licensing_supported;
674 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
675 unsigned int enu_partn_mask;
676 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
679 size_t enu_svpd_length;
680 #endif /* EFSYS_OPT_VPD */
683 #endif /* EFSYS_OPT_SIENA */
686 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
694 size_t ena_svpd_length;
695 #endif /* EFSYS_OPT_VPD */
696 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
697 uint32_t ena_piobuf_count;
698 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
699 uint32_t ena_pio_write_vi_base;
700 /* Memory BAR mapping regions */
701 uint32_t ena_uc_mem_map_offset;
702 size_t ena_uc_mem_map_size;
703 uint32_t ena_wc_mem_map_offset;
704 size_t ena_wc_mem_map_size;
707 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
711 #define EFX_NIC_MAGIC 0x02121996
713 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
714 const efx_ev_callbacks_t *, void *);
716 typedef struct efx_evq_rxq_state_s {
717 unsigned int eers_rx_read_ptr;
718 unsigned int eers_rx_mask;
719 #if EFSYS_OPT_RX_PACKED_STREAM
720 unsigned int eers_rx_stream_npackets;
721 boolean_t eers_rx_packed_stream;
722 unsigned int eers_rx_packed_stream_credits;
724 } efx_evq_rxq_state_t;
729 unsigned int ee_index;
730 unsigned int ee_mask;
731 efsys_mem_t *ee_esmp;
733 uint32_t ee_stat[EV_NQSTATS];
734 #endif /* EFSYS_OPT_QSTATS */
736 efx_ev_handler_t ee_rx;
737 efx_ev_handler_t ee_tx;
738 efx_ev_handler_t ee_driver;
739 efx_ev_handler_t ee_global;
740 efx_ev_handler_t ee_drv_gen;
742 efx_ev_handler_t ee_mcdi;
743 #endif /* EFSYS_OPT_MCDI */
745 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
750 #define EFX_EVQ_MAGIC 0x08081997
752 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
758 unsigned int er_index;
759 unsigned int er_label;
760 unsigned int er_mask;
761 efsys_mem_t *er_esmp;
762 efx_evq_rxq_state_t *er_ev_qstate;
765 #define EFX_RXQ_MAGIC 0x15022005
770 unsigned int et_index;
771 unsigned int et_mask;
772 efsys_mem_t *et_esmp;
773 #if EFSYS_OPT_HUNTINGTON
774 uint32_t et_pio_bufnum;
775 uint32_t et_pio_blknum;
776 uint32_t et_pio_write_offset;
777 uint32_t et_pio_offset;
781 uint32_t et_stat[TX_NQSTATS];
782 #endif /* EFSYS_OPT_QSTATS */
785 #define EFX_TXQ_MAGIC 0x05092005
787 #define EFX_MAC_ADDR_COPY(_dst, _src) \
789 (_dst)[0] = (_src)[0]; \
790 (_dst)[1] = (_src)[1]; \
791 (_dst)[2] = (_src)[2]; \
792 (_dst)[3] = (_src)[3]; \
793 (_dst)[4] = (_src)[4]; \
794 (_dst)[5] = (_src)[5]; \
795 _NOTE(CONSTANTCONDITION) \
798 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
800 uint16_t *_d = (uint16_t *)(_dst); \
804 _NOTE(CONSTANTCONDITION) \
807 #if EFSYS_OPT_CHECK_REG
808 #define EFX_CHECK_REG(_enp, _reg) \
810 const char *name = #_reg; \
811 char min = name[4]; \
812 char max = name[5]; \
815 switch ((_enp)->en_family) { \
816 case EFX_FAMILY_SIENA: \
820 case EFX_FAMILY_HUNTINGTON: \
824 case EFX_FAMILY_MEDFORD: \
833 EFSYS_ASSERT3S(rev, >=, min); \
834 EFSYS_ASSERT3S(rev, <=, max); \
836 _NOTE(CONSTANTCONDITION) \
839 #define EFX_CHECK_REG(_enp, _reg) do { \
840 _NOTE(CONSTANTCONDITION) \
844 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
846 EFX_CHECK_REG((_enp), (_reg)); \
847 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
849 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
850 uint32_t, _reg ## _OFST, \
851 uint32_t, (_edp)->ed_u32[0]); \
852 _NOTE(CONSTANTCONDITION) \
855 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
857 EFX_CHECK_REG((_enp), (_reg)); \
858 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
859 uint32_t, _reg ## _OFST, \
860 uint32_t, (_edp)->ed_u32[0]); \
861 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
863 _NOTE(CONSTANTCONDITION) \
866 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
868 EFX_CHECK_REG((_enp), (_reg)); \
869 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
871 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
872 uint32_t, _reg ## _OFST, \
873 uint32_t, (_eqp)->eq_u32[1], \
874 uint32_t, (_eqp)->eq_u32[0]); \
875 _NOTE(CONSTANTCONDITION) \
878 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
880 EFX_CHECK_REG((_enp), (_reg)); \
881 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
882 uint32_t, _reg ## _OFST, \
883 uint32_t, (_eqp)->eq_u32[1], \
884 uint32_t, (_eqp)->eq_u32[0]); \
885 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
887 _NOTE(CONSTANTCONDITION) \
890 #define EFX_BAR_READO(_enp, _reg, _eop) \
892 EFX_CHECK_REG((_enp), (_reg)); \
893 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
895 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
896 uint32_t, _reg ## _OFST, \
897 uint32_t, (_eop)->eo_u32[3], \
898 uint32_t, (_eop)->eo_u32[2], \
899 uint32_t, (_eop)->eo_u32[1], \
900 uint32_t, (_eop)->eo_u32[0]); \
901 _NOTE(CONSTANTCONDITION) \
904 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
906 EFX_CHECK_REG((_enp), (_reg)); \
907 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
908 uint32_t, _reg ## _OFST, \
909 uint32_t, (_eop)->eo_u32[3], \
910 uint32_t, (_eop)->eo_u32[2], \
911 uint32_t, (_eop)->eo_u32[1], \
912 uint32_t, (_eop)->eo_u32[0]); \
913 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
915 _NOTE(CONSTANTCONDITION) \
918 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
920 EFX_CHECK_REG((_enp), (_reg)); \
921 EFSYS_BAR_READD((_enp)->en_esbp, \
922 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
924 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
925 uint32_t, (_index), \
926 uint32_t, _reg ## _OFST, \
927 uint32_t, (_edp)->ed_u32[0]); \
928 _NOTE(CONSTANTCONDITION) \
931 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
933 EFX_CHECK_REG((_enp), (_reg)); \
934 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
935 uint32_t, (_index), \
936 uint32_t, _reg ## _OFST, \
937 uint32_t, (_edp)->ed_u32[0]); \
938 EFSYS_BAR_WRITED((_enp)->en_esbp, \
939 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
941 _NOTE(CONSTANTCONDITION) \
944 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
946 EFX_CHECK_REG((_enp), (_reg)); \
947 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
948 uint32_t, (_index), \
949 uint32_t, _reg ## _OFST, \
950 uint32_t, (_edp)->ed_u32[0]); \
951 EFSYS_BAR_WRITED((_enp)->en_esbp, \
953 (2 * sizeof (efx_dword_t)) + \
954 ((_index) * _reg ## _STEP)), \
956 _NOTE(CONSTANTCONDITION) \
959 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
961 EFX_CHECK_REG((_enp), (_reg)); \
962 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
963 uint32_t, (_index), \
964 uint32_t, _reg ## _OFST, \
965 uint32_t, (_edp)->ed_u32[0]); \
966 EFSYS_BAR_WRITED((_enp)->en_esbp, \
968 (3 * sizeof (efx_dword_t)) + \
969 ((_index) * _reg ## _STEP)), \
971 _NOTE(CONSTANTCONDITION) \
974 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
976 EFX_CHECK_REG((_enp), (_reg)); \
977 EFSYS_BAR_READQ((_enp)->en_esbp, \
978 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
980 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
981 uint32_t, (_index), \
982 uint32_t, _reg ## _OFST, \
983 uint32_t, (_eqp)->eq_u32[1], \
984 uint32_t, (_eqp)->eq_u32[0]); \
985 _NOTE(CONSTANTCONDITION) \
988 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
990 EFX_CHECK_REG((_enp), (_reg)); \
991 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
992 uint32_t, (_index), \
993 uint32_t, _reg ## _OFST, \
994 uint32_t, (_eqp)->eq_u32[1], \
995 uint32_t, (_eqp)->eq_u32[0]); \
996 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
997 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
999 _NOTE(CONSTANTCONDITION) \
1002 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1004 EFX_CHECK_REG((_enp), (_reg)); \
1005 EFSYS_BAR_READO((_enp)->en_esbp, \
1006 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1008 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1009 uint32_t, (_index), \
1010 uint32_t, _reg ## _OFST, \
1011 uint32_t, (_eop)->eo_u32[3], \
1012 uint32_t, (_eop)->eo_u32[2], \
1013 uint32_t, (_eop)->eo_u32[1], \
1014 uint32_t, (_eop)->eo_u32[0]); \
1015 _NOTE(CONSTANTCONDITION) \
1018 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1020 EFX_CHECK_REG((_enp), (_reg)); \
1021 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1022 uint32_t, (_index), \
1023 uint32_t, _reg ## _OFST, \
1024 uint32_t, (_eop)->eo_u32[3], \
1025 uint32_t, (_eop)->eo_u32[2], \
1026 uint32_t, (_eop)->eo_u32[1], \
1027 uint32_t, (_eop)->eo_u32[0]); \
1028 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1029 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1031 _NOTE(CONSTANTCONDITION) \
1035 * Allow drivers to perform optimised 128-bit doorbell writes.
1036 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1037 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1038 * the need for locking in the host, and are the only ones known to be safe to
1039 * use 128-bites write with.
1041 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1043 EFX_CHECK_REG((_enp), (_reg)); \
1044 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1045 const char *, #_reg, \
1046 uint32_t, (_index), \
1047 uint32_t, _reg ## _OFST, \
1048 uint32_t, (_eop)->eo_u32[3], \
1049 uint32_t, (_eop)->eo_u32[2], \
1050 uint32_t, (_eop)->eo_u32[1], \
1051 uint32_t, (_eop)->eo_u32[0]); \
1052 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1053 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1055 _NOTE(CONSTANTCONDITION) \
1058 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1060 unsigned int _new = (_wptr); \
1061 unsigned int _old = (_owptr); \
1063 if ((_new) >= (_old)) \
1064 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1065 (_old) * sizeof (efx_desc_t), \
1066 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1069 * It is cheaper to sync entire map than sync \
1070 * two parts especially when offset/size are \
1071 * ignored and entire map is synced in any case.\
1073 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1075 (_entries) * sizeof (efx_desc_t)); \
1076 _NOTE(CONSTANTCONDITION) \
1079 extern __checkReturn efx_rc_t
1081 __in efx_nic_t *enp);
1084 efx_mac_multicast_hash_compute(
1085 __in_ecount(6*count) uint8_t const *addrs,
1087 __out efx_oword_t *hash_low,
1088 __out efx_oword_t *hash_high);
1090 extern __checkReturn efx_rc_t
1092 __in efx_nic_t *enp);
1096 __in efx_nic_t *enp);
1100 /* VPD utility functions */
1102 extern __checkReturn efx_rc_t
1103 efx_vpd_hunk_length(
1104 __in_bcount(size) caddr_t data,
1106 __out size_t *lengthp);
1108 extern __checkReturn efx_rc_t
1109 efx_vpd_hunk_verify(
1110 __in_bcount(size) caddr_t data,
1112 __out_opt boolean_t *cksummedp);
1114 extern __checkReturn efx_rc_t
1115 efx_vpd_hunk_reinit(
1116 __in_bcount(size) caddr_t data,
1118 __in boolean_t wantpid);
1120 extern __checkReturn efx_rc_t
1122 __in_bcount(size) caddr_t data,
1124 __in efx_vpd_tag_t tag,
1125 __in efx_vpd_keyword_t keyword,
1126 __out unsigned int *payloadp,
1127 __out uint8_t *paylenp);
1129 extern __checkReturn efx_rc_t
1131 __in_bcount(size) caddr_t data,
1133 __out efx_vpd_tag_t *tagp,
1134 __out efx_vpd_keyword_t *keyword,
1135 __out_opt unsigned int *payloadp,
1136 __out_opt uint8_t *paylenp,
1137 __inout unsigned int *contp);
1139 extern __checkReturn efx_rc_t
1141 __in_bcount(size) caddr_t data,
1143 __in efx_vpd_value_t *evvp);
1145 #endif /* EFSYS_OPT_VPD */
1149 extern __checkReturn efx_rc_t
1150 efx_mcdi_set_workaround(
1151 __in efx_nic_t *enp,
1153 __in boolean_t enabled,
1154 __out_opt uint32_t *flagsp);
1156 extern __checkReturn efx_rc_t
1157 efx_mcdi_get_workarounds(
1158 __in efx_nic_t *enp,
1159 __out_opt uint32_t *implementedp,
1160 __out_opt uint32_t *enabledp);
1162 #endif /* EFSYS_OPT_MCDI */
1164 #if EFSYS_OPT_MAC_STATS
1167 * Closed range of stats (i.e. the first and the last are included).
1168 * The last must be greater or equal (if the range is one item only) to
1171 struct efx_mac_stats_range {
1172 efx_mac_stat_t first;
1173 efx_mac_stat_t last;
1177 efx_mac_stats_mask_add_ranges(
1178 __inout_bcount(mask_size) uint32_t *maskp,
1179 __in size_t mask_size,
1180 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1181 __in unsigned int rng_count);
1183 #endif /* EFSYS_OPT_MAC_STATS */
1189 #endif /* _SYS_EFX_IMPL_H */