drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #if EFSYS_OPT_MCDI
  14 #include "efx_mcdi.h"
  15 #endif  /* EFSYS_OPT_MCDI */
  16
  17 /* FIXME: Add definition for driver generated software events */
  18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  20 #endif
  21
  22
  23 #if EFSYS_OPT_SIENA
  24 #include "siena_impl.h"
  25 #endif  /* EFSYS_OPT_SIENA */
  26
  27 #if EFSYS_OPT_HUNTINGTON
  28 #include "hunt_impl.h"
  29 #endif  /* EFSYS_OPT_HUNTINGTON */
  30
  31 #if EFSYS_OPT_MEDFORD
  32 #include "medford_impl.h"
  33 #endif  /* EFSYS_OPT_MEDFORD */
  34
  35 #if EFSYS_OPT_MEDFORD2
  36 #include "medford2_impl.h"
  37 #endif  /* EFSYS_OPT_MEDFORD2 */
  38
  39 #if EFX_OPTS_EF10()
  40 #include "ef10_impl.h"
  41 #endif  /* EFX_OPTS_EF10() */
  42
  43 #ifdef  __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define EFX_MOD_MCDI            0x00000001
  48 #define EFX_MOD_PROBE           0x00000002
  49 #define EFX_MOD_NVRAM           0x00000004
  50 #define EFX_MOD_VPD             0x00000008
  51 #define EFX_MOD_NIC             0x00000010
  52 #define EFX_MOD_INTR            0x00000020
  53 #define EFX_MOD_EV              0x00000040
  54 #define EFX_MOD_RX              0x00000080
  55 #define EFX_MOD_TX              0x00000100
  56 #define EFX_MOD_PORT            0x00000200
  57 #define EFX_MOD_MON             0x00000400
  58 #define EFX_MOD_FILTER          0x00001000
  59 #define EFX_MOD_LIC             0x00002000
  60 #define EFX_MOD_TUNNEL          0x00004000
  61 #define EFX_MOD_EVB             0x00008000
  62
  63 #define EFX_RESET_PHY           0x00000001
  64 #define EFX_RESET_RXQ_ERR       0x00000002
  65 #define EFX_RESET_TXQ_ERR       0x00000004
  66 #define EFX_RESET_HW_UNAVAIL    0x00000008
  67
  68 typedef enum efx_mac_type_e {
  69         EFX_MAC_INVALID = 0,
  70         EFX_MAC_SIENA,
  71         EFX_MAC_HUNTINGTON,
  72         EFX_MAC_MEDFORD,
  73         EFX_MAC_MEDFORD2,
  74         EFX_MAC_NTYPES
  75 } efx_mac_type_t;
  76
  77 typedef struct efx_ev_ops_s {
  78         efx_rc_t        (*eevo_init)(efx_nic_t *);
  79         void            (*eevo_fini)(efx_nic_t *);
  80         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  81                                           efsys_mem_t *, size_t, uint32_t,
  82                                           uint32_t, uint32_t, efx_evq_t *);
  83         void            (*eevo_qdestroy)(efx_evq_t *);
  84         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  85         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  86         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  87 #if EFSYS_OPT_QSTATS
  88         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  89 #endif
  90 } efx_ev_ops_t;
  91
  92 typedef struct efx_tx_ops_s {
  93         efx_rc_t        (*etxo_init)(efx_nic_t *);
  94         void            (*etxo_fini)(efx_nic_t *);
  95         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  96                                         unsigned int, unsigned int,
  97                                         efsys_mem_t *, size_t,
  98                                         uint32_t, uint16_t,
  99                                         efx_evq_t *, efx_txq_t *,
 100                                         unsigned int *);
 101         void            (*etxo_qdestroy)(efx_txq_t *);
 102         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 103                                       unsigned int, unsigned int,
 104                                       unsigned int *);
 105         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 106         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 107         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 108         void            (*etxo_qenable)(efx_txq_t *);
 109         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 110         void            (*etxo_qpio_disable)(efx_txq_t *);
 111         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 112                                            size_t);
 113         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 114                                            unsigned int *);
 115         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 119                                                 size_t, boolean_t,
 120                                                 efx_desc_t *);
 121         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 122                                                 uint32_t, uint8_t,
 123                                                 efx_desc_t *);
 124         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 125                                                 uint16_t, uint32_t, uint16_t,
 126                                                 efx_desc_t *, int);
 127         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 128                                                 efx_desc_t *);
 129         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 130                                                 efx_desc_t *);
 131 #if EFSYS_OPT_QSTATS
 132         void            (*etxo_qstats_update)(efx_txq_t *,
 133                                               efsys_stat_t *);
 134 #endif
 135 } efx_tx_ops_t;
 136
 137 typedef union efx_rxq_type_data_u {
 138         struct {
 139                 size_t          ed_buf_size;
 140         } ertd_default;
 141 #if EFSYS_OPT_RX_PACKED_STREAM
 142         struct {
 143                 uint32_t        eps_buf_size;
 144         } ertd_packed_stream;
 145 #endif
 146 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 147         struct {
 148                 uint32_t        eessb_bufs_per_desc;
 149                 uint32_t        eessb_max_dma_len;
 150                 uint32_t        eessb_buf_stride;
 151                 uint32_t        eessb_hol_block_timeout;
 152         } ertd_es_super_buffer;
 153 #endif
 154 } efx_rxq_type_data_t;
 155
 156 typedef struct efx_rx_ops_s {
 157         efx_rc_t        (*erxo_init)(efx_nic_t *);
 158         void            (*erxo_fini)(efx_nic_t *);
 159 #if EFSYS_OPT_RX_SCATTER
 160         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 161 #endif
 162 #if EFSYS_OPT_RX_SCALE
 163         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 164                                                     efx_rx_scale_context_type_t,
 165                                                     uint32_t, uint32_t *);
 166         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 167         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 168                                                efx_rx_hash_alg_t,
 169                                                efx_rx_hash_type_t, boolean_t);
 170         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 171                                               uint8_t *, size_t);
 172         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 173                                               unsigned int *, size_t);
 174         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 175                                             uint8_t *);
 176 #endif /* EFSYS_OPT_RX_SCALE */
 177         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 178                                               uint16_t *);
 179         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 180                                       unsigned int, unsigned int,
 181                                       unsigned int);
 182         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 183 #if EFSYS_OPT_RX_PACKED_STREAM
 184         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 185         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 186                                                 uint32_t, uint32_t,
 187                                                 uint16_t *, uint32_t *, uint32_t *);
 188 #endif
 189         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 190         void            (*erxo_qenable)(efx_rxq_t *);
 191         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 192                                         unsigned int, efx_rxq_type_t,
 193                                         const efx_rxq_type_data_t *,
 194                                         efsys_mem_t *, size_t, uint32_t,
 195                                         unsigned int,
 196                                         efx_evq_t *, efx_rxq_t *);
 197         void            (*erxo_qdestroy)(efx_rxq_t *);
 198 } efx_rx_ops_t;
 199
 200 typedef struct efx_mac_ops_s {
 201         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 202         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 203         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 204         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 205         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 206         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 207         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 208         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 209                                                       efx_rxq_t *, boolean_t);
 210         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 211 #if EFSYS_OPT_LOOPBACK
 212         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 213                                             efx_loopback_type_t);
 214 #endif  /* EFSYS_OPT_LOOPBACK */
 215 #if EFSYS_OPT_MAC_STATS
 216         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 217         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 218         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 219         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 220                                               uint16_t, boolean_t);
 221         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 222                                             efsys_stat_t *, uint32_t *);
 223 #endif  /* EFSYS_OPT_MAC_STATS */
 224 } efx_mac_ops_t;
 225
 226 typedef struct efx_phy_ops_s {
 227         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 228         efx_rc_t        (*epo_reset)(efx_nic_t *);
 229         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 230         efx_rc_t        (*epo_verify)(efx_nic_t *);
 231         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 232         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 233 #if EFSYS_OPT_PHY_STATS
 234         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 235                                             uint32_t *);
 236 #endif  /* EFSYS_OPT_PHY_STATS */
 237 #if EFSYS_OPT_BIST
 238         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 239         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 240         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 241                                          efx_bist_result_t *, uint32_t *,
 242                                          unsigned long *, size_t);
 243         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 244 #endif  /* EFSYS_OPT_BIST */
 245 } efx_phy_ops_t;
 246
 247 #if EFSYS_OPT_FILTER
 248 typedef struct efx_filter_ops_s {
 249         efx_rc_t        (*efo_init)(efx_nic_t *);
 250         void            (*efo_fini)(efx_nic_t *);
 251         efx_rc_t        (*efo_restore)(efx_nic_t *);
 252         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 253                                    boolean_t may_replace);
 254         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 255         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 256                                    size_t, size_t *);
 257         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 258                                    boolean_t, boolean_t, boolean_t,
 259                                    uint8_t const *, uint32_t);
 260 } efx_filter_ops_t;
 261
 262 extern  __checkReturn   efx_rc_t
 263 efx_filter_reconfigure(
 264         __in                            efx_nic_t *enp,
 265         __in_ecount(6)                  uint8_t const *mac_addr,
 266         __in                            boolean_t all_unicst,
 267         __in                            boolean_t mulcst,
 268         __in                            boolean_t all_mulcst,
 269         __in                            boolean_t brdcst,
 270         __in_ecount(6*count)            uint8_t const *addrs,
 271         __in                            uint32_t count);
 272
 273 #endif /* EFSYS_OPT_FILTER */
 274
 275 #if EFSYS_OPT_TUNNEL
 276 typedef struct efx_tunnel_ops_s {
 277         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 278         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 279 } efx_tunnel_ops_t;
 280 #endif /* EFSYS_OPT_TUNNEL */
 281
 282 typedef struct efx_port_s {
 283         efx_mac_type_t          ep_mac_type;
 284         uint32_t                ep_phy_type;
 285         uint8_t                 ep_port;
 286         uint32_t                ep_mac_pdu;
 287         uint8_t                 ep_mac_addr[6];
 288         efx_link_mode_t         ep_link_mode;
 289         boolean_t               ep_all_unicst;
 290         boolean_t               ep_mulcst;
 291         boolean_t               ep_all_mulcst;
 292         boolean_t               ep_brdcst;
 293         unsigned int            ep_fcntl;
 294         boolean_t               ep_fcntl_autoneg;
 295         efx_oword_t             ep_multicst_hash[2];
 296         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 297                                                     EFX_MAC_MULTICAST_LIST_MAX];
 298         uint32_t                ep_mulcst_addr_count;
 299 #if EFSYS_OPT_LOOPBACK
 300         efx_loopback_type_t     ep_loopback_type;
 301         efx_link_mode_t         ep_loopback_link_mode;
 302 #endif  /* EFSYS_OPT_LOOPBACK */
 303 #if EFSYS_OPT_PHY_FLAGS
 304         uint32_t                ep_phy_flags;
 305 #endif  /* EFSYS_OPT_PHY_FLAGS */
 306 #if EFSYS_OPT_PHY_LED_CONTROL
 307         efx_phy_led_mode_t      ep_phy_led_mode;
 308 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 309         efx_phy_media_type_t    ep_fixed_port_type;
 310         efx_phy_media_type_t    ep_module_type;
 311         uint32_t                ep_adv_cap_mask;
 312         uint32_t                ep_lp_cap_mask;
 313         uint32_t                ep_default_adv_cap_mask;
 314         uint32_t                ep_phy_cap_mask;
 315         boolean_t               ep_mac_drain;
 316 #if EFSYS_OPT_BIST
 317         efx_bist_type_t         ep_current_bist;
 318 #endif
 319         const efx_mac_ops_t     *ep_emop;
 320         const efx_phy_ops_t     *ep_epop;
 321 } efx_port_t;
 322
 323 typedef struct efx_mon_ops_s {
 324 #if EFSYS_OPT_MON_STATS
 325         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 326                                             efx_mon_stat_value_t *);
 327         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 328                                              efx_mon_stat_limits_t *);
 329 #endif  /* EFSYS_OPT_MON_STATS */
 330 } efx_mon_ops_t;
 331
 332 typedef struct efx_mon_s {
 333         efx_mon_type_t          em_type;
 334         const efx_mon_ops_t     *em_emop;
 335 } efx_mon_t;
 336
 337 typedef struct efx_intr_ops_s {
 338         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 339         void            (*eio_enable)(efx_nic_t *);
 340         void            (*eio_disable)(efx_nic_t *);
 341         void            (*eio_disable_unlocked)(efx_nic_t *);
 342         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 343         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 344         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 345                                  boolean_t *);
 346         void            (*eio_fatal)(efx_nic_t *);
 347         void            (*eio_fini)(efx_nic_t *);
 348 } efx_intr_ops_t;
 349
 350 typedef struct efx_intr_s {
 351         const efx_intr_ops_t    *ei_eiop;
 352         efsys_mem_t             *ei_esmp;
 353         efx_intr_type_t         ei_type;
 354         unsigned int            ei_level;
 355 } efx_intr_t;
 356
 357 typedef struct efx_nic_ops_s {
 358         efx_rc_t        (*eno_probe)(efx_nic_t *);
 359         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 360         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 361         efx_rc_t        (*eno_reset)(efx_nic_t *);
 362         efx_rc_t        (*eno_init)(efx_nic_t *);
 363         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 364         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 365                                         uint32_t *, size_t *);
 366         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 367         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 368 #if EFSYS_OPT_DIAG
 369         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 370 #endif  /* EFSYS_OPT_DIAG */
 371         void            (*eno_fini)(efx_nic_t *);
 372         void            (*eno_unprobe)(efx_nic_t *);
 373 } efx_nic_ops_t;
 374
 375 #ifndef EFX_TXQ_LIMIT_TARGET
 376 #define EFX_TXQ_LIMIT_TARGET 259
 377 #endif
 378 #ifndef EFX_RXQ_LIMIT_TARGET
 379 #define EFX_RXQ_LIMIT_TARGET 512
 380 #endif
 381
 382
 383 #if EFSYS_OPT_FILTER
 384
 385 #if EFSYS_OPT_SIENA
 386
 387 typedef struct siena_filter_spec_s {
 388         uint8_t         sfs_type;
 389         uint32_t        sfs_flags;
 390         uint32_t        sfs_dmaq_id;
 391         uint32_t        sfs_dword[3];
 392 } siena_filter_spec_t;
 393
 394 typedef enum siena_filter_type_e {
 395         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 396         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 397         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 398         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 399         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 400         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 401
 402         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 403         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 404         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 405         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 406         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 407         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 408
 409         EFX_SIENA_FILTER_NTYPES
 410 } siena_filter_type_t;
 411
 412 typedef enum siena_filter_tbl_id_e {
 413         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 414         EFX_SIENA_FILTER_TBL_RX_MAC,
 415         EFX_SIENA_FILTER_TBL_TX_IP,
 416         EFX_SIENA_FILTER_TBL_TX_MAC,
 417         EFX_SIENA_FILTER_NTBLS
 418 } siena_filter_tbl_id_t;
 419
 420 typedef struct siena_filter_tbl_s {
 421         int                     sft_size;       /* number of entries */
 422         int                     sft_used;       /* active count */
 423         uint32_t                *sft_bitmap;    /* active bitmap */
 424         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 425 } siena_filter_tbl_t;
 426
 427 typedef struct siena_filter_s {
 428         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 429         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 430 } siena_filter_t;
 431
 432 #endif  /* EFSYS_OPT_SIENA */
 433
 434 typedef struct efx_filter_s {
 435 #if EFSYS_OPT_SIENA
 436         siena_filter_t          *ef_siena_filter;
 437 #endif /* EFSYS_OPT_SIENA */
 438 #if EFX_OPTS_EF10()
 439         ef10_filter_table_t     *ef_ef10_filter_table;
 440 #endif /* EFX_OPTS_EF10() */
 441 } efx_filter_t;
 442
 443 #if EFSYS_OPT_SIENA
 444
 445 extern                  void
 446 siena_filter_tbl_clear(
 447         __in            efx_nic_t *enp,
 448         __in            siena_filter_tbl_id_t tbl);
 449
 450 #endif  /* EFSYS_OPT_SIENA */
 451
 452 #endif  /* EFSYS_OPT_FILTER */
 453
 454 #if EFSYS_OPT_MCDI
 455
 456 #define EFX_TUNNEL_MAXNENTRIES  (16)
 457
 458 #if EFSYS_OPT_TUNNEL
 459
 460 typedef struct efx_tunnel_udp_entry_s {
 461         uint16_t                        etue_port; /* host/cpu-endian */
 462         uint16_t                        etue_protocol;
 463 } efx_tunnel_udp_entry_t;
 464
 465 typedef struct efx_tunnel_cfg_s {
 466         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 467         unsigned int            etc_udp_entries_num;
 468 } efx_tunnel_cfg_t;
 469
 470 #endif /* EFSYS_OPT_TUNNEL */
 471
 472 typedef struct efx_mcdi_ops_s {
 473         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 474         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 475                                         void *, size_t);
 476         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 477         boolean_t       (*emco_poll_response)(efx_nic_t *);
 478         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 479         void            (*emco_fini)(efx_nic_t *);
 480         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 481                                             efx_mcdi_feature_id_t, boolean_t *);
 482         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 483                                             uint32_t *);
 484 } efx_mcdi_ops_t;
 485
 486 typedef struct efx_mcdi_s {
 487         const efx_mcdi_ops_t            *em_emcop;
 488         const efx_mcdi_transport_t      *em_emtp;
 489         efx_mcdi_iface_t                em_emip;
 490 } efx_mcdi_t;
 491
 492 #endif /* EFSYS_OPT_MCDI */
 493
 494 #if EFSYS_OPT_NVRAM
 495
 496 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 497 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 498
 499 typedef struct efx_nvram_ops_s {
 500 #if EFSYS_OPT_DIAG
 501         efx_rc_t        (*envo_test)(efx_nic_t *);
 502 #endif  /* EFSYS_OPT_DIAG */
 503         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 504                                             uint32_t *);
 505         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 506                                             efx_nvram_info_t *);
 507         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 508         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 509                                             unsigned int, caddr_t, size_t);
 510         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 511                                             unsigned int, caddr_t, size_t);
 512         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 513                                             unsigned int, size_t);
 514         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 515                                             unsigned int, caddr_t, size_t);
 516         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 517                                             uint32_t *);
 518         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 519                                             uint32_t *, uint16_t *);
 520         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 521                                             uint16_t *);
 522         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 523                                             caddr_t, size_t);
 524 } efx_nvram_ops_t;
 525 #endif /* EFSYS_OPT_NVRAM */
 526
 527 #if EFSYS_OPT_VPD
 528 typedef struct efx_vpd_ops_s {
 529         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 530         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 531         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 532         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 533         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 534         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 535                                         efx_vpd_value_t *);
 536         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 537                                         efx_vpd_value_t *);
 538         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 539                                         efx_vpd_value_t *, unsigned int *);
 540         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 541         void            (*evpdo_fini)(efx_nic_t *);
 542 } efx_vpd_ops_t;
 543 #endif  /* EFSYS_OPT_VPD */
 544
 545 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 546
 547         __checkReturn           efx_rc_t
 548 efx_mcdi_nvram_partitions(
 549         __in                    efx_nic_t *enp,
 550         __out_bcount(size)      caddr_t data,
 551         __in                    size_t size,
 552         __out                   unsigned int *npartnp);
 553
 554         __checkReturn           efx_rc_t
 555 efx_mcdi_nvram_metadata(
 556         __in                    efx_nic_t *enp,
 557         __in                    uint32_t partn,
 558         __out                   uint32_t *subtypep,
 559         __out_ecount(4)         uint16_t version[4],
 560         __out_bcount_opt(size)  char *descp,
 561         __in                    size_t size);
 562
 563         __checkReturn           efx_rc_t
 564 efx_mcdi_nvram_info(
 565         __in                    efx_nic_t *enp,
 566         __in                    uint32_t partn,
 567         __out                   efx_nvram_info_t *eni);
 568
 569         __checkReturn           efx_rc_t
 570 efx_mcdi_nvram_update_start(
 571         __in                    efx_nic_t *enp,
 572         __in                    uint32_t partn);
 573
 574         __checkReturn           efx_rc_t
 575 efx_mcdi_nvram_read(
 576         __in                    efx_nic_t *enp,
 577         __in                    uint32_t partn,
 578         __in                    uint32_t offset,
 579         __out_bcount(size)      caddr_t data,
 580         __in                    size_t size,
 581         __in                    uint32_t mode);
 582
 583         __checkReturn           efx_rc_t
 584 efx_mcdi_nvram_erase(
 585         __in                    efx_nic_t *enp,
 586         __in                    uint32_t partn,
 587         __in                    uint32_t offset,
 588         __in                    size_t size);
 589
 590         __checkReturn           efx_rc_t
 591 efx_mcdi_nvram_write(
 592         __in                    efx_nic_t *enp,
 593         __in                    uint32_t partn,
 594         __in                    uint32_t offset,
 595         __in_bcount(size)       caddr_t data,
 596         __in                    size_t size);
 597
 598 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 599 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 600
 601         __checkReturn           efx_rc_t
 602 efx_mcdi_nvram_update_finish(
 603         __in                    efx_nic_t *enp,
 604         __in                    uint32_t partn,
 605         __in                    boolean_t reboot,
 606         __in                    uint32_t flags,
 607         __out_opt               uint32_t *verify_resultp);
 608
 609 #if EFSYS_OPT_DIAG
 610
 611         __checkReturn           efx_rc_t
 612 efx_mcdi_nvram_test(
 613         __in                    efx_nic_t *enp,
 614         __in                    uint32_t partn);
 615
 616 #endif  /* EFSYS_OPT_DIAG */
 617
 618 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 619
 620 #if EFSYS_OPT_LICENSING
 621
 622 typedef struct efx_lic_ops_s {
 623         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 624         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 625         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 626         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 627                                       size_t *, uint8_t *);
 628         efx_rc_t        (*elo_find_start)
 629                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 630         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 631                                 uint32_t, uint32_t *);
 632         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 633                                 uint32_t, uint32_t *, uint32_t *);
 634         boolean_t       (*elo_validate_key)(efx_nic_t *,
 635                                 caddr_t, uint32_t);
 636         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 637                                 caddr_t, size_t, uint32_t, uint32_t,
 638                                 caddr_t, size_t, uint32_t *);
 639         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 640                                 caddr_t, size_t, uint32_t,
 641                                 caddr_t, uint32_t, uint32_t *);
 642         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 643                                 caddr_t, size_t, uint32_t,
 644                                 uint32_t, uint32_t, uint32_t *);
 645         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 646                                 caddr_t, size_t);
 647         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 648                                 caddr_t, size_t);
 649 } efx_lic_ops_t;
 650
 651 #endif
 652
 653 #if EFSYS_OPT_EVB
 654
 655 typedef struct efx_evb_ops_s {
 656         efx_rc_t        (*eeo_init)(efx_nic_t *);
 657         void            (*eeo_fini)(efx_nic_t *);
 658         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 659         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 660         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 661                                                 efx_vport_type_t, uint16_t,
 662                                                 boolean_t, efx_vport_id_t *);
 663         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 664                                                 efx_vport_id_t);
 665         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 666                                                 efx_vport_id_t, uint8_t *);
 667         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 668                                                 efx_vport_id_t, uint8_t *);
 669         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 670                                                 efx_vport_id_t);
 671         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 672                                                 efx_vport_id_t);
 673         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 674                                                 efx_vport_id_t, uint32_t);
 675 } efx_evb_ops_t;
 676
 677 #endif /* EFSYS_OPT_EVB */
 678
 679 #define EFX_DRV_VER_MAX         20
 680
 681 typedef struct efx_drv_cfg_s {
 682         uint32_t                edc_min_vi_count;
 683         uint32_t                edc_max_vi_count;
 684
 685         uint32_t                edc_max_piobuf_count;
 686         uint32_t                edc_pio_alloc_size;
 687 } efx_drv_cfg_t;
 688
 689 struct efx_nic_s {
 690         uint32_t                en_magic;
 691         efx_family_t            en_family;
 692         uint32_t                en_features;
 693         efsys_identifier_t      *en_esip;
 694         efsys_lock_t            *en_eslp;
 695         efsys_bar_t             *en_esbp;
 696         unsigned int            en_mod_flags;
 697         unsigned int            en_reset_flags;
 698         efx_nic_cfg_t           en_nic_cfg;
 699         efx_drv_cfg_t           en_drv_cfg;
 700         efx_port_t              en_port;
 701         efx_mon_t               en_mon;
 702         efx_intr_t              en_intr;
 703         uint32_t                en_ev_qcount;
 704         uint32_t                en_rx_qcount;
 705         uint32_t                en_tx_qcount;
 706         const efx_nic_ops_t     *en_enop;
 707         const efx_ev_ops_t      *en_eevop;
 708         const efx_tx_ops_t      *en_etxop;
 709         const efx_rx_ops_t      *en_erxop;
 710         efx_fw_variant_t        efv;
 711         char                    en_drv_version[EFX_DRV_VER_MAX];
 712 #if EFSYS_OPT_FILTER
 713         efx_filter_t            en_filter;
 714         const efx_filter_ops_t  *en_efop;
 715 #endif  /* EFSYS_OPT_FILTER */
 716 #if EFSYS_OPT_TUNNEL
 717         efx_tunnel_cfg_t        en_tunnel_cfg;
 718         const efx_tunnel_ops_t  *en_etop;
 719 #endif /* EFSYS_OPT_TUNNEL */
 720 #if EFSYS_OPT_MCDI
 721         efx_mcdi_t              en_mcdi;
 722 #endif  /* EFSYS_OPT_MCDI */
 723 #if EFSYS_OPT_NVRAM
 724         uint32_t                en_nvram_partn_locked;
 725         const efx_nvram_ops_t   *en_envop;
 726 #endif  /* EFSYS_OPT_NVRAM */
 727 #if EFSYS_OPT_VPD
 728         const efx_vpd_ops_t     *en_evpdop;
 729 #endif  /* EFSYS_OPT_VPD */
 730 #if EFSYS_OPT_RX_SCALE
 731         efx_rx_hash_support_t           en_hash_support;
 732         efx_rx_scale_context_type_t     en_rss_context_type;
 733         uint32_t                        en_rss_context;
 734 #endif  /* EFSYS_OPT_RX_SCALE */
 735         uint32_t                en_vport_id;
 736 #if EFSYS_OPT_LICENSING
 737         const efx_lic_ops_t     *en_elop;
 738         boolean_t               en_licensing_supported;
 739 #endif
 740         union {
 741 #if EFSYS_OPT_SIENA
 742                 struct {
 743 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 744                         unsigned int            enu_partn_mask;
 745 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 746 #if EFSYS_OPT_VPD
 747                         caddr_t                 enu_svpd;
 748                         size_t                  enu_svpd_length;
 749 #endif  /* EFSYS_OPT_VPD */
 750                         int                     enu_unused;
 751                 } siena;
 752 #endif  /* EFSYS_OPT_SIENA */
 753                 int     enu_unused;
 754         } en_u;
 755 #if EFX_OPTS_EF10()
 756         union en_arch {
 757                 struct {
 758                         int                     ena_vi_base;
 759                         int                     ena_vi_count;
 760                         int                     ena_vi_shift;
 761 #if EFSYS_OPT_VPD
 762                         caddr_t                 ena_svpd;
 763                         size_t                  ena_svpd_length;
 764 #endif  /* EFSYS_OPT_VPD */
 765                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 766                         uint32_t                ena_piobuf_count;
 767                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 768                         uint32_t                ena_pio_write_vi_base;
 769                         /* Memory BAR mapping regions */
 770                         uint32_t                ena_uc_mem_map_offset;
 771                         size_t                  ena_uc_mem_map_size;
 772                         uint32_t                ena_wc_mem_map_offset;
 773                         size_t                  ena_wc_mem_map_size;
 774                 } ef10;
 775         } en_arch;
 776 #endif  /* EFX_OPTS_EF10() */
 777 #if EFSYS_OPT_EVB
 778         const efx_evb_ops_t     *en_eeop;
 779 #endif  /* EFSYS_OPT_EVB */
 780 };
 781
 782 #define EFX_FAMILY_IS_EF10(_enp) \
 783         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 784          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 785          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 786
 787
 788 #define EFX_NIC_MAGIC   0x02121996
 789
 790 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 791     const efx_ev_callbacks_t *, void *);
 792
 793 typedef struct efx_evq_rxq_state_s {
 794         unsigned int                    eers_rx_read_ptr;
 795         unsigned int                    eers_rx_mask;
 796 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 797         unsigned int                    eers_rx_stream_npackets;
 798         boolean_t                       eers_rx_packed_stream;
 799 #endif
 800 #if EFSYS_OPT_RX_PACKED_STREAM
 801         unsigned int                    eers_rx_packed_stream_credits;
 802 #endif
 803 } efx_evq_rxq_state_t;
 804
 805 struct efx_evq_s {
 806         uint32_t                        ee_magic;
 807         uint32_t                        ee_flags;
 808         efx_nic_t                       *ee_enp;
 809         unsigned int                    ee_index;
 810         unsigned int                    ee_mask;
 811         efsys_mem_t                     *ee_esmp;
 812 #if EFSYS_OPT_QSTATS
 813         uint32_t                        ee_stat[EV_NQSTATS];
 814 #endif  /* EFSYS_OPT_QSTATS */
 815
 816         efx_ev_handler_t                ee_rx;
 817         efx_ev_handler_t                ee_tx;
 818         efx_ev_handler_t                ee_driver;
 819         efx_ev_handler_t                ee_global;
 820         efx_ev_handler_t                ee_drv_gen;
 821 #if EFSYS_OPT_MCDI
 822         efx_ev_handler_t                ee_mcdi;
 823 #endif  /* EFSYS_OPT_MCDI */
 824
 825         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 826 };
 827
 828 #define EFX_EVQ_MAGIC   0x08081997
 829
 830 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 831
 832 #if EFSYS_OPT_QSTATS
 833 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
 834         do {                                                            \
 835                 (_eep)->ee_stat[_stat]++;                               \
 836         _NOTE(CONSTANTCONDITION)                                        \
 837         } while (B_FALSE)
 838 #else
 839 #define EFX_EV_QSTAT_INCR(_eep, _stat)
 840 #endif
 841
 842 struct efx_rxq_s {
 843         uint32_t                        er_magic;
 844         efx_nic_t                       *er_enp;
 845         efx_evq_t                       *er_eep;
 846         unsigned int                    er_index;
 847         unsigned int                    er_label;
 848         unsigned int                    er_mask;
 849         size_t                          er_buf_size;
 850         efsys_mem_t                     *er_esmp;
 851         efx_evq_rxq_state_t             *er_ev_qstate;
 852 };
 853
 854 #define EFX_RXQ_MAGIC   0x15022005
 855
 856 struct efx_txq_s {
 857         uint32_t                        et_magic;
 858         efx_nic_t                       *et_enp;
 859         unsigned int                    et_index;
 860         unsigned int                    et_mask;
 861         efsys_mem_t                     *et_esmp;
 862 #if EFSYS_OPT_HUNTINGTON
 863         uint32_t                        et_pio_bufnum;
 864         uint32_t                        et_pio_blknum;
 865         uint32_t                        et_pio_write_offset;
 866         uint32_t                        et_pio_offset;
 867         size_t                          et_pio_size;
 868 #endif
 869 #if EFSYS_OPT_QSTATS
 870         uint32_t                        et_stat[TX_NQSTATS];
 871 #endif  /* EFSYS_OPT_QSTATS */
 872 };
 873
 874 #define EFX_TXQ_MAGIC   0x05092005
 875
 876 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 877         do {                                                            \
 878                 (_dst)[0] = (_src)[0];                                  \
 879                 (_dst)[1] = (_src)[1];                                  \
 880                 (_dst)[2] = (_src)[2];                                  \
 881                 (_dst)[3] = (_src)[3];                                  \
 882                 (_dst)[4] = (_src)[4];                                  \
 883                 (_dst)[5] = (_src)[5];                                  \
 884         _NOTE(CONSTANTCONDITION)                                        \
 885         } while (B_FALSE)
 886
 887 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 888         do {                                                            \
 889                 uint16_t *_d = (uint16_t *)(_dst);                      \
 890                 _d[0] = 0xffff;                                         \
 891                 _d[1] = 0xffff;                                         \
 892                 _d[2] = 0xffff;                                         \
 893         _NOTE(CONSTANTCONDITION)                                        \
 894         } while (B_FALSE)
 895
 896 #if EFSYS_OPT_CHECK_REG
 897 #define EFX_CHECK_REG(_enp, _reg)                                       \
 898         do {                                                            \
 899                 const char *name = #_reg;                               \
 900                 char min = name[4];                                     \
 901                 char max = name[5];                                     \
 902                 char rev;                                               \
 903                                                                         \
 904                 switch ((_enp)->en_family) {                            \
 905                 case EFX_FAMILY_SIENA:                                  \
 906                         rev = 'C';                                      \
 907                         break;                                          \
 908                                                                         \
 909                 case EFX_FAMILY_HUNTINGTON:                             \
 910                         rev = 'D';                                      \
 911                         break;                                          \
 912                                                                         \
 913                 case EFX_FAMILY_MEDFORD:                                \
 914                         rev = 'E';                                      \
 915                         break;                                          \
 916                                                                         \
 917                 case EFX_FAMILY_MEDFORD2:                               \
 918                         rev = 'F';                                      \
 919                         break;                                          \
 920                                                                         \
 921                 default:                                                \
 922                         rev = '?';                                      \
 923                         break;                                          \
 924                 }                                                       \
 925                                                                         \
 926                 EFSYS_ASSERT3S(rev, >=, min);                           \
 927                 EFSYS_ASSERT3S(rev, <=, max);                           \
 928                                                                         \
 929         _NOTE(CONSTANTCONDITION)                                        \
 930         } while (B_FALSE)
 931 #else
 932 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 933         _NOTE(CONSTANTCONDITION)                                        \
 934         } while (B_FALSE)
 935 #endif
 936
 937 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 938         do {                                                            \
 939                 EFX_CHECK_REG((_enp), (_reg));                          \
 940                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 941                     (_edp), (_lock));                                   \
 942                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 943                     uint32_t, _reg ## _OFST,                            \
 944                     uint32_t, (_edp)->ed_u32[0]);                       \
 945         _NOTE(CONSTANTCONDITION)                                        \
 946         } while (B_FALSE)
 947
 948 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 949         do {                                                            \
 950                 EFX_CHECK_REG((_enp), (_reg));                          \
 951                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 952                     uint32_t, _reg ## _OFST,                            \
 953                     uint32_t, (_edp)->ed_u32[0]);                       \
 954                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 955                     (_edp), (_lock));                                   \
 956         _NOTE(CONSTANTCONDITION)                                        \
 957         } while (B_FALSE)
 958
 959 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 960         do {                                                            \
 961                 EFX_CHECK_REG((_enp), (_reg));                          \
 962                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 963                     (_eqp));                                            \
 964                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 965                     uint32_t, _reg ## _OFST,                            \
 966                     uint32_t, (_eqp)->eq_u32[1],                        \
 967                     uint32_t, (_eqp)->eq_u32[0]);                       \
 968         _NOTE(CONSTANTCONDITION)                                        \
 969         } while (B_FALSE)
 970
 971 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 972         do {                                                            \
 973                 EFX_CHECK_REG((_enp), (_reg));                          \
 974                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 975                     uint32_t, _reg ## _OFST,                            \
 976                     uint32_t, (_eqp)->eq_u32[1],                        \
 977                     uint32_t, (_eqp)->eq_u32[0]);                       \
 978                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 979                     (_eqp));                                            \
 980         _NOTE(CONSTANTCONDITION)                                        \
 981         } while (B_FALSE)
 982
 983 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 984         do {                                                            \
 985                 EFX_CHECK_REG((_enp), (_reg));                          \
 986                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 987                     (_eop), B_TRUE);                                    \
 988                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 989                     uint32_t, _reg ## _OFST,                            \
 990                     uint32_t, (_eop)->eo_u32[3],                        \
 991                     uint32_t, (_eop)->eo_u32[2],                        \
 992                     uint32_t, (_eop)->eo_u32[1],                        \
 993                     uint32_t, (_eop)->eo_u32[0]);                       \
 994         _NOTE(CONSTANTCONDITION)                                        \
 995         } while (B_FALSE)
 996
 997 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 998         do {                                                            \
 999                 EFX_CHECK_REG((_enp), (_reg));                          \
1000                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1001                     uint32_t, _reg ## _OFST,                            \
1002                     uint32_t, (_eop)->eo_u32[3],                        \
1003                     uint32_t, (_eop)->eo_u32[2],                        \
1004                     uint32_t, (_eop)->eo_u32[1],                        \
1005                     uint32_t, (_eop)->eo_u32[0]);                       \
1006                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1007                     (_eop), B_TRUE);                                    \
1008         _NOTE(CONSTANTCONDITION)                                        \
1009         } while (B_FALSE)
1010
1011 /*
1012  * Accessors for memory BAR non-VI tables.
1013  *
1014  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1015  * to ensure the correct runtime VI window size is used on Medford2.
1016  *
1017  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1018  */
1019
1020 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1021         do {                                                            \
1022                 EFX_CHECK_REG((_enp), (_reg));                          \
1023                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1024                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1025                     (_edp), (_lock));                                   \
1026                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1027                     uint32_t, (_index),                                 \
1028                     uint32_t, _reg ## _OFST,                            \
1029                     uint32_t, (_edp)->ed_u32[0]);                       \
1030         _NOTE(CONSTANTCONDITION)                                        \
1031         } while (B_FALSE)
1032
1033 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1034         do {                                                            \
1035                 EFX_CHECK_REG((_enp), (_reg));                          \
1036                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1037                     uint32_t, (_index),                                 \
1038                     uint32_t, _reg ## _OFST,                            \
1039                     uint32_t, (_edp)->ed_u32[0]);                       \
1040                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1041                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1042                     (_edp), (_lock));                                   \
1043         _NOTE(CONSTANTCONDITION)                                        \
1044         } while (B_FALSE)
1045
1046 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1047         do {                                                            \
1048                 EFX_CHECK_REG((_enp), (_reg));                          \
1049                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1050                     uint32_t, (_index),                                 \
1051                     uint32_t, _reg ## _OFST,                            \
1052                     uint32_t, (_edp)->ed_u32[0]);                       \
1053                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1054                     (_reg ## _OFST +                                    \
1055                     (3 * sizeof (efx_dword_t)) +                        \
1056                     ((_index) * _reg ## _STEP)),                        \
1057                     (_edp), (_lock));                                   \
1058         _NOTE(CONSTANTCONDITION)                                        \
1059         } while (B_FALSE)
1060
1061 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1062         do {                                                            \
1063                 EFX_CHECK_REG((_enp), (_reg));                          \
1064                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1065                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1066                     (_eqp));                                            \
1067                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1068                     uint32_t, (_index),                                 \
1069                     uint32_t, _reg ## _OFST,                            \
1070                     uint32_t, (_eqp)->eq_u32[1],                        \
1071                     uint32_t, (_eqp)->eq_u32[0]);                       \
1072         _NOTE(CONSTANTCONDITION)                                        \
1073         } while (B_FALSE)
1074
1075 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1076         do {                                                            \
1077                 EFX_CHECK_REG((_enp), (_reg));                          \
1078                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1079                     uint32_t, (_index),                                 \
1080                     uint32_t, _reg ## _OFST,                            \
1081                     uint32_t, (_eqp)->eq_u32[1],                        \
1082                     uint32_t, (_eqp)->eq_u32[0]);                       \
1083                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1084                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1085                     (_eqp));                                            \
1086         _NOTE(CONSTANTCONDITION)                                        \
1087         } while (B_FALSE)
1088
1089 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1090         do {                                                            \
1091                 EFX_CHECK_REG((_enp), (_reg));                          \
1092                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1093                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1094                     (_eop), (_lock));                                   \
1095                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1096                     uint32_t, (_index),                                 \
1097                     uint32_t, _reg ## _OFST,                            \
1098                     uint32_t, (_eop)->eo_u32[3],                        \
1099                     uint32_t, (_eop)->eo_u32[2],                        \
1100                     uint32_t, (_eop)->eo_u32[1],                        \
1101                     uint32_t, (_eop)->eo_u32[0]);                       \
1102         _NOTE(CONSTANTCONDITION)                                        \
1103         } while (B_FALSE)
1104
1105 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1106         do {                                                            \
1107                 EFX_CHECK_REG((_enp), (_reg));                          \
1108                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1109                     uint32_t, (_index),                                 \
1110                     uint32_t, _reg ## _OFST,                            \
1111                     uint32_t, (_eop)->eo_u32[3],                        \
1112                     uint32_t, (_eop)->eo_u32[2],                        \
1113                     uint32_t, (_eop)->eo_u32[1],                        \
1114                     uint32_t, (_eop)->eo_u32[0]);                       \
1115                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1116                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1117                     (_eop), (_lock));                                   \
1118         _NOTE(CONSTANTCONDITION)                                        \
1119         } while (B_FALSE)
1120
1121 /*
1122  * Accessors for memory BAR per-VI registers.
1123  *
1124  * The VI window size is 8KB for Medford and all earlier controllers.
1125  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1126  */
1127
1128 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1129         do {                                                            \
1130                 EFX_CHECK_REG((_enp), (_reg));                          \
1131                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1132                     ((_reg ## _OFST) +                                  \
1133                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1134                     (_edp), (_lock));                                   \
1135                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1136                     uint32_t, (_index),                                 \
1137                     uint32_t, _reg ## _OFST,                            \
1138                     uint32_t, (_edp)->ed_u32[0]);                       \
1139         _NOTE(CONSTANTCONDITION)                                        \
1140         } while (B_FALSE)
1141
1142 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1143         do {                                                            \
1144                 EFX_CHECK_REG((_enp), (_reg));                          \
1145                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1146                     uint32_t, (_index),                                 \
1147                     uint32_t, _reg ## _OFST,                            \
1148                     uint32_t, (_edp)->ed_u32[0]);                       \
1149                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1150                     ((_reg ## _OFST) +                                  \
1151                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1152                     (_edp), (_lock));                                   \
1153         _NOTE(CONSTANTCONDITION)                                        \
1154         } while (B_FALSE)
1155
1156 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1157         do {                                                            \
1158                 EFX_CHECK_REG((_enp), (_reg));                          \
1159                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1160                     uint32_t, (_index),                                 \
1161                     uint32_t, _reg ## _OFST,                            \
1162                     uint32_t, (_edp)->ed_u32[0]);                       \
1163                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1164                     ((_reg ## _OFST) +                                  \
1165                     (2 * sizeof (efx_dword_t)) +                        \
1166                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1167                     (_edp), (_lock));                                   \
1168         _NOTE(CONSTANTCONDITION)                                        \
1169         } while (B_FALSE)
1170
1171 /*
1172  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1173  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1174  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1175  * the need for locking in the host, and are the only ones known to be safe to
1176  * use 128-bites write with.
1177  */
1178 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1179         do {                                                            \
1180                 EFX_CHECK_REG((_enp), (_reg));                          \
1181                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1182                     const char *, #_reg,                                \
1183                     uint32_t, (_index),                                 \
1184                     uint32_t, _reg ## _OFST,                            \
1185                     uint32_t, (_eop)->eo_u32[3],                        \
1186                     uint32_t, (_eop)->eo_u32[2],                        \
1187                     uint32_t, (_eop)->eo_u32[1],                        \
1188                     uint32_t, (_eop)->eo_u32[0]);                       \
1189                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1190                     (_reg ## _OFST +                                    \
1191                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1192                     (_eop));                                            \
1193         _NOTE(CONSTANTCONDITION)                                        \
1194         } while (B_FALSE)
1195
1196 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1197         do {                                                            \
1198                 unsigned int _new = (_wptr);                            \
1199                 unsigned int _old = (_owptr);                           \
1200                                                                         \
1201                 if ((_new) >= (_old))                                   \
1202                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1203                             (_old) * sizeof (efx_desc_t),               \
1204                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1205                 else                                                    \
1206                         /*                                              \
1207                          * It is cheaper to sync entire map than sync   \
1208                          * two parts especially when offset/size are    \
1209                          * ignored and entire map is synced in any case.\
1210                          */                                             \
1211                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1212                             0,                                          \
1213                             (_entries) * sizeof (efx_desc_t));          \
1214         _NOTE(CONSTANTCONDITION)                                        \
1215         } while (B_FALSE)
1216
1217 extern  __checkReturn   efx_rc_t
1218 efx_mac_select(
1219         __in            efx_nic_t *enp);
1220
1221 extern  void
1222 efx_mac_multicast_hash_compute(
1223         __in_ecount(6*count)            uint8_t const *addrs,
1224         __in                            int count,
1225         __out                           efx_oword_t *hash_low,
1226         __out                           efx_oword_t *hash_high);
1227
1228 extern  __checkReturn   efx_rc_t
1229 efx_phy_probe(
1230         __in            efx_nic_t *enp);
1231
1232 extern                  void
1233 efx_phy_unprobe(
1234         __in            efx_nic_t *enp);
1235
1236 #if EFSYS_OPT_VPD
1237
1238 /* VPD utility functions */
1239
1240 extern  __checkReturn           efx_rc_t
1241 efx_vpd_hunk_length(
1242         __in_bcount(size)       caddr_t data,
1243         __in                    size_t size,
1244         __out                   size_t *lengthp);
1245
1246 extern  __checkReturn           efx_rc_t
1247 efx_vpd_hunk_verify(
1248         __in_bcount(size)       caddr_t data,
1249         __in                    size_t size,
1250         __out_opt               boolean_t *cksummedp);
1251
1252 extern  __checkReturn           efx_rc_t
1253 efx_vpd_hunk_reinit(
1254         __in_bcount(size)       caddr_t data,
1255         __in                    size_t size,
1256         __in                    boolean_t wantpid);
1257
1258 extern  __checkReturn           efx_rc_t
1259 efx_vpd_hunk_get(
1260         __in_bcount(size)       caddr_t data,
1261         __in                    size_t size,
1262         __in                    efx_vpd_tag_t tag,
1263         __in                    efx_vpd_keyword_t keyword,
1264         __out                   unsigned int *payloadp,
1265         __out                   uint8_t *paylenp);
1266
1267 extern  __checkReturn                   efx_rc_t
1268 efx_vpd_hunk_next(
1269         __in_bcount(size)               caddr_t data,
1270         __in                            size_t size,
1271         __out                           efx_vpd_tag_t *tagp,
1272         __out                           efx_vpd_keyword_t *keyword,
1273         __out_opt                       unsigned int *payloadp,
1274         __out_opt                       uint8_t *paylenp,
1275         __inout                         unsigned int *contp);
1276
1277 extern  __checkReturn           efx_rc_t
1278 efx_vpd_hunk_set(
1279         __in_bcount(size)       caddr_t data,
1280         __in                    size_t size,
1281         __in                    efx_vpd_value_t *evvp);
1282
1283 #endif  /* EFSYS_OPT_VPD */
1284
1285 #if EFSYS_OPT_MCDI
1286
1287 extern  __checkReturn           efx_rc_t
1288 efx_mcdi_set_workaround(
1289         __in                    efx_nic_t *enp,
1290         __in                    uint32_t type,
1291         __in                    boolean_t enabled,
1292         __out_opt               uint32_t *flagsp);
1293
1294 extern  __checkReturn           efx_rc_t
1295 efx_mcdi_get_workarounds(
1296         __in                    efx_nic_t *enp,
1297         __out_opt               uint32_t *implementedp,
1298         __out_opt               uint32_t *enabledp);
1299
1300 #endif /* EFSYS_OPT_MCDI */
1301
1302 #if EFSYS_OPT_MAC_STATS
1303
1304 /*
1305  * Closed range of stats (i.e. the first and the last are included).
1306  * The last must be greater or equal (if the range is one item only) to
1307  * the first.
1308  */
1309 struct efx_mac_stats_range {
1310         efx_mac_stat_t          first;
1311         efx_mac_stat_t          last;
1312 };
1313
1314 extern                                  efx_rc_t
1315 efx_mac_stats_mask_add_ranges(
1316         __inout_bcount(mask_size)       uint32_t *maskp,
1317         __in                            size_t mask_size,
1318         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1319         __in                            unsigned int rng_count);
1320
1321 #endif  /* EFSYS_OPT_MAC_STATS */
1322
1323 #ifdef  __cplusplus
1324 }
1325 #endif
1326
1327 #endif  /* _SYS_EFX_IMPL_H */