1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
14 /* FIXME: Add definition for driver generated software events */
15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
21 #include "siena_impl.h"
22 #endif /* EFSYS_OPT_SIENA */
24 #if EFSYS_OPT_HUNTINGTON
25 #include "hunt_impl.h"
26 #endif /* EFSYS_OPT_HUNTINGTON */
29 #include "medford_impl.h"
30 #endif /* EFSYS_OPT_MEDFORD */
32 #if EFSYS_OPT_MEDFORD2
33 #include "medford2_impl.h"
34 #endif /* EFSYS_OPT_MEDFORD2 */
36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
37 #include "ef10_impl.h"
38 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
44 #define EFX_MOD_MCDI 0x00000001
45 #define EFX_MOD_PROBE 0x00000002
46 #define EFX_MOD_NVRAM 0x00000004
47 #define EFX_MOD_VPD 0x00000008
48 #define EFX_MOD_NIC 0x00000010
49 #define EFX_MOD_INTR 0x00000020
50 #define EFX_MOD_EV 0x00000040
51 #define EFX_MOD_RX 0x00000080
52 #define EFX_MOD_TX 0x00000100
53 #define EFX_MOD_PORT 0x00000200
54 #define EFX_MOD_MON 0x00000400
55 #define EFX_MOD_FILTER 0x00001000
56 #define EFX_MOD_LIC 0x00002000
57 #define EFX_MOD_TUNNEL 0x00004000
59 #define EFX_RESET_PHY 0x00000001
60 #define EFX_RESET_RXQ_ERR 0x00000002
61 #define EFX_RESET_TXQ_ERR 0x00000004
63 typedef enum efx_mac_type_e {
72 typedef struct efx_ev_ops_s {
73 efx_rc_t (*eevo_init)(efx_nic_t *);
74 void (*eevo_fini)(efx_nic_t *);
75 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
76 efsys_mem_t *, size_t, uint32_t,
77 uint32_t, uint32_t, efx_evq_t *);
78 void (*eevo_qdestroy)(efx_evq_t *);
79 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
80 void (*eevo_qpost)(efx_evq_t *, uint16_t);
81 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
83 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
87 typedef struct efx_tx_ops_s {
88 efx_rc_t (*etxo_init)(efx_nic_t *);
89 void (*etxo_fini)(efx_nic_t *);
90 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
91 unsigned int, unsigned int,
92 efsys_mem_t *, size_t,
94 efx_evq_t *, efx_txq_t *,
96 void (*etxo_qdestroy)(efx_txq_t *);
97 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
98 unsigned int, unsigned int,
100 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
101 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
102 efx_rc_t (*etxo_qflush)(efx_txq_t *);
103 void (*etxo_qenable)(efx_txq_t *);
104 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
105 void (*etxo_qpio_disable)(efx_txq_t *);
106 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
108 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
110 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
111 unsigned int, unsigned int,
113 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
116 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
119 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
120 uint16_t, uint32_t, uint16_t,
122 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
124 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
127 void (*etxo_qstats_update)(efx_txq_t *,
132 typedef union efx_rxq_type_data_u {
133 /* Dummy member to have non-empty union if no options are enabled */
135 #if EFSYS_OPT_RX_PACKED_STREAM
137 uint32_t eps_buf_size;
138 } ertd_packed_stream;
140 } efx_rxq_type_data_t;
142 typedef struct efx_rx_ops_s {
143 efx_rc_t (*erxo_init)(efx_nic_t *);
144 void (*erxo_fini)(efx_nic_t *);
145 #if EFSYS_OPT_RX_SCATTER
146 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
148 #if EFSYS_OPT_RX_SCALE
149 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
150 efx_rx_scale_context_type_t,
151 uint32_t, uint32_t *);
152 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
153 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
155 efx_rx_hash_type_t, boolean_t);
156 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
158 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
159 unsigned int *, size_t);
160 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
162 #endif /* EFSYS_OPT_RX_SCALE */
163 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
165 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
166 unsigned int, unsigned int,
168 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
169 #if EFSYS_OPT_RX_PACKED_STREAM
170 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
171 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
173 uint16_t *, uint32_t *, uint32_t *);
175 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
176 void (*erxo_qenable)(efx_rxq_t *);
177 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
178 unsigned int, efx_rxq_type_t,
179 const efx_rxq_type_data_t *,
180 efsys_mem_t *, size_t, uint32_t,
182 efx_evq_t *, efx_rxq_t *);
183 void (*erxo_qdestroy)(efx_rxq_t *);
186 typedef struct efx_mac_ops_s {
187 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
188 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
189 efx_rc_t (*emo_addr_set)(efx_nic_t *);
190 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
191 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
192 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
193 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
194 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
195 efx_rxq_t *, boolean_t);
196 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
197 #if EFSYS_OPT_LOOPBACK
198 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
199 efx_loopback_type_t);
200 #endif /* EFSYS_OPT_LOOPBACK */
201 #if EFSYS_OPT_MAC_STATS
202 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
203 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
204 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
205 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
206 uint16_t, boolean_t);
207 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
208 efsys_stat_t *, uint32_t *);
209 #endif /* EFSYS_OPT_MAC_STATS */
212 typedef struct efx_phy_ops_s {
213 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
214 efx_rc_t (*epo_reset)(efx_nic_t *);
215 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
216 efx_rc_t (*epo_verify)(efx_nic_t *);
217 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
218 #if EFSYS_OPT_PHY_STATS
219 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
221 #endif /* EFSYS_OPT_PHY_STATS */
223 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
224 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
225 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
226 efx_bist_result_t *, uint32_t *,
227 unsigned long *, size_t);
228 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
229 #endif /* EFSYS_OPT_BIST */
233 typedef struct efx_filter_ops_s {
234 efx_rc_t (*efo_init)(efx_nic_t *);
235 void (*efo_fini)(efx_nic_t *);
236 efx_rc_t (*efo_restore)(efx_nic_t *);
237 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
238 boolean_t may_replace);
239 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
240 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
242 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
243 boolean_t, boolean_t, boolean_t,
244 uint8_t const *, uint32_t);
247 extern __checkReturn efx_rc_t
248 efx_filter_reconfigure(
250 __in_ecount(6) uint8_t const *mac_addr,
251 __in boolean_t all_unicst,
252 __in boolean_t mulcst,
253 __in boolean_t all_mulcst,
254 __in boolean_t brdcst,
255 __in_ecount(6*count) uint8_t const *addrs,
256 __in uint32_t count);
258 #endif /* EFSYS_OPT_FILTER */
261 typedef struct efx_tunnel_ops_s {
262 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
263 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
265 #endif /* EFSYS_OPT_TUNNEL */
267 typedef struct efx_port_s {
268 efx_mac_type_t ep_mac_type;
269 uint32_t ep_phy_type;
272 uint8_t ep_mac_addr[6];
273 efx_link_mode_t ep_link_mode;
274 boolean_t ep_all_unicst;
276 boolean_t ep_all_mulcst;
278 unsigned int ep_fcntl;
279 boolean_t ep_fcntl_autoneg;
280 efx_oword_t ep_multicst_hash[2];
281 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
282 EFX_MAC_MULTICAST_LIST_MAX];
283 uint32_t ep_mulcst_addr_count;
284 #if EFSYS_OPT_LOOPBACK
285 efx_loopback_type_t ep_loopback_type;
286 efx_link_mode_t ep_loopback_link_mode;
287 #endif /* EFSYS_OPT_LOOPBACK */
288 #if EFSYS_OPT_PHY_FLAGS
289 uint32_t ep_phy_flags;
290 #endif /* EFSYS_OPT_PHY_FLAGS */
291 #if EFSYS_OPT_PHY_LED_CONTROL
292 efx_phy_led_mode_t ep_phy_led_mode;
293 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
294 efx_phy_media_type_t ep_fixed_port_type;
295 efx_phy_media_type_t ep_module_type;
296 uint32_t ep_adv_cap_mask;
297 uint32_t ep_lp_cap_mask;
298 uint32_t ep_default_adv_cap_mask;
299 uint32_t ep_phy_cap_mask;
300 boolean_t ep_mac_drain;
302 efx_bist_type_t ep_current_bist;
304 const efx_mac_ops_t *ep_emop;
305 const efx_phy_ops_t *ep_epop;
308 typedef struct efx_mon_ops_s {
309 #if EFSYS_OPT_MON_STATS
310 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
311 efx_mon_stat_value_t *);
312 #endif /* EFSYS_OPT_MON_STATS */
315 typedef struct efx_mon_s {
316 efx_mon_type_t em_type;
317 const efx_mon_ops_t *em_emop;
320 typedef struct efx_intr_ops_s {
321 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
322 void (*eio_enable)(efx_nic_t *);
323 void (*eio_disable)(efx_nic_t *);
324 void (*eio_disable_unlocked)(efx_nic_t *);
325 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
326 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
327 void (*eio_status_message)(efx_nic_t *, unsigned int,
329 void (*eio_fatal)(efx_nic_t *);
330 void (*eio_fini)(efx_nic_t *);
333 typedef struct efx_intr_s {
334 const efx_intr_ops_t *ei_eiop;
335 efsys_mem_t *ei_esmp;
336 efx_intr_type_t ei_type;
337 unsigned int ei_level;
340 typedef struct efx_nic_ops_s {
341 efx_rc_t (*eno_probe)(efx_nic_t *);
342 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
343 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
344 efx_rc_t (*eno_reset)(efx_nic_t *);
345 efx_rc_t (*eno_init)(efx_nic_t *);
346 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
347 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
348 uint32_t *, size_t *);
350 efx_rc_t (*eno_register_test)(efx_nic_t *);
351 #endif /* EFSYS_OPT_DIAG */
352 void (*eno_fini)(efx_nic_t *);
353 void (*eno_unprobe)(efx_nic_t *);
356 #ifndef EFX_TXQ_LIMIT_TARGET
357 #define EFX_TXQ_LIMIT_TARGET 259
359 #ifndef EFX_RXQ_LIMIT_TARGET
360 #define EFX_RXQ_LIMIT_TARGET 512
368 typedef struct siena_filter_spec_s {
371 uint32_t sfs_dmaq_id;
372 uint32_t sfs_dword[3];
373 } siena_filter_spec_t;
375 typedef enum siena_filter_type_e {
376 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
377 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
378 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
379 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
380 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
381 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
383 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
384 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
385 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
386 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
387 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
388 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
390 EFX_SIENA_FILTER_NTYPES
391 } siena_filter_type_t;
393 typedef enum siena_filter_tbl_id_e {
394 EFX_SIENA_FILTER_TBL_RX_IP = 0,
395 EFX_SIENA_FILTER_TBL_RX_MAC,
396 EFX_SIENA_FILTER_TBL_TX_IP,
397 EFX_SIENA_FILTER_TBL_TX_MAC,
398 EFX_SIENA_FILTER_NTBLS
399 } siena_filter_tbl_id_t;
401 typedef struct siena_filter_tbl_s {
402 int sft_size; /* number of entries */
403 int sft_used; /* active count */
404 uint32_t *sft_bitmap; /* active bitmap */
405 siena_filter_spec_t *sft_spec; /* array of saved specs */
406 } siena_filter_tbl_t;
408 typedef struct siena_filter_s {
409 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
410 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
413 #endif /* EFSYS_OPT_SIENA */
415 typedef struct efx_filter_s {
417 siena_filter_t *ef_siena_filter;
418 #endif /* EFSYS_OPT_SIENA */
419 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
420 ef10_filter_table_t *ef_ef10_filter_table;
421 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
427 siena_filter_tbl_clear(
429 __in siena_filter_tbl_id_t tbl);
431 #endif /* EFSYS_OPT_SIENA */
433 #endif /* EFSYS_OPT_FILTER */
437 #define EFX_TUNNEL_MAXNENTRIES (16)
441 typedef struct efx_tunnel_udp_entry_s {
442 uint16_t etue_port; /* host/cpu-endian */
443 uint16_t etue_protocol;
444 } efx_tunnel_udp_entry_t;
446 typedef struct efx_tunnel_cfg_s {
447 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
448 unsigned int etc_udp_entries_num;
451 #endif /* EFSYS_OPT_TUNNEL */
453 typedef struct efx_mcdi_ops_s {
454 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
455 void (*emco_send_request)(efx_nic_t *, void *, size_t,
457 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
458 boolean_t (*emco_poll_response)(efx_nic_t *);
459 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
460 void (*emco_fini)(efx_nic_t *);
461 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
462 efx_mcdi_feature_id_t, boolean_t *);
463 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
467 typedef struct efx_mcdi_s {
468 const efx_mcdi_ops_t *em_emcop;
469 const efx_mcdi_transport_t *em_emtp;
470 efx_mcdi_iface_t em_emip;
473 #endif /* EFSYS_OPT_MCDI */
477 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
478 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
480 typedef struct efx_nvram_ops_s {
482 efx_rc_t (*envo_test)(efx_nic_t *);
483 #endif /* EFSYS_OPT_DIAG */
484 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
486 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
487 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
488 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
489 unsigned int, caddr_t, size_t);
490 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
491 unsigned int, caddr_t, size_t);
492 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
493 unsigned int, size_t);
494 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
495 unsigned int, caddr_t, size_t);
496 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
498 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
499 uint32_t *, uint16_t *);
500 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
502 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
505 #endif /* EFSYS_OPT_NVRAM */
508 typedef struct efx_vpd_ops_s {
509 efx_rc_t (*evpdo_init)(efx_nic_t *);
510 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
511 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
512 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
513 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
514 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
516 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
518 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
519 efx_vpd_value_t *, unsigned int *);
520 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
521 void (*evpdo_fini)(efx_nic_t *);
523 #endif /* EFSYS_OPT_VPD */
525 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
527 __checkReturn efx_rc_t
528 efx_mcdi_nvram_partitions(
530 __out_bcount(size) caddr_t data,
532 __out unsigned int *npartnp);
534 __checkReturn efx_rc_t
535 efx_mcdi_nvram_metadata(
538 __out uint32_t *subtypep,
539 __out_ecount(4) uint16_t version[4],
540 __out_bcount_opt(size) char *descp,
543 __checkReturn efx_rc_t
547 __out_opt size_t *sizep,
548 __out_opt uint32_t *addressp,
549 __out_opt uint32_t *erase_sizep,
550 __out_opt uint32_t *write_sizep);
552 __checkReturn efx_rc_t
553 efx_mcdi_nvram_update_start(
555 __in uint32_t partn);
557 __checkReturn efx_rc_t
561 __in uint32_t offset,
562 __out_bcount(size) caddr_t data,
566 __checkReturn efx_rc_t
567 efx_mcdi_nvram_erase(
570 __in uint32_t offset,
573 __checkReturn efx_rc_t
574 efx_mcdi_nvram_write(
577 __in uint32_t offset,
578 __out_bcount(size) caddr_t data,
581 __checkReturn efx_rc_t
582 efx_mcdi_nvram_update_finish(
585 __in boolean_t reboot,
586 __out_opt uint32_t *verify_resultp);
590 __checkReturn efx_rc_t
593 __in uint32_t partn);
595 #endif /* EFSYS_OPT_DIAG */
597 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
599 #if EFSYS_OPT_LICENSING
601 typedef struct efx_lic_ops_s {
602 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
603 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
604 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
605 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
606 size_t *, uint8_t *);
607 efx_rc_t (*elo_find_start)
608 (efx_nic_t *, caddr_t, size_t, uint32_t *);
609 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
610 uint32_t, uint32_t *);
611 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
612 uint32_t, uint32_t *, uint32_t *);
613 boolean_t (*elo_validate_key)(efx_nic_t *,
615 efx_rc_t (*elo_read_key)(efx_nic_t *,
616 caddr_t, size_t, uint32_t, uint32_t,
617 caddr_t, size_t, uint32_t *);
618 efx_rc_t (*elo_write_key)(efx_nic_t *,
619 caddr_t, size_t, uint32_t,
620 caddr_t, uint32_t, uint32_t *);
621 efx_rc_t (*elo_delete_key)(efx_nic_t *,
622 caddr_t, size_t, uint32_t,
623 uint32_t, uint32_t, uint32_t *);
624 efx_rc_t (*elo_create_partition)(efx_nic_t *,
626 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
632 typedef struct efx_drv_cfg_s {
633 uint32_t edc_min_vi_count;
634 uint32_t edc_max_vi_count;
636 uint32_t edc_max_piobuf_count;
637 uint32_t edc_pio_alloc_size;
642 efx_family_t en_family;
643 uint32_t en_features;
644 efsys_identifier_t *en_esip;
645 efsys_lock_t *en_eslp;
646 efsys_bar_t *en_esbp;
647 unsigned int en_mod_flags;
648 unsigned int en_reset_flags;
649 efx_nic_cfg_t en_nic_cfg;
650 efx_drv_cfg_t en_drv_cfg;
654 uint32_t en_ev_qcount;
655 uint32_t en_rx_qcount;
656 uint32_t en_tx_qcount;
657 const efx_nic_ops_t *en_enop;
658 const efx_ev_ops_t *en_eevop;
659 const efx_tx_ops_t *en_etxop;
660 const efx_rx_ops_t *en_erxop;
661 efx_fw_variant_t efv;
663 efx_filter_t en_filter;
664 const efx_filter_ops_t *en_efop;
665 #endif /* EFSYS_OPT_FILTER */
667 efx_tunnel_cfg_t en_tunnel_cfg;
668 const efx_tunnel_ops_t *en_etop;
669 #endif /* EFSYS_OPT_TUNNEL */
672 #endif /* EFSYS_OPT_MCDI */
674 uint32_t en_nvram_partn_locked;
675 const efx_nvram_ops_t *en_envop;
676 #endif /* EFSYS_OPT_NVRAM */
678 const efx_vpd_ops_t *en_evpdop;
679 #endif /* EFSYS_OPT_VPD */
680 #if EFSYS_OPT_RX_SCALE
681 efx_rx_hash_support_t en_hash_support;
682 efx_rx_scale_context_type_t en_rss_context_type;
683 uint32_t en_rss_context;
684 #endif /* EFSYS_OPT_RX_SCALE */
685 uint32_t en_vport_id;
686 #if EFSYS_OPT_LICENSING
687 const efx_lic_ops_t *en_elop;
688 boolean_t en_licensing_supported;
693 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
694 unsigned int enu_partn_mask;
695 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
698 size_t enu_svpd_length;
699 #endif /* EFSYS_OPT_VPD */
702 #endif /* EFSYS_OPT_SIENA */
705 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
713 size_t ena_svpd_length;
714 #endif /* EFSYS_OPT_VPD */
715 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
716 uint32_t ena_piobuf_count;
717 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
718 uint32_t ena_pio_write_vi_base;
719 /* Memory BAR mapping regions */
720 uint32_t ena_uc_mem_map_offset;
721 size_t ena_uc_mem_map_size;
722 uint32_t ena_wc_mem_map_offset;
723 size_t ena_wc_mem_map_size;
726 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
730 #define EFX_NIC_MAGIC 0x02121996
732 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
733 const efx_ev_callbacks_t *, void *);
735 typedef struct efx_evq_rxq_state_s {
736 unsigned int eers_rx_read_ptr;
737 unsigned int eers_rx_mask;
738 #if EFSYS_OPT_RX_PACKED_STREAM
739 unsigned int eers_rx_stream_npackets;
740 boolean_t eers_rx_packed_stream;
741 unsigned int eers_rx_packed_stream_credits;
743 } efx_evq_rxq_state_t;
748 unsigned int ee_index;
749 unsigned int ee_mask;
750 efsys_mem_t *ee_esmp;
752 uint32_t ee_stat[EV_NQSTATS];
753 #endif /* EFSYS_OPT_QSTATS */
755 efx_ev_handler_t ee_rx;
756 efx_ev_handler_t ee_tx;
757 efx_ev_handler_t ee_driver;
758 efx_ev_handler_t ee_global;
759 efx_ev_handler_t ee_drv_gen;
761 efx_ev_handler_t ee_mcdi;
762 #endif /* EFSYS_OPT_MCDI */
764 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
769 #define EFX_EVQ_MAGIC 0x08081997
771 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
777 unsigned int er_index;
778 unsigned int er_label;
779 unsigned int er_mask;
780 efsys_mem_t *er_esmp;
781 efx_evq_rxq_state_t *er_ev_qstate;
784 #define EFX_RXQ_MAGIC 0x15022005
789 unsigned int et_index;
790 unsigned int et_mask;
791 efsys_mem_t *et_esmp;
792 #if EFSYS_OPT_HUNTINGTON
793 uint32_t et_pio_bufnum;
794 uint32_t et_pio_blknum;
795 uint32_t et_pio_write_offset;
796 uint32_t et_pio_offset;
800 uint32_t et_stat[TX_NQSTATS];
801 #endif /* EFSYS_OPT_QSTATS */
804 #define EFX_TXQ_MAGIC 0x05092005
806 #define EFX_MAC_ADDR_COPY(_dst, _src) \
808 (_dst)[0] = (_src)[0]; \
809 (_dst)[1] = (_src)[1]; \
810 (_dst)[2] = (_src)[2]; \
811 (_dst)[3] = (_src)[3]; \
812 (_dst)[4] = (_src)[4]; \
813 (_dst)[5] = (_src)[5]; \
814 _NOTE(CONSTANTCONDITION) \
817 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
819 uint16_t *_d = (uint16_t *)(_dst); \
823 _NOTE(CONSTANTCONDITION) \
826 #if EFSYS_OPT_CHECK_REG
827 #define EFX_CHECK_REG(_enp, _reg) \
829 const char *name = #_reg; \
830 char min = name[4]; \
831 char max = name[5]; \
834 switch ((_enp)->en_family) { \
835 case EFX_FAMILY_SIENA: \
839 case EFX_FAMILY_HUNTINGTON: \
843 case EFX_FAMILY_MEDFORD: \
847 case EFX_FAMILY_MEDFORD2: \
856 EFSYS_ASSERT3S(rev, >=, min); \
857 EFSYS_ASSERT3S(rev, <=, max); \
859 _NOTE(CONSTANTCONDITION) \
862 #define EFX_CHECK_REG(_enp, _reg) do { \
863 _NOTE(CONSTANTCONDITION) \
867 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
869 EFX_CHECK_REG((_enp), (_reg)); \
870 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
872 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
873 uint32_t, _reg ## _OFST, \
874 uint32_t, (_edp)->ed_u32[0]); \
875 _NOTE(CONSTANTCONDITION) \
878 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
880 EFX_CHECK_REG((_enp), (_reg)); \
881 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
882 uint32_t, _reg ## _OFST, \
883 uint32_t, (_edp)->ed_u32[0]); \
884 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
886 _NOTE(CONSTANTCONDITION) \
889 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
891 EFX_CHECK_REG((_enp), (_reg)); \
892 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
894 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
895 uint32_t, _reg ## _OFST, \
896 uint32_t, (_eqp)->eq_u32[1], \
897 uint32_t, (_eqp)->eq_u32[0]); \
898 _NOTE(CONSTANTCONDITION) \
901 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
903 EFX_CHECK_REG((_enp), (_reg)); \
904 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
905 uint32_t, _reg ## _OFST, \
906 uint32_t, (_eqp)->eq_u32[1], \
907 uint32_t, (_eqp)->eq_u32[0]); \
908 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
910 _NOTE(CONSTANTCONDITION) \
913 #define EFX_BAR_READO(_enp, _reg, _eop) \
915 EFX_CHECK_REG((_enp), (_reg)); \
916 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
918 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
919 uint32_t, _reg ## _OFST, \
920 uint32_t, (_eop)->eo_u32[3], \
921 uint32_t, (_eop)->eo_u32[2], \
922 uint32_t, (_eop)->eo_u32[1], \
923 uint32_t, (_eop)->eo_u32[0]); \
924 _NOTE(CONSTANTCONDITION) \
927 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
929 EFX_CHECK_REG((_enp), (_reg)); \
930 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
931 uint32_t, _reg ## _OFST, \
932 uint32_t, (_eop)->eo_u32[3], \
933 uint32_t, (_eop)->eo_u32[2], \
934 uint32_t, (_eop)->eo_u32[1], \
935 uint32_t, (_eop)->eo_u32[0]); \
936 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
938 _NOTE(CONSTANTCONDITION) \
942 * Accessors for memory BAR non-VI tables.
944 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
945 * to ensure the correct runtime VI window size is used on Medford2.
947 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
950 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
952 EFX_CHECK_REG((_enp), (_reg)); \
953 EFSYS_BAR_READD((_enp)->en_esbp, \
954 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
956 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
957 uint32_t, (_index), \
958 uint32_t, _reg ## _OFST, \
959 uint32_t, (_edp)->ed_u32[0]); \
960 _NOTE(CONSTANTCONDITION) \
963 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
965 EFX_CHECK_REG((_enp), (_reg)); \
966 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
967 uint32_t, (_index), \
968 uint32_t, _reg ## _OFST, \
969 uint32_t, (_edp)->ed_u32[0]); \
970 EFSYS_BAR_WRITED((_enp)->en_esbp, \
971 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
973 _NOTE(CONSTANTCONDITION) \
976 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
978 EFX_CHECK_REG((_enp), (_reg)); \
979 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
980 uint32_t, (_index), \
981 uint32_t, _reg ## _OFST, \
982 uint32_t, (_edp)->ed_u32[0]); \
983 EFSYS_BAR_WRITED((_enp)->en_esbp, \
985 (3 * sizeof (efx_dword_t)) + \
986 ((_index) * _reg ## _STEP)), \
988 _NOTE(CONSTANTCONDITION) \
991 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
993 EFX_CHECK_REG((_enp), (_reg)); \
994 EFSYS_BAR_READQ((_enp)->en_esbp, \
995 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
997 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
998 uint32_t, (_index), \
999 uint32_t, _reg ## _OFST, \
1000 uint32_t, (_eqp)->eq_u32[1], \
1001 uint32_t, (_eqp)->eq_u32[0]); \
1002 _NOTE(CONSTANTCONDITION) \
1005 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1007 EFX_CHECK_REG((_enp), (_reg)); \
1008 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1009 uint32_t, (_index), \
1010 uint32_t, _reg ## _OFST, \
1011 uint32_t, (_eqp)->eq_u32[1], \
1012 uint32_t, (_eqp)->eq_u32[0]); \
1013 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1014 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1016 _NOTE(CONSTANTCONDITION) \
1019 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1021 EFX_CHECK_REG((_enp), (_reg)); \
1022 EFSYS_BAR_READO((_enp)->en_esbp, \
1023 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1025 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1026 uint32_t, (_index), \
1027 uint32_t, _reg ## _OFST, \
1028 uint32_t, (_eop)->eo_u32[3], \
1029 uint32_t, (_eop)->eo_u32[2], \
1030 uint32_t, (_eop)->eo_u32[1], \
1031 uint32_t, (_eop)->eo_u32[0]); \
1032 _NOTE(CONSTANTCONDITION) \
1035 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1037 EFX_CHECK_REG((_enp), (_reg)); \
1038 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1039 uint32_t, (_index), \
1040 uint32_t, _reg ## _OFST, \
1041 uint32_t, (_eop)->eo_u32[3], \
1042 uint32_t, (_eop)->eo_u32[2], \
1043 uint32_t, (_eop)->eo_u32[1], \
1044 uint32_t, (_eop)->eo_u32[0]); \
1045 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1046 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1048 _NOTE(CONSTANTCONDITION) \
1052 * Accessors for memory BAR per-VI registers.
1054 * The VI window size is 8KB for Medford and all earlier controllers.
1055 * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1058 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \
1060 EFX_CHECK_REG((_enp), (_reg)); \
1061 EFSYS_BAR_READD((_enp)->en_esbp, \
1062 ((_reg ## _OFST) + \
1063 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1065 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \
1066 uint32_t, (_index), \
1067 uint32_t, _reg ## _OFST, \
1068 uint32_t, (_edp)->ed_u32[0]); \
1069 _NOTE(CONSTANTCONDITION) \
1072 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \
1074 EFX_CHECK_REG((_enp), (_reg)); \
1075 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1076 uint32_t, (_index), \
1077 uint32_t, _reg ## _OFST, \
1078 uint32_t, (_edp)->ed_u32[0]); \
1079 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1080 ((_reg ## _OFST) + \
1081 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1083 _NOTE(CONSTANTCONDITION) \
1086 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \
1088 EFX_CHECK_REG((_enp), (_reg)); \
1089 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1090 uint32_t, (_index), \
1091 uint32_t, _reg ## _OFST, \
1092 uint32_t, (_edp)->ed_u32[0]); \
1093 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1094 ((_reg ## _OFST) + \
1095 (2 * sizeof (efx_dword_t)) + \
1096 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1098 _NOTE(CONSTANTCONDITION) \
1102 * Allow drivers to perform optimised 128-bit VI doorbell writes.
1103 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1104 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1105 * the need for locking in the host, and are the only ones known to be safe to
1106 * use 128-bites write with.
1108 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1110 EFX_CHECK_REG((_enp), (_reg)); \
1111 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \
1112 const char *, #_reg, \
1113 uint32_t, (_index), \
1114 uint32_t, _reg ## _OFST, \
1115 uint32_t, (_eop)->eo_u32[3], \
1116 uint32_t, (_eop)->eo_u32[2], \
1117 uint32_t, (_eop)->eo_u32[1], \
1118 uint32_t, (_eop)->eo_u32[0]); \
1119 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1121 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1123 _NOTE(CONSTANTCONDITION) \
1126 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1128 unsigned int _new = (_wptr); \
1129 unsigned int _old = (_owptr); \
1131 if ((_new) >= (_old)) \
1132 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1133 (_old) * sizeof (efx_desc_t), \
1134 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1137 * It is cheaper to sync entire map than sync \
1138 * two parts especially when offset/size are \
1139 * ignored and entire map is synced in any case.\
1141 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1143 (_entries) * sizeof (efx_desc_t)); \
1144 _NOTE(CONSTANTCONDITION) \
1147 extern __checkReturn efx_rc_t
1149 __in efx_nic_t *enp);
1152 efx_mac_multicast_hash_compute(
1153 __in_ecount(6*count) uint8_t const *addrs,
1155 __out efx_oword_t *hash_low,
1156 __out efx_oword_t *hash_high);
1158 extern __checkReturn efx_rc_t
1160 __in efx_nic_t *enp);
1164 __in efx_nic_t *enp);
1168 /* VPD utility functions */
1170 extern __checkReturn efx_rc_t
1171 efx_vpd_hunk_length(
1172 __in_bcount(size) caddr_t data,
1174 __out size_t *lengthp);
1176 extern __checkReturn efx_rc_t
1177 efx_vpd_hunk_verify(
1178 __in_bcount(size) caddr_t data,
1180 __out_opt boolean_t *cksummedp);
1182 extern __checkReturn efx_rc_t
1183 efx_vpd_hunk_reinit(
1184 __in_bcount(size) caddr_t data,
1186 __in boolean_t wantpid);
1188 extern __checkReturn efx_rc_t
1190 __in_bcount(size) caddr_t data,
1192 __in efx_vpd_tag_t tag,
1193 __in efx_vpd_keyword_t keyword,
1194 __out unsigned int *payloadp,
1195 __out uint8_t *paylenp);
1197 extern __checkReturn efx_rc_t
1199 __in_bcount(size) caddr_t data,
1201 __out efx_vpd_tag_t *tagp,
1202 __out efx_vpd_keyword_t *keyword,
1203 __out_opt unsigned int *payloadp,
1204 __out_opt uint8_t *paylenp,
1205 __inout unsigned int *contp);
1207 extern __checkReturn efx_rc_t
1209 __in_bcount(size) caddr_t data,
1211 __in efx_vpd_value_t *evvp);
1213 #endif /* EFSYS_OPT_VPD */
1217 extern __checkReturn efx_rc_t
1218 efx_mcdi_set_workaround(
1219 __in efx_nic_t *enp,
1221 __in boolean_t enabled,
1222 __out_opt uint32_t *flagsp);
1224 extern __checkReturn efx_rc_t
1225 efx_mcdi_get_workarounds(
1226 __in efx_nic_t *enp,
1227 __out_opt uint32_t *implementedp,
1228 __out_opt uint32_t *enabledp);
1230 #endif /* EFSYS_OPT_MCDI */
1232 #if EFSYS_OPT_MAC_STATS
1235 * Closed range of stats (i.e. the first and the last are included).
1236 * The last must be greater or equal (if the range is one item only) to
1239 struct efx_mac_stats_range {
1240 efx_mac_stat_t first;
1241 efx_mac_stat_t last;
1245 efx_mac_stats_mask_add_ranges(
1246 __inout_bcount(mask_size) uint32_t *maskp,
1247 __in size_t mask_size,
1248 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1249 __in unsigned int rng_count);
1251 #endif /* EFSYS_OPT_MAC_STATS */
1257 #endif /* _SYS_EFX_IMPL_H */