1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
15 #endif /* EFSYS_OPT_MCDI */
17 /* FIXME: Add definition for driver generated software events */
18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
24 #include "siena_impl.h"
25 #endif /* EFSYS_OPT_SIENA */
27 #if EFSYS_OPT_HUNTINGTON
28 #include "hunt_impl.h"
29 #endif /* EFSYS_OPT_HUNTINGTON */
32 #include "medford_impl.h"
33 #endif /* EFSYS_OPT_MEDFORD */
35 #if EFSYS_OPT_MEDFORD2
36 #include "medford2_impl.h"
37 #endif /* EFSYS_OPT_MEDFORD2 */
40 #include "ef10_impl.h"
41 #endif /* EFX_OPTS_EF10() */
47 #define EFX_MOD_MCDI 0x00000001
48 #define EFX_MOD_PROBE 0x00000002
49 #define EFX_MOD_NVRAM 0x00000004
50 #define EFX_MOD_VPD 0x00000008
51 #define EFX_MOD_NIC 0x00000010
52 #define EFX_MOD_INTR 0x00000020
53 #define EFX_MOD_EV 0x00000040
54 #define EFX_MOD_RX 0x00000080
55 #define EFX_MOD_TX 0x00000100
56 #define EFX_MOD_PORT 0x00000200
57 #define EFX_MOD_MON 0x00000400
58 #define EFX_MOD_FILTER 0x00001000
59 #define EFX_MOD_LIC 0x00002000
60 #define EFX_MOD_TUNNEL 0x00004000
62 #define EFX_RESET_PHY 0x00000001
63 #define EFX_RESET_RXQ_ERR 0x00000002
64 #define EFX_RESET_TXQ_ERR 0x00000004
65 #define EFX_RESET_HW_UNAVAIL 0x00000008
67 typedef enum efx_mac_type_e {
76 typedef struct efx_ev_ops_s {
77 efx_rc_t (*eevo_init)(efx_nic_t *);
78 void (*eevo_fini)(efx_nic_t *);
79 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
80 efsys_mem_t *, size_t, uint32_t,
81 uint32_t, uint32_t, efx_evq_t *);
82 void (*eevo_qdestroy)(efx_evq_t *);
83 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
84 void (*eevo_qpost)(efx_evq_t *, uint16_t);
85 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
87 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
91 typedef struct efx_tx_ops_s {
92 efx_rc_t (*etxo_init)(efx_nic_t *);
93 void (*etxo_fini)(efx_nic_t *);
94 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
95 unsigned int, unsigned int,
96 efsys_mem_t *, size_t,
98 efx_evq_t *, efx_txq_t *,
100 void (*etxo_qdestroy)(efx_txq_t *);
101 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
102 unsigned int, unsigned int,
104 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
105 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
106 efx_rc_t (*etxo_qflush)(efx_txq_t *);
107 void (*etxo_qenable)(efx_txq_t *);
108 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
109 void (*etxo_qpio_disable)(efx_txq_t *);
110 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
112 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
114 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
115 unsigned int, unsigned int,
117 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
120 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
123 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
124 uint16_t, uint32_t, uint16_t,
126 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
128 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
131 void (*etxo_qstats_update)(efx_txq_t *,
136 typedef union efx_rxq_type_data_u {
140 #if EFSYS_OPT_RX_PACKED_STREAM
142 uint32_t eps_buf_size;
143 } ertd_packed_stream;
145 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
147 uint32_t eessb_bufs_per_desc;
148 uint32_t eessb_max_dma_len;
149 uint32_t eessb_buf_stride;
150 uint32_t eessb_hol_block_timeout;
151 } ertd_es_super_buffer;
153 } efx_rxq_type_data_t;
155 typedef struct efx_rx_ops_s {
156 efx_rc_t (*erxo_init)(efx_nic_t *);
157 void (*erxo_fini)(efx_nic_t *);
158 #if EFSYS_OPT_RX_SCATTER
159 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
161 #if EFSYS_OPT_RX_SCALE
162 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
163 efx_rx_scale_context_type_t,
164 uint32_t, uint32_t *);
165 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
166 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
168 efx_rx_hash_type_t, boolean_t);
169 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
171 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
172 unsigned int *, size_t);
173 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
175 #endif /* EFSYS_OPT_RX_SCALE */
176 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
178 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
179 unsigned int, unsigned int,
181 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
182 #if EFSYS_OPT_RX_PACKED_STREAM
183 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
184 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
186 uint16_t *, uint32_t *, uint32_t *);
188 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
189 void (*erxo_qenable)(efx_rxq_t *);
190 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
191 unsigned int, efx_rxq_type_t,
192 const efx_rxq_type_data_t *,
193 efsys_mem_t *, size_t, uint32_t,
195 efx_evq_t *, efx_rxq_t *);
196 void (*erxo_qdestroy)(efx_rxq_t *);
199 typedef struct efx_mac_ops_s {
200 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
201 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
202 efx_rc_t (*emo_addr_set)(efx_nic_t *);
203 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
204 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
205 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
206 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
207 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
208 efx_rxq_t *, boolean_t);
209 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
210 #if EFSYS_OPT_LOOPBACK
211 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
212 efx_loopback_type_t);
213 #endif /* EFSYS_OPT_LOOPBACK */
214 #if EFSYS_OPT_MAC_STATS
215 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
216 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
217 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
218 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
219 uint16_t, boolean_t);
220 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
221 efsys_stat_t *, uint32_t *);
222 #endif /* EFSYS_OPT_MAC_STATS */
225 typedef struct efx_phy_ops_s {
226 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
227 efx_rc_t (*epo_reset)(efx_nic_t *);
228 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
229 efx_rc_t (*epo_verify)(efx_nic_t *);
230 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
231 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
232 #if EFSYS_OPT_PHY_STATS
233 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
235 #endif /* EFSYS_OPT_PHY_STATS */
237 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
238 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
239 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
240 efx_bist_result_t *, uint32_t *,
241 unsigned long *, size_t);
242 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
243 #endif /* EFSYS_OPT_BIST */
247 typedef struct efx_filter_ops_s {
248 efx_rc_t (*efo_init)(efx_nic_t *);
249 void (*efo_fini)(efx_nic_t *);
250 efx_rc_t (*efo_restore)(efx_nic_t *);
251 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
252 boolean_t may_replace);
253 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
254 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
256 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
257 boolean_t, boolean_t, boolean_t,
258 uint8_t const *, uint32_t);
261 extern __checkReturn efx_rc_t
262 efx_filter_reconfigure(
264 __in_ecount(6) uint8_t const *mac_addr,
265 __in boolean_t all_unicst,
266 __in boolean_t mulcst,
267 __in boolean_t all_mulcst,
268 __in boolean_t brdcst,
269 __in_ecount(6*count) uint8_t const *addrs,
270 __in uint32_t count);
272 #endif /* EFSYS_OPT_FILTER */
275 typedef struct efx_tunnel_ops_s {
276 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
277 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
279 #endif /* EFSYS_OPT_TUNNEL */
281 typedef struct efx_port_s {
282 efx_mac_type_t ep_mac_type;
283 uint32_t ep_phy_type;
286 uint8_t ep_mac_addr[6];
287 efx_link_mode_t ep_link_mode;
288 boolean_t ep_all_unicst;
290 boolean_t ep_all_mulcst;
292 unsigned int ep_fcntl;
293 boolean_t ep_fcntl_autoneg;
294 efx_oword_t ep_multicst_hash[2];
295 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
296 EFX_MAC_MULTICAST_LIST_MAX];
297 uint32_t ep_mulcst_addr_count;
298 #if EFSYS_OPT_LOOPBACK
299 efx_loopback_type_t ep_loopback_type;
300 efx_link_mode_t ep_loopback_link_mode;
301 #endif /* EFSYS_OPT_LOOPBACK */
302 #if EFSYS_OPT_PHY_FLAGS
303 uint32_t ep_phy_flags;
304 #endif /* EFSYS_OPT_PHY_FLAGS */
305 #if EFSYS_OPT_PHY_LED_CONTROL
306 efx_phy_led_mode_t ep_phy_led_mode;
307 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
308 efx_phy_media_type_t ep_fixed_port_type;
309 efx_phy_media_type_t ep_module_type;
310 uint32_t ep_adv_cap_mask;
311 uint32_t ep_lp_cap_mask;
312 uint32_t ep_default_adv_cap_mask;
313 uint32_t ep_phy_cap_mask;
314 boolean_t ep_mac_drain;
316 efx_bist_type_t ep_current_bist;
318 const efx_mac_ops_t *ep_emop;
319 const efx_phy_ops_t *ep_epop;
322 typedef struct efx_mon_ops_s {
323 #if EFSYS_OPT_MON_STATS
324 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
325 efx_mon_stat_value_t *);
326 efx_rc_t (*emo_limits_update)(efx_nic_t *,
327 efx_mon_stat_limits_t *);
328 #endif /* EFSYS_OPT_MON_STATS */
331 typedef struct efx_mon_s {
332 efx_mon_type_t em_type;
333 const efx_mon_ops_t *em_emop;
336 typedef struct efx_intr_ops_s {
337 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
338 void (*eio_enable)(efx_nic_t *);
339 void (*eio_disable)(efx_nic_t *);
340 void (*eio_disable_unlocked)(efx_nic_t *);
341 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
342 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
343 void (*eio_status_message)(efx_nic_t *, unsigned int,
345 void (*eio_fatal)(efx_nic_t *);
346 void (*eio_fini)(efx_nic_t *);
349 typedef struct efx_intr_s {
350 const efx_intr_ops_t *ei_eiop;
351 efsys_mem_t *ei_esmp;
352 efx_intr_type_t ei_type;
353 unsigned int ei_level;
356 typedef struct efx_nic_ops_s {
357 efx_rc_t (*eno_probe)(efx_nic_t *);
358 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
359 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
360 efx_rc_t (*eno_reset)(efx_nic_t *);
361 efx_rc_t (*eno_init)(efx_nic_t *);
362 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
363 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
364 uint32_t *, size_t *);
365 boolean_t (*eno_hw_unavailable)(efx_nic_t *);
366 void (*eno_set_hw_unavailable)(efx_nic_t *);
368 efx_rc_t (*eno_register_test)(efx_nic_t *);
369 #endif /* EFSYS_OPT_DIAG */
370 void (*eno_fini)(efx_nic_t *);
371 void (*eno_unprobe)(efx_nic_t *);
374 #ifndef EFX_TXQ_LIMIT_TARGET
375 #define EFX_TXQ_LIMIT_TARGET 259
377 #ifndef EFX_RXQ_LIMIT_TARGET
378 #define EFX_RXQ_LIMIT_TARGET 512
386 typedef struct siena_filter_spec_s {
389 uint32_t sfs_dmaq_id;
390 uint32_t sfs_dword[3];
391 } siena_filter_spec_t;
393 typedef enum siena_filter_type_e {
394 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
395 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
396 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
397 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
398 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
399 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
401 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
402 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
403 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
404 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
405 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
406 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
408 EFX_SIENA_FILTER_NTYPES
409 } siena_filter_type_t;
411 typedef enum siena_filter_tbl_id_e {
412 EFX_SIENA_FILTER_TBL_RX_IP = 0,
413 EFX_SIENA_FILTER_TBL_RX_MAC,
414 EFX_SIENA_FILTER_TBL_TX_IP,
415 EFX_SIENA_FILTER_TBL_TX_MAC,
416 EFX_SIENA_FILTER_NTBLS
417 } siena_filter_tbl_id_t;
419 typedef struct siena_filter_tbl_s {
420 int sft_size; /* number of entries */
421 int sft_used; /* active count */
422 uint32_t *sft_bitmap; /* active bitmap */
423 siena_filter_spec_t *sft_spec; /* array of saved specs */
424 } siena_filter_tbl_t;
426 typedef struct siena_filter_s {
427 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
428 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
431 #endif /* EFSYS_OPT_SIENA */
433 typedef struct efx_filter_s {
435 siena_filter_t *ef_siena_filter;
436 #endif /* EFSYS_OPT_SIENA */
438 ef10_filter_table_t *ef_ef10_filter_table;
439 #endif /* EFX_OPTS_EF10() */
445 siena_filter_tbl_clear(
447 __in siena_filter_tbl_id_t tbl);
449 #endif /* EFSYS_OPT_SIENA */
451 #endif /* EFSYS_OPT_FILTER */
455 #define EFX_TUNNEL_MAXNENTRIES (16)
459 typedef struct efx_tunnel_udp_entry_s {
460 uint16_t etue_port; /* host/cpu-endian */
461 uint16_t etue_protocol;
462 } efx_tunnel_udp_entry_t;
464 typedef struct efx_tunnel_cfg_s {
465 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
466 unsigned int etc_udp_entries_num;
469 #endif /* EFSYS_OPT_TUNNEL */
471 typedef struct efx_mcdi_ops_s {
472 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
473 void (*emco_send_request)(efx_nic_t *, void *, size_t,
475 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
476 boolean_t (*emco_poll_response)(efx_nic_t *);
477 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
478 void (*emco_fini)(efx_nic_t *);
479 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
480 efx_mcdi_feature_id_t, boolean_t *);
481 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
485 typedef struct efx_mcdi_s {
486 const efx_mcdi_ops_t *em_emcop;
487 const efx_mcdi_transport_t *em_emtp;
488 efx_mcdi_iface_t em_emip;
491 #endif /* EFSYS_OPT_MCDI */
495 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
496 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
498 typedef struct efx_nvram_ops_s {
500 efx_rc_t (*envo_test)(efx_nic_t *);
501 #endif /* EFSYS_OPT_DIAG */
502 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
504 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
505 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
506 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
507 unsigned int, caddr_t, size_t);
508 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
509 unsigned int, caddr_t, size_t);
510 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
511 unsigned int, size_t);
512 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
513 unsigned int, caddr_t, size_t);
514 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
516 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
517 uint32_t *, uint16_t *);
518 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
520 efx_rc_t (*envo_buffer_validate)(uint32_t,
523 #endif /* EFSYS_OPT_NVRAM */
526 typedef struct efx_vpd_ops_s {
527 efx_rc_t (*evpdo_init)(efx_nic_t *);
528 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
529 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
530 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
531 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
532 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
534 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
536 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
537 efx_vpd_value_t *, unsigned int *);
538 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
539 void (*evpdo_fini)(efx_nic_t *);
541 #endif /* EFSYS_OPT_VPD */
543 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
545 __checkReturn efx_rc_t
546 efx_mcdi_nvram_partitions(
548 __out_bcount(size) caddr_t data,
550 __out unsigned int *npartnp);
552 __checkReturn efx_rc_t
553 efx_mcdi_nvram_metadata(
556 __out uint32_t *subtypep,
557 __out_ecount(4) uint16_t version[4],
558 __out_bcount_opt(size) char *descp,
561 __checkReturn efx_rc_t
565 __out_opt size_t *sizep,
566 __out_opt uint32_t *addressp,
567 __out_opt uint32_t *erase_sizep,
568 __out_opt uint32_t *write_sizep);
570 __checkReturn efx_rc_t
571 efx_mcdi_nvram_update_start(
573 __in uint32_t partn);
575 __checkReturn efx_rc_t
579 __in uint32_t offset,
580 __out_bcount(size) caddr_t data,
584 __checkReturn efx_rc_t
585 efx_mcdi_nvram_erase(
588 __in uint32_t offset,
591 __checkReturn efx_rc_t
592 efx_mcdi_nvram_write(
595 __in uint32_t offset,
596 __in_bcount(size) caddr_t data,
599 __checkReturn efx_rc_t
600 efx_mcdi_nvram_update_finish(
603 __in boolean_t reboot,
604 __out_opt uint32_t *verify_resultp);
608 __checkReturn efx_rc_t
611 __in uint32_t partn);
613 #endif /* EFSYS_OPT_DIAG */
615 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
617 #if EFSYS_OPT_LICENSING
619 typedef struct efx_lic_ops_s {
620 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
621 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
622 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
623 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
624 size_t *, uint8_t *);
625 efx_rc_t (*elo_find_start)
626 (efx_nic_t *, caddr_t, size_t, uint32_t *);
627 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
628 uint32_t, uint32_t *);
629 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
630 uint32_t, uint32_t *, uint32_t *);
631 boolean_t (*elo_validate_key)(efx_nic_t *,
633 efx_rc_t (*elo_read_key)(efx_nic_t *,
634 caddr_t, size_t, uint32_t, uint32_t,
635 caddr_t, size_t, uint32_t *);
636 efx_rc_t (*elo_write_key)(efx_nic_t *,
637 caddr_t, size_t, uint32_t,
638 caddr_t, uint32_t, uint32_t *);
639 efx_rc_t (*elo_delete_key)(efx_nic_t *,
640 caddr_t, size_t, uint32_t,
641 uint32_t, uint32_t, uint32_t *);
642 efx_rc_t (*elo_create_partition)(efx_nic_t *,
644 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
650 typedef struct efx_drv_cfg_s {
651 uint32_t edc_min_vi_count;
652 uint32_t edc_max_vi_count;
654 uint32_t edc_max_piobuf_count;
655 uint32_t edc_pio_alloc_size;
660 efx_family_t en_family;
661 uint32_t en_features;
662 efsys_identifier_t *en_esip;
663 efsys_lock_t *en_eslp;
664 efsys_bar_t *en_esbp;
665 unsigned int en_mod_flags;
666 unsigned int en_reset_flags;
667 efx_nic_cfg_t en_nic_cfg;
668 efx_drv_cfg_t en_drv_cfg;
672 uint32_t en_ev_qcount;
673 uint32_t en_rx_qcount;
674 uint32_t en_tx_qcount;
675 const efx_nic_ops_t *en_enop;
676 const efx_ev_ops_t *en_eevop;
677 const efx_tx_ops_t *en_etxop;
678 const efx_rx_ops_t *en_erxop;
679 efx_fw_variant_t efv;
681 efx_filter_t en_filter;
682 const efx_filter_ops_t *en_efop;
683 #endif /* EFSYS_OPT_FILTER */
685 efx_tunnel_cfg_t en_tunnel_cfg;
686 const efx_tunnel_ops_t *en_etop;
687 #endif /* EFSYS_OPT_TUNNEL */
690 #endif /* EFSYS_OPT_MCDI */
692 uint32_t en_nvram_partn_locked;
693 const efx_nvram_ops_t *en_envop;
694 #endif /* EFSYS_OPT_NVRAM */
696 const efx_vpd_ops_t *en_evpdop;
697 #endif /* EFSYS_OPT_VPD */
698 #if EFSYS_OPT_RX_SCALE
699 efx_rx_hash_support_t en_hash_support;
700 efx_rx_scale_context_type_t en_rss_context_type;
701 uint32_t en_rss_context;
702 #endif /* EFSYS_OPT_RX_SCALE */
703 uint32_t en_vport_id;
704 #if EFSYS_OPT_LICENSING
705 const efx_lic_ops_t *en_elop;
706 boolean_t en_licensing_supported;
711 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
712 unsigned int enu_partn_mask;
713 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
716 size_t enu_svpd_length;
717 #endif /* EFSYS_OPT_VPD */
720 #endif /* EFSYS_OPT_SIENA */
731 size_t ena_svpd_length;
732 #endif /* EFSYS_OPT_VPD */
733 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
734 uint32_t ena_piobuf_count;
735 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
736 uint32_t ena_pio_write_vi_base;
737 /* Memory BAR mapping regions */
738 uint32_t ena_uc_mem_map_offset;
739 size_t ena_uc_mem_map_size;
740 uint32_t ena_wc_mem_map_offset;
741 size_t ena_wc_mem_map_size;
744 #endif /* EFX_OPTS_EF10() */
747 #define EFX_FAMILY_IS_EF10(_enp) \
748 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
749 (_enp)->en_family == EFX_FAMILY_MEDFORD || \
750 (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
753 #define EFX_NIC_MAGIC 0x02121996
755 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
756 const efx_ev_callbacks_t *, void *);
758 typedef struct efx_evq_rxq_state_s {
759 unsigned int eers_rx_read_ptr;
760 unsigned int eers_rx_mask;
761 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
762 unsigned int eers_rx_stream_npackets;
763 boolean_t eers_rx_packed_stream;
765 #if EFSYS_OPT_RX_PACKED_STREAM
766 unsigned int eers_rx_packed_stream_credits;
768 } efx_evq_rxq_state_t;
774 unsigned int ee_index;
775 unsigned int ee_mask;
776 efsys_mem_t *ee_esmp;
778 uint32_t ee_stat[EV_NQSTATS];
779 #endif /* EFSYS_OPT_QSTATS */
781 efx_ev_handler_t ee_rx;
782 efx_ev_handler_t ee_tx;
783 efx_ev_handler_t ee_driver;
784 efx_ev_handler_t ee_global;
785 efx_ev_handler_t ee_drv_gen;
787 efx_ev_handler_t ee_mcdi;
788 #endif /* EFSYS_OPT_MCDI */
790 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
793 #define EFX_EVQ_MAGIC 0x08081997
795 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
798 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
800 (_eep)->ee_stat[_stat]++; \
801 _NOTE(CONSTANTCONDITION) \
804 #define EFX_EV_QSTAT_INCR(_eep, _stat)
811 unsigned int er_index;
812 unsigned int er_label;
813 unsigned int er_mask;
815 efsys_mem_t *er_esmp;
816 efx_evq_rxq_state_t *er_ev_qstate;
819 #define EFX_RXQ_MAGIC 0x15022005
824 unsigned int et_index;
825 unsigned int et_mask;
826 efsys_mem_t *et_esmp;
827 #if EFSYS_OPT_HUNTINGTON
828 uint32_t et_pio_bufnum;
829 uint32_t et_pio_blknum;
830 uint32_t et_pio_write_offset;
831 uint32_t et_pio_offset;
835 uint32_t et_stat[TX_NQSTATS];
836 #endif /* EFSYS_OPT_QSTATS */
839 #define EFX_TXQ_MAGIC 0x05092005
841 #define EFX_MAC_ADDR_COPY(_dst, _src) \
843 (_dst)[0] = (_src)[0]; \
844 (_dst)[1] = (_src)[1]; \
845 (_dst)[2] = (_src)[2]; \
846 (_dst)[3] = (_src)[3]; \
847 (_dst)[4] = (_src)[4]; \
848 (_dst)[5] = (_src)[5]; \
849 _NOTE(CONSTANTCONDITION) \
852 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
854 uint16_t *_d = (uint16_t *)(_dst); \
858 _NOTE(CONSTANTCONDITION) \
861 #if EFSYS_OPT_CHECK_REG
862 #define EFX_CHECK_REG(_enp, _reg) \
864 const char *name = #_reg; \
865 char min = name[4]; \
866 char max = name[5]; \
869 switch ((_enp)->en_family) { \
870 case EFX_FAMILY_SIENA: \
874 case EFX_FAMILY_HUNTINGTON: \
878 case EFX_FAMILY_MEDFORD: \
882 case EFX_FAMILY_MEDFORD2: \
891 EFSYS_ASSERT3S(rev, >=, min); \
892 EFSYS_ASSERT3S(rev, <=, max); \
894 _NOTE(CONSTANTCONDITION) \
897 #define EFX_CHECK_REG(_enp, _reg) do { \
898 _NOTE(CONSTANTCONDITION) \
902 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
904 EFX_CHECK_REG((_enp), (_reg)); \
905 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
907 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
908 uint32_t, _reg ## _OFST, \
909 uint32_t, (_edp)->ed_u32[0]); \
910 _NOTE(CONSTANTCONDITION) \
913 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
915 EFX_CHECK_REG((_enp), (_reg)); \
916 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
917 uint32_t, _reg ## _OFST, \
918 uint32_t, (_edp)->ed_u32[0]); \
919 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
921 _NOTE(CONSTANTCONDITION) \
924 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
926 EFX_CHECK_REG((_enp), (_reg)); \
927 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
929 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
930 uint32_t, _reg ## _OFST, \
931 uint32_t, (_eqp)->eq_u32[1], \
932 uint32_t, (_eqp)->eq_u32[0]); \
933 _NOTE(CONSTANTCONDITION) \
936 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
938 EFX_CHECK_REG((_enp), (_reg)); \
939 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
940 uint32_t, _reg ## _OFST, \
941 uint32_t, (_eqp)->eq_u32[1], \
942 uint32_t, (_eqp)->eq_u32[0]); \
943 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
945 _NOTE(CONSTANTCONDITION) \
948 #define EFX_BAR_READO(_enp, _reg, _eop) \
950 EFX_CHECK_REG((_enp), (_reg)); \
951 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
953 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
954 uint32_t, _reg ## _OFST, \
955 uint32_t, (_eop)->eo_u32[3], \
956 uint32_t, (_eop)->eo_u32[2], \
957 uint32_t, (_eop)->eo_u32[1], \
958 uint32_t, (_eop)->eo_u32[0]); \
959 _NOTE(CONSTANTCONDITION) \
962 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
964 EFX_CHECK_REG((_enp), (_reg)); \
965 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
966 uint32_t, _reg ## _OFST, \
967 uint32_t, (_eop)->eo_u32[3], \
968 uint32_t, (_eop)->eo_u32[2], \
969 uint32_t, (_eop)->eo_u32[1], \
970 uint32_t, (_eop)->eo_u32[0]); \
971 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
973 _NOTE(CONSTANTCONDITION) \
977 * Accessors for memory BAR non-VI tables.
979 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
980 * to ensure the correct runtime VI window size is used on Medford2.
982 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
985 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
987 EFX_CHECK_REG((_enp), (_reg)); \
988 EFSYS_BAR_READD((_enp)->en_esbp, \
989 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
991 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
992 uint32_t, (_index), \
993 uint32_t, _reg ## _OFST, \
994 uint32_t, (_edp)->ed_u32[0]); \
995 _NOTE(CONSTANTCONDITION) \
998 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
1000 EFX_CHECK_REG((_enp), (_reg)); \
1001 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
1002 uint32_t, (_index), \
1003 uint32_t, _reg ## _OFST, \
1004 uint32_t, (_edp)->ed_u32[0]); \
1005 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1006 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1008 _NOTE(CONSTANTCONDITION) \
1011 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
1013 EFX_CHECK_REG((_enp), (_reg)); \
1014 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
1015 uint32_t, (_index), \
1016 uint32_t, _reg ## _OFST, \
1017 uint32_t, (_edp)->ed_u32[0]); \
1018 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1020 (3 * sizeof (efx_dword_t)) + \
1021 ((_index) * _reg ## _STEP)), \
1023 _NOTE(CONSTANTCONDITION) \
1026 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
1028 EFX_CHECK_REG((_enp), (_reg)); \
1029 EFSYS_BAR_READQ((_enp)->en_esbp, \
1030 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1032 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
1033 uint32_t, (_index), \
1034 uint32_t, _reg ## _OFST, \
1035 uint32_t, (_eqp)->eq_u32[1], \
1036 uint32_t, (_eqp)->eq_u32[0]); \
1037 _NOTE(CONSTANTCONDITION) \
1040 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1042 EFX_CHECK_REG((_enp), (_reg)); \
1043 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1044 uint32_t, (_index), \
1045 uint32_t, _reg ## _OFST, \
1046 uint32_t, (_eqp)->eq_u32[1], \
1047 uint32_t, (_eqp)->eq_u32[0]); \
1048 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1049 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1051 _NOTE(CONSTANTCONDITION) \
1054 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1056 EFX_CHECK_REG((_enp), (_reg)); \
1057 EFSYS_BAR_READO((_enp)->en_esbp, \
1058 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1060 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1061 uint32_t, (_index), \
1062 uint32_t, _reg ## _OFST, \
1063 uint32_t, (_eop)->eo_u32[3], \
1064 uint32_t, (_eop)->eo_u32[2], \
1065 uint32_t, (_eop)->eo_u32[1], \
1066 uint32_t, (_eop)->eo_u32[0]); \
1067 _NOTE(CONSTANTCONDITION) \
1070 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1072 EFX_CHECK_REG((_enp), (_reg)); \
1073 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1074 uint32_t, (_index), \
1075 uint32_t, _reg ## _OFST, \
1076 uint32_t, (_eop)->eo_u32[3], \
1077 uint32_t, (_eop)->eo_u32[2], \
1078 uint32_t, (_eop)->eo_u32[1], \
1079 uint32_t, (_eop)->eo_u32[0]); \
1080 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1081 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1083 _NOTE(CONSTANTCONDITION) \
1087 * Accessors for memory BAR per-VI registers.
1089 * The VI window size is 8KB for Medford and all earlier controllers.
1090 * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1093 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \
1095 EFX_CHECK_REG((_enp), (_reg)); \
1096 EFSYS_BAR_READD((_enp)->en_esbp, \
1097 ((_reg ## _OFST) + \
1098 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1100 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \
1101 uint32_t, (_index), \
1102 uint32_t, _reg ## _OFST, \
1103 uint32_t, (_edp)->ed_u32[0]); \
1104 _NOTE(CONSTANTCONDITION) \
1107 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \
1109 EFX_CHECK_REG((_enp), (_reg)); \
1110 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1111 uint32_t, (_index), \
1112 uint32_t, _reg ## _OFST, \
1113 uint32_t, (_edp)->ed_u32[0]); \
1114 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1115 ((_reg ## _OFST) + \
1116 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1118 _NOTE(CONSTANTCONDITION) \
1121 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \
1123 EFX_CHECK_REG((_enp), (_reg)); \
1124 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1125 uint32_t, (_index), \
1126 uint32_t, _reg ## _OFST, \
1127 uint32_t, (_edp)->ed_u32[0]); \
1128 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1129 ((_reg ## _OFST) + \
1130 (2 * sizeof (efx_dword_t)) + \
1131 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1133 _NOTE(CONSTANTCONDITION) \
1137 * Allow drivers to perform optimised 128-bit VI doorbell writes.
1138 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1139 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1140 * the need for locking in the host, and are the only ones known to be safe to
1141 * use 128-bites write with.
1143 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1145 EFX_CHECK_REG((_enp), (_reg)); \
1146 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \
1147 const char *, #_reg, \
1148 uint32_t, (_index), \
1149 uint32_t, _reg ## _OFST, \
1150 uint32_t, (_eop)->eo_u32[3], \
1151 uint32_t, (_eop)->eo_u32[2], \
1152 uint32_t, (_eop)->eo_u32[1], \
1153 uint32_t, (_eop)->eo_u32[0]); \
1154 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1156 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1158 _NOTE(CONSTANTCONDITION) \
1161 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1163 unsigned int _new = (_wptr); \
1164 unsigned int _old = (_owptr); \
1166 if ((_new) >= (_old)) \
1167 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1168 (_old) * sizeof (efx_desc_t), \
1169 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1172 * It is cheaper to sync entire map than sync \
1173 * two parts especially when offset/size are \
1174 * ignored and entire map is synced in any case.\
1176 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1178 (_entries) * sizeof (efx_desc_t)); \
1179 _NOTE(CONSTANTCONDITION) \
1182 extern __checkReturn efx_rc_t
1184 __in efx_nic_t *enp);
1187 efx_mac_multicast_hash_compute(
1188 __in_ecount(6*count) uint8_t const *addrs,
1190 __out efx_oword_t *hash_low,
1191 __out efx_oword_t *hash_high);
1193 extern __checkReturn efx_rc_t
1195 __in efx_nic_t *enp);
1199 __in efx_nic_t *enp);
1203 /* VPD utility functions */
1205 extern __checkReturn efx_rc_t
1206 efx_vpd_hunk_length(
1207 __in_bcount(size) caddr_t data,
1209 __out size_t *lengthp);
1211 extern __checkReturn efx_rc_t
1212 efx_vpd_hunk_verify(
1213 __in_bcount(size) caddr_t data,
1215 __out_opt boolean_t *cksummedp);
1217 extern __checkReturn efx_rc_t
1218 efx_vpd_hunk_reinit(
1219 __in_bcount(size) caddr_t data,
1221 __in boolean_t wantpid);
1223 extern __checkReturn efx_rc_t
1225 __in_bcount(size) caddr_t data,
1227 __in efx_vpd_tag_t tag,
1228 __in efx_vpd_keyword_t keyword,
1229 __out unsigned int *payloadp,
1230 __out uint8_t *paylenp);
1232 extern __checkReturn efx_rc_t
1234 __in_bcount(size) caddr_t data,
1236 __out efx_vpd_tag_t *tagp,
1237 __out efx_vpd_keyword_t *keyword,
1238 __out_opt unsigned int *payloadp,
1239 __out_opt uint8_t *paylenp,
1240 __inout unsigned int *contp);
1242 extern __checkReturn efx_rc_t
1244 __in_bcount(size) caddr_t data,
1246 __in efx_vpd_value_t *evvp);
1248 #endif /* EFSYS_OPT_VPD */
1252 extern __checkReturn efx_rc_t
1253 efx_mcdi_set_workaround(
1254 __in efx_nic_t *enp,
1256 __in boolean_t enabled,
1257 __out_opt uint32_t *flagsp);
1259 extern __checkReturn efx_rc_t
1260 efx_mcdi_get_workarounds(
1261 __in efx_nic_t *enp,
1262 __out_opt uint32_t *implementedp,
1263 __out_opt uint32_t *enabledp);
1265 #endif /* EFSYS_OPT_MCDI */
1267 #if EFSYS_OPT_MAC_STATS
1270 * Closed range of stats (i.e. the first and the last are included).
1271 * The last must be greater or equal (if the range is one item only) to
1274 struct efx_mac_stats_range {
1275 efx_mac_stat_t first;
1276 efx_mac_stat_t last;
1280 efx_mac_stats_mask_add_ranges(
1281 __inout_bcount(mask_size) uint32_t *maskp,
1282 __in size_t mask_size,
1283 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1284 __in unsigned int rng_count);
1286 #endif /* EFSYS_OPT_MAC_STATS */
1292 #endif /* _SYS_EFX_IMPL_H */