1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
14 /* FIXME: Add definition for driver generated software events */
15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
21 #include "siena_impl.h"
22 #endif /* EFSYS_OPT_SIENA */
24 #if EFSYS_OPT_HUNTINGTON
25 #include "hunt_impl.h"
26 #endif /* EFSYS_OPT_HUNTINGTON */
29 #include "medford_impl.h"
30 #endif /* EFSYS_OPT_MEDFORD */
32 #if EFSYS_OPT_MEDFORD2
33 #include "medford2_impl.h"
34 #endif /* EFSYS_OPT_MEDFORD2 */
36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
37 #include "ef10_impl.h"
38 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
44 #define EFX_MOD_MCDI 0x00000001
45 #define EFX_MOD_PROBE 0x00000002
46 #define EFX_MOD_NVRAM 0x00000004
47 #define EFX_MOD_VPD 0x00000008
48 #define EFX_MOD_NIC 0x00000010
49 #define EFX_MOD_INTR 0x00000020
50 #define EFX_MOD_EV 0x00000040
51 #define EFX_MOD_RX 0x00000080
52 #define EFX_MOD_TX 0x00000100
53 #define EFX_MOD_PORT 0x00000200
54 #define EFX_MOD_MON 0x00000400
55 #define EFX_MOD_FILTER 0x00001000
56 #define EFX_MOD_LIC 0x00002000
57 #define EFX_MOD_TUNNEL 0x00004000
59 #define EFX_RESET_PHY 0x00000001
60 #define EFX_RESET_RXQ_ERR 0x00000002
61 #define EFX_RESET_TXQ_ERR 0x00000004
63 typedef enum efx_mac_type_e {
71 typedef struct efx_ev_ops_s {
72 efx_rc_t (*eevo_init)(efx_nic_t *);
73 void (*eevo_fini)(efx_nic_t *);
74 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
75 efsys_mem_t *, size_t, uint32_t,
76 uint32_t, uint32_t, efx_evq_t *);
77 void (*eevo_qdestroy)(efx_evq_t *);
78 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
79 void (*eevo_qpost)(efx_evq_t *, uint16_t);
80 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
82 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
86 typedef struct efx_tx_ops_s {
87 efx_rc_t (*etxo_init)(efx_nic_t *);
88 void (*etxo_fini)(efx_nic_t *);
89 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
90 unsigned int, unsigned int,
91 efsys_mem_t *, size_t,
93 efx_evq_t *, efx_txq_t *,
95 void (*etxo_qdestroy)(efx_txq_t *);
96 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
97 unsigned int, unsigned int,
99 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
100 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
101 efx_rc_t (*etxo_qflush)(efx_txq_t *);
102 void (*etxo_qenable)(efx_txq_t *);
103 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
104 void (*etxo_qpio_disable)(efx_txq_t *);
105 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
107 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
109 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
110 unsigned int, unsigned int,
112 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
115 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
118 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
121 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
124 void (*etxo_qstats_update)(efx_txq_t *,
129 typedef struct efx_rx_ops_s {
130 efx_rc_t (*erxo_init)(efx_nic_t *);
131 void (*erxo_fini)(efx_nic_t *);
132 #if EFSYS_OPT_RX_SCATTER
133 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
135 #if EFSYS_OPT_RX_SCALE
136 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
137 efx_rx_scale_context_type_t,
138 uint32_t, uint32_t *);
139 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
140 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
142 efx_rx_hash_type_t, boolean_t);
143 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
145 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
146 unsigned int *, size_t);
147 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
149 #endif /* EFSYS_OPT_RX_SCALE */
150 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
152 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
153 unsigned int, unsigned int,
155 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
156 #if EFSYS_OPT_RX_PACKED_STREAM
157 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
158 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
160 uint16_t *, uint32_t *, uint32_t *);
162 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
163 void (*erxo_qenable)(efx_rxq_t *);
164 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
165 unsigned int, efx_rxq_type_t, uint32_t,
166 efsys_mem_t *, size_t, uint32_t,
168 efx_evq_t *, efx_rxq_t *);
169 void (*erxo_qdestroy)(efx_rxq_t *);
172 typedef struct efx_mac_ops_s {
173 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
174 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
175 efx_rc_t (*emo_addr_set)(efx_nic_t *);
176 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
177 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
178 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
179 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
180 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
181 efx_rxq_t *, boolean_t);
182 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
183 #if EFSYS_OPT_LOOPBACK
184 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
185 efx_loopback_type_t);
186 #endif /* EFSYS_OPT_LOOPBACK */
187 #if EFSYS_OPT_MAC_STATS
188 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
189 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
190 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
191 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
192 uint16_t, boolean_t);
193 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
194 efsys_stat_t *, uint32_t *);
195 #endif /* EFSYS_OPT_MAC_STATS */
198 typedef struct efx_phy_ops_s {
199 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
200 efx_rc_t (*epo_reset)(efx_nic_t *);
201 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
202 efx_rc_t (*epo_verify)(efx_nic_t *);
203 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
204 #if EFSYS_OPT_PHY_STATS
205 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
207 #endif /* EFSYS_OPT_PHY_STATS */
209 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
210 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
211 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
212 efx_bist_result_t *, uint32_t *,
213 unsigned long *, size_t);
214 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
215 #endif /* EFSYS_OPT_BIST */
219 typedef struct efx_filter_ops_s {
220 efx_rc_t (*efo_init)(efx_nic_t *);
221 void (*efo_fini)(efx_nic_t *);
222 efx_rc_t (*efo_restore)(efx_nic_t *);
223 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
224 boolean_t may_replace);
225 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
226 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
228 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
229 boolean_t, boolean_t, boolean_t,
230 uint8_t const *, uint32_t);
233 extern __checkReturn efx_rc_t
234 efx_filter_reconfigure(
236 __in_ecount(6) uint8_t const *mac_addr,
237 __in boolean_t all_unicst,
238 __in boolean_t mulcst,
239 __in boolean_t all_mulcst,
240 __in boolean_t brdcst,
241 __in_ecount(6*count) uint8_t const *addrs,
242 __in uint32_t count);
244 #endif /* EFSYS_OPT_FILTER */
247 typedef struct efx_tunnel_ops_s {
248 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
249 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
251 #endif /* EFSYS_OPT_TUNNEL */
253 typedef struct efx_port_s {
254 efx_mac_type_t ep_mac_type;
255 uint32_t ep_phy_type;
258 uint8_t ep_mac_addr[6];
259 efx_link_mode_t ep_link_mode;
260 boolean_t ep_all_unicst;
262 boolean_t ep_all_mulcst;
264 unsigned int ep_fcntl;
265 boolean_t ep_fcntl_autoneg;
266 efx_oword_t ep_multicst_hash[2];
267 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
268 EFX_MAC_MULTICAST_LIST_MAX];
269 uint32_t ep_mulcst_addr_count;
270 #if EFSYS_OPT_LOOPBACK
271 efx_loopback_type_t ep_loopback_type;
272 efx_link_mode_t ep_loopback_link_mode;
273 #endif /* EFSYS_OPT_LOOPBACK */
274 #if EFSYS_OPT_PHY_FLAGS
275 uint32_t ep_phy_flags;
276 #endif /* EFSYS_OPT_PHY_FLAGS */
277 #if EFSYS_OPT_PHY_LED_CONTROL
278 efx_phy_led_mode_t ep_phy_led_mode;
279 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
280 efx_phy_media_type_t ep_fixed_port_type;
281 efx_phy_media_type_t ep_module_type;
282 uint32_t ep_adv_cap_mask;
283 uint32_t ep_lp_cap_mask;
284 uint32_t ep_default_adv_cap_mask;
285 uint32_t ep_phy_cap_mask;
286 boolean_t ep_mac_drain;
288 efx_bist_type_t ep_current_bist;
290 const efx_mac_ops_t *ep_emop;
291 const efx_phy_ops_t *ep_epop;
294 typedef struct efx_mon_ops_s {
295 #if EFSYS_OPT_MON_STATS
296 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
297 efx_mon_stat_value_t *);
298 #endif /* EFSYS_OPT_MON_STATS */
301 typedef struct efx_mon_s {
302 efx_mon_type_t em_type;
303 const efx_mon_ops_t *em_emop;
306 typedef struct efx_intr_ops_s {
307 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
308 void (*eio_enable)(efx_nic_t *);
309 void (*eio_disable)(efx_nic_t *);
310 void (*eio_disable_unlocked)(efx_nic_t *);
311 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
312 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
313 void (*eio_status_message)(efx_nic_t *, unsigned int,
315 void (*eio_fatal)(efx_nic_t *);
316 void (*eio_fini)(efx_nic_t *);
319 typedef struct efx_intr_s {
320 const efx_intr_ops_t *ei_eiop;
321 efsys_mem_t *ei_esmp;
322 efx_intr_type_t ei_type;
323 unsigned int ei_level;
326 typedef struct efx_nic_ops_s {
327 efx_rc_t (*eno_probe)(efx_nic_t *);
328 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
329 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
330 efx_rc_t (*eno_reset)(efx_nic_t *);
331 efx_rc_t (*eno_init)(efx_nic_t *);
332 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
333 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
334 uint32_t *, size_t *);
336 efx_rc_t (*eno_register_test)(efx_nic_t *);
337 #endif /* EFSYS_OPT_DIAG */
338 void (*eno_fini)(efx_nic_t *);
339 void (*eno_unprobe)(efx_nic_t *);
342 #ifndef EFX_TXQ_LIMIT_TARGET
343 #define EFX_TXQ_LIMIT_TARGET 259
345 #ifndef EFX_RXQ_LIMIT_TARGET
346 #define EFX_RXQ_LIMIT_TARGET 512
354 typedef struct siena_filter_spec_s {
357 uint32_t sfs_dmaq_id;
358 uint32_t sfs_dword[3];
359 } siena_filter_spec_t;
361 typedef enum siena_filter_type_e {
362 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
363 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
364 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
365 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
366 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
367 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
369 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
370 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
371 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
372 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
373 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
374 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
376 EFX_SIENA_FILTER_NTYPES
377 } siena_filter_type_t;
379 typedef enum siena_filter_tbl_id_e {
380 EFX_SIENA_FILTER_TBL_RX_IP = 0,
381 EFX_SIENA_FILTER_TBL_RX_MAC,
382 EFX_SIENA_FILTER_TBL_TX_IP,
383 EFX_SIENA_FILTER_TBL_TX_MAC,
384 EFX_SIENA_FILTER_NTBLS
385 } siena_filter_tbl_id_t;
387 typedef struct siena_filter_tbl_s {
388 int sft_size; /* number of entries */
389 int sft_used; /* active count */
390 uint32_t *sft_bitmap; /* active bitmap */
391 siena_filter_spec_t *sft_spec; /* array of saved specs */
392 } siena_filter_tbl_t;
394 typedef struct siena_filter_s {
395 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
396 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
399 #endif /* EFSYS_OPT_SIENA */
401 typedef struct efx_filter_s {
403 siena_filter_t *ef_siena_filter;
404 #endif /* EFSYS_OPT_SIENA */
405 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
406 ef10_filter_table_t *ef_ef10_filter_table;
407 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
413 siena_filter_tbl_clear(
415 __in siena_filter_tbl_id_t tbl);
417 #endif /* EFSYS_OPT_SIENA */
419 #endif /* EFSYS_OPT_FILTER */
423 #define EFX_TUNNEL_MAXNENTRIES (16)
427 typedef struct efx_tunnel_udp_entry_s {
428 uint16_t etue_port; /* host/cpu-endian */
429 uint16_t etue_protocol;
430 } efx_tunnel_udp_entry_t;
432 typedef struct efx_tunnel_cfg_s {
433 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
434 unsigned int etc_udp_entries_num;
437 #endif /* EFSYS_OPT_TUNNEL */
439 typedef struct efx_mcdi_ops_s {
440 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
441 void (*emco_send_request)(efx_nic_t *, void *, size_t,
443 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
444 boolean_t (*emco_poll_response)(efx_nic_t *);
445 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
446 void (*emco_fini)(efx_nic_t *);
447 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
448 efx_mcdi_feature_id_t, boolean_t *);
449 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
453 typedef struct efx_mcdi_s {
454 const efx_mcdi_ops_t *em_emcop;
455 const efx_mcdi_transport_t *em_emtp;
456 efx_mcdi_iface_t em_emip;
459 #endif /* EFSYS_OPT_MCDI */
463 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
464 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
466 typedef struct efx_nvram_ops_s {
468 efx_rc_t (*envo_test)(efx_nic_t *);
469 #endif /* EFSYS_OPT_DIAG */
470 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
472 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
473 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
474 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
475 unsigned int, caddr_t, size_t);
476 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
477 unsigned int, caddr_t, size_t);
478 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
479 unsigned int, size_t);
480 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
481 unsigned int, caddr_t, size_t);
482 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
484 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
485 uint32_t *, uint16_t *);
486 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
488 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
491 #endif /* EFSYS_OPT_NVRAM */
494 typedef struct efx_vpd_ops_s {
495 efx_rc_t (*evpdo_init)(efx_nic_t *);
496 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
497 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
498 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
499 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
500 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
502 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
504 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
505 efx_vpd_value_t *, unsigned int *);
506 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
507 void (*evpdo_fini)(efx_nic_t *);
509 #endif /* EFSYS_OPT_VPD */
511 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
513 __checkReturn efx_rc_t
514 efx_mcdi_nvram_partitions(
516 __out_bcount(size) caddr_t data,
518 __out unsigned int *npartnp);
520 __checkReturn efx_rc_t
521 efx_mcdi_nvram_metadata(
524 __out uint32_t *subtypep,
525 __out_ecount(4) uint16_t version[4],
526 __out_bcount_opt(size) char *descp,
529 __checkReturn efx_rc_t
533 __out_opt size_t *sizep,
534 __out_opt uint32_t *addressp,
535 __out_opt uint32_t *erase_sizep,
536 __out_opt uint32_t *write_sizep);
538 __checkReturn efx_rc_t
539 efx_mcdi_nvram_update_start(
541 __in uint32_t partn);
543 __checkReturn efx_rc_t
547 __in uint32_t offset,
548 __out_bcount(size) caddr_t data,
552 __checkReturn efx_rc_t
553 efx_mcdi_nvram_erase(
556 __in uint32_t offset,
559 __checkReturn efx_rc_t
560 efx_mcdi_nvram_write(
563 __in uint32_t offset,
564 __out_bcount(size) caddr_t data,
567 __checkReturn efx_rc_t
568 efx_mcdi_nvram_update_finish(
571 __in boolean_t reboot,
572 __out_opt uint32_t *verify_resultp);
576 __checkReturn efx_rc_t
579 __in uint32_t partn);
581 #endif /* EFSYS_OPT_DIAG */
583 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
585 #if EFSYS_OPT_LICENSING
587 typedef struct efx_lic_ops_s {
588 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
589 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
590 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
591 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
592 size_t *, uint8_t *);
593 efx_rc_t (*elo_find_start)
594 (efx_nic_t *, caddr_t, size_t, uint32_t *);
595 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
596 uint32_t, uint32_t *);
597 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
598 uint32_t, uint32_t *, uint32_t *);
599 boolean_t (*elo_validate_key)(efx_nic_t *,
601 efx_rc_t (*elo_read_key)(efx_nic_t *,
602 caddr_t, size_t, uint32_t, uint32_t,
603 caddr_t, size_t, uint32_t *);
604 efx_rc_t (*elo_write_key)(efx_nic_t *,
605 caddr_t, size_t, uint32_t,
606 caddr_t, uint32_t, uint32_t *);
607 efx_rc_t (*elo_delete_key)(efx_nic_t *,
608 caddr_t, size_t, uint32_t,
609 uint32_t, uint32_t, uint32_t *);
610 efx_rc_t (*elo_create_partition)(efx_nic_t *,
612 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
618 typedef struct efx_drv_cfg_s {
619 uint32_t edc_min_vi_count;
620 uint32_t edc_max_vi_count;
622 uint32_t edc_max_piobuf_count;
623 uint32_t edc_pio_alloc_size;
628 efx_family_t en_family;
629 uint32_t en_features;
630 efsys_identifier_t *en_esip;
631 efsys_lock_t *en_eslp;
632 efsys_bar_t *en_esbp;
633 unsigned int en_mod_flags;
634 unsigned int en_reset_flags;
635 efx_nic_cfg_t en_nic_cfg;
636 efx_drv_cfg_t en_drv_cfg;
640 uint32_t en_ev_qcount;
641 uint32_t en_rx_qcount;
642 uint32_t en_tx_qcount;
643 const efx_nic_ops_t *en_enop;
644 const efx_ev_ops_t *en_eevop;
645 const efx_tx_ops_t *en_etxop;
646 const efx_rx_ops_t *en_erxop;
648 efx_filter_t en_filter;
649 const efx_filter_ops_t *en_efop;
650 #endif /* EFSYS_OPT_FILTER */
652 efx_tunnel_cfg_t en_tunnel_cfg;
653 const efx_tunnel_ops_t *en_etop;
654 #endif /* EFSYS_OPT_TUNNEL */
657 #endif /* EFSYS_OPT_MCDI */
659 uint32_t en_nvram_partn_locked;
660 const efx_nvram_ops_t *en_envop;
661 #endif /* EFSYS_OPT_NVRAM */
663 const efx_vpd_ops_t *en_evpdop;
664 #endif /* EFSYS_OPT_VPD */
665 #if EFSYS_OPT_RX_SCALE
666 efx_rx_hash_support_t en_hash_support;
667 efx_rx_scale_context_type_t en_rss_context_type;
668 uint32_t en_rss_context;
669 #endif /* EFSYS_OPT_RX_SCALE */
670 uint32_t en_vport_id;
671 #if EFSYS_OPT_LICENSING
672 const efx_lic_ops_t *en_elop;
673 boolean_t en_licensing_supported;
678 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
679 unsigned int enu_partn_mask;
680 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
683 size_t enu_svpd_length;
684 #endif /* EFSYS_OPT_VPD */
687 #endif /* EFSYS_OPT_SIENA */
690 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
698 size_t ena_svpd_length;
699 #endif /* EFSYS_OPT_VPD */
700 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
701 uint32_t ena_piobuf_count;
702 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
703 uint32_t ena_pio_write_vi_base;
704 /* Memory BAR mapping regions */
705 uint32_t ena_uc_mem_map_offset;
706 size_t ena_uc_mem_map_size;
707 uint32_t ena_wc_mem_map_offset;
708 size_t ena_wc_mem_map_size;
711 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
715 #define EFX_NIC_MAGIC 0x02121996
717 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
718 const efx_ev_callbacks_t *, void *);
720 typedef struct efx_evq_rxq_state_s {
721 unsigned int eers_rx_read_ptr;
722 unsigned int eers_rx_mask;
723 #if EFSYS_OPT_RX_PACKED_STREAM
724 unsigned int eers_rx_stream_npackets;
725 boolean_t eers_rx_packed_stream;
726 unsigned int eers_rx_packed_stream_credits;
728 } efx_evq_rxq_state_t;
733 unsigned int ee_index;
734 unsigned int ee_mask;
735 efsys_mem_t *ee_esmp;
737 uint32_t ee_stat[EV_NQSTATS];
738 #endif /* EFSYS_OPT_QSTATS */
740 efx_ev_handler_t ee_rx;
741 efx_ev_handler_t ee_tx;
742 efx_ev_handler_t ee_driver;
743 efx_ev_handler_t ee_global;
744 efx_ev_handler_t ee_drv_gen;
746 efx_ev_handler_t ee_mcdi;
747 #endif /* EFSYS_OPT_MCDI */
749 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
754 #define EFX_EVQ_MAGIC 0x08081997
756 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
762 unsigned int er_index;
763 unsigned int er_label;
764 unsigned int er_mask;
765 efsys_mem_t *er_esmp;
766 efx_evq_rxq_state_t *er_ev_qstate;
769 #define EFX_RXQ_MAGIC 0x15022005
774 unsigned int et_index;
775 unsigned int et_mask;
776 efsys_mem_t *et_esmp;
777 #if EFSYS_OPT_HUNTINGTON
778 uint32_t et_pio_bufnum;
779 uint32_t et_pio_blknum;
780 uint32_t et_pio_write_offset;
781 uint32_t et_pio_offset;
785 uint32_t et_stat[TX_NQSTATS];
786 #endif /* EFSYS_OPT_QSTATS */
789 #define EFX_TXQ_MAGIC 0x05092005
791 #define EFX_MAC_ADDR_COPY(_dst, _src) \
793 (_dst)[0] = (_src)[0]; \
794 (_dst)[1] = (_src)[1]; \
795 (_dst)[2] = (_src)[2]; \
796 (_dst)[3] = (_src)[3]; \
797 (_dst)[4] = (_src)[4]; \
798 (_dst)[5] = (_src)[5]; \
799 _NOTE(CONSTANTCONDITION) \
802 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
804 uint16_t *_d = (uint16_t *)(_dst); \
808 _NOTE(CONSTANTCONDITION) \
811 #if EFSYS_OPT_CHECK_REG
812 #define EFX_CHECK_REG(_enp, _reg) \
814 const char *name = #_reg; \
815 char min = name[4]; \
816 char max = name[5]; \
819 switch ((_enp)->en_family) { \
820 case EFX_FAMILY_SIENA: \
824 case EFX_FAMILY_HUNTINGTON: \
828 case EFX_FAMILY_MEDFORD: \
832 case EFX_FAMILY_MEDFORD2: \
841 EFSYS_ASSERT3S(rev, >=, min); \
842 EFSYS_ASSERT3S(rev, <=, max); \
844 _NOTE(CONSTANTCONDITION) \
847 #define EFX_CHECK_REG(_enp, _reg) do { \
848 _NOTE(CONSTANTCONDITION) \
852 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
854 EFX_CHECK_REG((_enp), (_reg)); \
855 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
857 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
858 uint32_t, _reg ## _OFST, \
859 uint32_t, (_edp)->ed_u32[0]); \
860 _NOTE(CONSTANTCONDITION) \
863 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
865 EFX_CHECK_REG((_enp), (_reg)); \
866 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
867 uint32_t, _reg ## _OFST, \
868 uint32_t, (_edp)->ed_u32[0]); \
869 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
871 _NOTE(CONSTANTCONDITION) \
874 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
876 EFX_CHECK_REG((_enp), (_reg)); \
877 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
879 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
880 uint32_t, _reg ## _OFST, \
881 uint32_t, (_eqp)->eq_u32[1], \
882 uint32_t, (_eqp)->eq_u32[0]); \
883 _NOTE(CONSTANTCONDITION) \
886 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
888 EFX_CHECK_REG((_enp), (_reg)); \
889 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
890 uint32_t, _reg ## _OFST, \
891 uint32_t, (_eqp)->eq_u32[1], \
892 uint32_t, (_eqp)->eq_u32[0]); \
893 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
895 _NOTE(CONSTANTCONDITION) \
898 #define EFX_BAR_READO(_enp, _reg, _eop) \
900 EFX_CHECK_REG((_enp), (_reg)); \
901 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
903 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
904 uint32_t, _reg ## _OFST, \
905 uint32_t, (_eop)->eo_u32[3], \
906 uint32_t, (_eop)->eo_u32[2], \
907 uint32_t, (_eop)->eo_u32[1], \
908 uint32_t, (_eop)->eo_u32[0]); \
909 _NOTE(CONSTANTCONDITION) \
912 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
914 EFX_CHECK_REG((_enp), (_reg)); \
915 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
916 uint32_t, _reg ## _OFST, \
917 uint32_t, (_eop)->eo_u32[3], \
918 uint32_t, (_eop)->eo_u32[2], \
919 uint32_t, (_eop)->eo_u32[1], \
920 uint32_t, (_eop)->eo_u32[0]); \
921 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
923 _NOTE(CONSTANTCONDITION) \
926 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
928 EFX_CHECK_REG((_enp), (_reg)); \
929 EFSYS_BAR_READD((_enp)->en_esbp, \
930 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
932 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
933 uint32_t, (_index), \
934 uint32_t, _reg ## _OFST, \
935 uint32_t, (_edp)->ed_u32[0]); \
936 _NOTE(CONSTANTCONDITION) \
939 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
941 EFX_CHECK_REG((_enp), (_reg)); \
942 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
943 uint32_t, (_index), \
944 uint32_t, _reg ## _OFST, \
945 uint32_t, (_edp)->ed_u32[0]); \
946 EFSYS_BAR_WRITED((_enp)->en_esbp, \
947 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
949 _NOTE(CONSTANTCONDITION) \
952 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
954 EFX_CHECK_REG((_enp), (_reg)); \
955 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
956 uint32_t, (_index), \
957 uint32_t, _reg ## _OFST, \
958 uint32_t, (_edp)->ed_u32[0]); \
959 EFSYS_BAR_WRITED((_enp)->en_esbp, \
961 (2 * sizeof (efx_dword_t)) + \
962 ((_index) * _reg ## _STEP)), \
964 _NOTE(CONSTANTCONDITION) \
967 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
969 EFX_CHECK_REG((_enp), (_reg)); \
970 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
971 uint32_t, (_index), \
972 uint32_t, _reg ## _OFST, \
973 uint32_t, (_edp)->ed_u32[0]); \
974 EFSYS_BAR_WRITED((_enp)->en_esbp, \
976 (3 * sizeof (efx_dword_t)) + \
977 ((_index) * _reg ## _STEP)), \
979 _NOTE(CONSTANTCONDITION) \
982 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
984 EFX_CHECK_REG((_enp), (_reg)); \
985 EFSYS_BAR_READQ((_enp)->en_esbp, \
986 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
988 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
989 uint32_t, (_index), \
990 uint32_t, _reg ## _OFST, \
991 uint32_t, (_eqp)->eq_u32[1], \
992 uint32_t, (_eqp)->eq_u32[0]); \
993 _NOTE(CONSTANTCONDITION) \
996 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
998 EFX_CHECK_REG((_enp), (_reg)); \
999 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1000 uint32_t, (_index), \
1001 uint32_t, _reg ## _OFST, \
1002 uint32_t, (_eqp)->eq_u32[1], \
1003 uint32_t, (_eqp)->eq_u32[0]); \
1004 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1005 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1007 _NOTE(CONSTANTCONDITION) \
1010 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1012 EFX_CHECK_REG((_enp), (_reg)); \
1013 EFSYS_BAR_READO((_enp)->en_esbp, \
1014 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1016 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1017 uint32_t, (_index), \
1018 uint32_t, _reg ## _OFST, \
1019 uint32_t, (_eop)->eo_u32[3], \
1020 uint32_t, (_eop)->eo_u32[2], \
1021 uint32_t, (_eop)->eo_u32[1], \
1022 uint32_t, (_eop)->eo_u32[0]); \
1023 _NOTE(CONSTANTCONDITION) \
1026 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1028 EFX_CHECK_REG((_enp), (_reg)); \
1029 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1030 uint32_t, (_index), \
1031 uint32_t, _reg ## _OFST, \
1032 uint32_t, (_eop)->eo_u32[3], \
1033 uint32_t, (_eop)->eo_u32[2], \
1034 uint32_t, (_eop)->eo_u32[1], \
1035 uint32_t, (_eop)->eo_u32[0]); \
1036 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1037 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1039 _NOTE(CONSTANTCONDITION) \
1043 * Allow drivers to perform optimised 128-bit doorbell writes.
1044 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1045 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1046 * the need for locking in the host, and are the only ones known to be safe to
1047 * use 128-bites write with.
1049 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1051 EFX_CHECK_REG((_enp), (_reg)); \
1052 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1053 const char *, #_reg, \
1054 uint32_t, (_index), \
1055 uint32_t, _reg ## _OFST, \
1056 uint32_t, (_eop)->eo_u32[3], \
1057 uint32_t, (_eop)->eo_u32[2], \
1058 uint32_t, (_eop)->eo_u32[1], \
1059 uint32_t, (_eop)->eo_u32[0]); \
1060 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1061 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1063 _NOTE(CONSTANTCONDITION) \
1066 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1068 unsigned int _new = (_wptr); \
1069 unsigned int _old = (_owptr); \
1071 if ((_new) >= (_old)) \
1072 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1073 (_old) * sizeof (efx_desc_t), \
1074 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1077 * It is cheaper to sync entire map than sync \
1078 * two parts especially when offset/size are \
1079 * ignored and entire map is synced in any case.\
1081 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1083 (_entries) * sizeof (efx_desc_t)); \
1084 _NOTE(CONSTANTCONDITION) \
1087 extern __checkReturn efx_rc_t
1089 __in efx_nic_t *enp);
1092 efx_mac_multicast_hash_compute(
1093 __in_ecount(6*count) uint8_t const *addrs,
1095 __out efx_oword_t *hash_low,
1096 __out efx_oword_t *hash_high);
1098 extern __checkReturn efx_rc_t
1100 __in efx_nic_t *enp);
1104 __in efx_nic_t *enp);
1108 /* VPD utility functions */
1110 extern __checkReturn efx_rc_t
1111 efx_vpd_hunk_length(
1112 __in_bcount(size) caddr_t data,
1114 __out size_t *lengthp);
1116 extern __checkReturn efx_rc_t
1117 efx_vpd_hunk_verify(
1118 __in_bcount(size) caddr_t data,
1120 __out_opt boolean_t *cksummedp);
1122 extern __checkReturn efx_rc_t
1123 efx_vpd_hunk_reinit(
1124 __in_bcount(size) caddr_t data,
1126 __in boolean_t wantpid);
1128 extern __checkReturn efx_rc_t
1130 __in_bcount(size) caddr_t data,
1132 __in efx_vpd_tag_t tag,
1133 __in efx_vpd_keyword_t keyword,
1134 __out unsigned int *payloadp,
1135 __out uint8_t *paylenp);
1137 extern __checkReturn efx_rc_t
1139 __in_bcount(size) caddr_t data,
1141 __out efx_vpd_tag_t *tagp,
1142 __out efx_vpd_keyword_t *keyword,
1143 __out_opt unsigned int *payloadp,
1144 __out_opt uint8_t *paylenp,
1145 __inout unsigned int *contp);
1147 extern __checkReturn efx_rc_t
1149 __in_bcount(size) caddr_t data,
1151 __in efx_vpd_value_t *evvp);
1153 #endif /* EFSYS_OPT_VPD */
1157 extern __checkReturn efx_rc_t
1158 efx_mcdi_set_workaround(
1159 __in efx_nic_t *enp,
1161 __in boolean_t enabled,
1162 __out_opt uint32_t *flagsp);
1164 extern __checkReturn efx_rc_t
1165 efx_mcdi_get_workarounds(
1166 __in efx_nic_t *enp,
1167 __out_opt uint32_t *implementedp,
1168 __out_opt uint32_t *enabledp);
1170 #endif /* EFSYS_OPT_MCDI */
1172 #if EFSYS_OPT_MAC_STATS
1175 * Closed range of stats (i.e. the first and the last are included).
1176 * The last must be greater or equal (if the range is one item only) to
1179 struct efx_mac_stats_range {
1180 efx_mac_stat_t first;
1181 efx_mac_stat_t last;
1185 efx_mac_stats_mask_add_ranges(
1186 __inout_bcount(mask_size) uint32_t *maskp,
1187 __in size_t mask_size,
1188 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1189 __in unsigned int rng_count);
1191 #endif /* EFSYS_OPT_MAC_STATS */
1197 #endif /* _SYS_EFX_IMPL_H */