drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154 #if EFSYS_OPT_RX_SCALE
 155         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 156                                                     efx_rx_scale_context_type_t,
 157                                                     uint32_t, uint32_t *);
 158         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 159         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 160                                                efx_rx_hash_alg_t,
 161                                                efx_rx_hash_type_t, boolean_t);
 162         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 163                                               uint8_t *, size_t);
 164         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 165                                               unsigned int *, size_t);
 166         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 167                                             uint8_t *);
 168 #endif /* EFSYS_OPT_RX_SCALE */
 169         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 170                                               uint16_t *);
 171         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 172                                       unsigned int, unsigned int,
 173                                       unsigned int);
 174         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 175 #if EFSYS_OPT_RX_PACKED_STREAM
 176         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 177         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 178                                                 uint32_t, uint32_t,
 179                                                 uint16_t *, uint32_t *, uint32_t *);
 180 #endif
 181         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 182         void            (*erxo_qenable)(efx_rxq_t *);
 183         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 184                                         unsigned int, efx_rxq_type_t,
 185                                         efsys_mem_t *, size_t, uint32_t,
 186                                         efx_evq_t *, efx_rxq_t *);
 187         void            (*erxo_qdestroy)(efx_rxq_t *);
 188 } efx_rx_ops_t;
 189
 190 typedef struct efx_mac_ops_s {
 191         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 192         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 193         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 194         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 195         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 196         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 197         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 198         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 199                                                       efx_rxq_t *, boolean_t);
 200         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 201 #if EFSYS_OPT_LOOPBACK
 202         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 203                                             efx_loopback_type_t);
 204 #endif  /* EFSYS_OPT_LOOPBACK */
 205 #if EFSYS_OPT_MAC_STATS
 206         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 207         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 208         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 209         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 210                                               uint16_t, boolean_t);
 211         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 212                                             efsys_stat_t *, uint32_t *);
 213 #endif  /* EFSYS_OPT_MAC_STATS */
 214 } efx_mac_ops_t;
 215
 216 typedef struct efx_phy_ops_s {
 217         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 218         efx_rc_t        (*epo_reset)(efx_nic_t *);
 219         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 220         efx_rc_t        (*epo_verify)(efx_nic_t *);
 221         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 222 #if EFSYS_OPT_PHY_STATS
 223         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 224                                             uint32_t *);
 225 #endif  /* EFSYS_OPT_PHY_STATS */
 226 #if EFSYS_OPT_BIST
 227         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 228         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 229         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 230                                          efx_bist_result_t *, uint32_t *,
 231                                          unsigned long *, size_t);
 232         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 233 #endif  /* EFSYS_OPT_BIST */
 234 } efx_phy_ops_t;
 235
 236 #if EFSYS_OPT_FILTER
 237 typedef struct efx_filter_ops_s {
 238         efx_rc_t        (*efo_init)(efx_nic_t *);
 239         void            (*efo_fini)(efx_nic_t *);
 240         efx_rc_t        (*efo_restore)(efx_nic_t *);
 241         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 242                                    boolean_t may_replace);
 243         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 244         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 245                                    size_t, size_t *);
 246         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 247                                    boolean_t, boolean_t, boolean_t,
 248                                    uint8_t const *, uint32_t);
 249 } efx_filter_ops_t;
 250
 251 extern  __checkReturn   efx_rc_t
 252 efx_filter_reconfigure(
 253         __in                            efx_nic_t *enp,
 254         __in_ecount(6)                  uint8_t const *mac_addr,
 255         __in                            boolean_t all_unicst,
 256         __in                            boolean_t mulcst,
 257         __in                            boolean_t all_mulcst,
 258         __in                            boolean_t brdcst,
 259         __in_ecount(6*count)            uint8_t const *addrs,
 260         __in                            uint32_t count);
 261
 262 #endif /* EFSYS_OPT_FILTER */
 263
 264
 265 typedef struct efx_port_s {
 266         efx_mac_type_t          ep_mac_type;
 267         uint32_t                ep_phy_type;
 268         uint8_t                 ep_port;
 269         uint32_t                ep_mac_pdu;
 270         uint8_t                 ep_mac_addr[6];
 271         efx_link_mode_t         ep_link_mode;
 272         boolean_t               ep_all_unicst;
 273         boolean_t               ep_mulcst;
 274         boolean_t               ep_all_mulcst;
 275         boolean_t               ep_brdcst;
 276         unsigned int            ep_fcntl;
 277         boolean_t               ep_fcntl_autoneg;
 278         efx_oword_t             ep_multicst_hash[2];
 279         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 280                                                     EFX_MAC_MULTICAST_LIST_MAX];
 281         uint32_t                ep_mulcst_addr_count;
 282 #if EFSYS_OPT_LOOPBACK
 283         efx_loopback_type_t     ep_loopback_type;
 284         efx_link_mode_t         ep_loopback_link_mode;
 285 #endif  /* EFSYS_OPT_LOOPBACK */
 286 #if EFSYS_OPT_PHY_FLAGS
 287         uint32_t                ep_phy_flags;
 288 #endif  /* EFSYS_OPT_PHY_FLAGS */
 289 #if EFSYS_OPT_PHY_LED_CONTROL
 290         efx_phy_led_mode_t      ep_phy_led_mode;
 291 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 292         efx_phy_media_type_t    ep_fixed_port_type;
 293         efx_phy_media_type_t    ep_module_type;
 294         uint32_t                ep_adv_cap_mask;
 295         uint32_t                ep_lp_cap_mask;
 296         uint32_t                ep_default_adv_cap_mask;
 297         uint32_t                ep_phy_cap_mask;
 298         boolean_t               ep_mac_drain;
 299         boolean_t               ep_mac_stats_pending;
 300 #if EFSYS_OPT_BIST
 301         efx_bist_type_t         ep_current_bist;
 302 #endif
 303         const efx_mac_ops_t     *ep_emop;
 304         const efx_phy_ops_t     *ep_epop;
 305 } efx_port_t;
 306
 307 typedef struct efx_mon_ops_s {
 308 #if EFSYS_OPT_MON_STATS
 309         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 310                                             efx_mon_stat_value_t *);
 311 #endif  /* EFSYS_OPT_MON_STATS */
 312 } efx_mon_ops_t;
 313
 314 typedef struct efx_mon_s {
 315         efx_mon_type_t          em_type;
 316         const efx_mon_ops_t     *em_emop;
 317 } efx_mon_t;
 318
 319 typedef struct efx_intr_ops_s {
 320         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 321         void            (*eio_enable)(efx_nic_t *);
 322         void            (*eio_disable)(efx_nic_t *);
 323         void            (*eio_disable_unlocked)(efx_nic_t *);
 324         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 325         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 326         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 327                                  boolean_t *);
 328         void            (*eio_fatal)(efx_nic_t *);
 329         void            (*eio_fini)(efx_nic_t *);
 330 } efx_intr_ops_t;
 331
 332 typedef struct efx_intr_s {
 333         const efx_intr_ops_t    *ei_eiop;
 334         efsys_mem_t             *ei_esmp;
 335         efx_intr_type_t         ei_type;
 336         unsigned int            ei_level;
 337 } efx_intr_t;
 338
 339 typedef struct efx_nic_ops_s {
 340         efx_rc_t        (*eno_probe)(efx_nic_t *);
 341         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 342         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 343         efx_rc_t        (*eno_reset)(efx_nic_t *);
 344         efx_rc_t        (*eno_init)(efx_nic_t *);
 345         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 346         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 347                                         uint32_t *, size_t *);
 348 #if EFSYS_OPT_DIAG
 349         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 350 #endif  /* EFSYS_OPT_DIAG */
 351         void            (*eno_fini)(efx_nic_t *);
 352         void            (*eno_unprobe)(efx_nic_t *);
 353 } efx_nic_ops_t;
 354
 355 #ifndef EFX_TXQ_LIMIT_TARGET
 356 #define EFX_TXQ_LIMIT_TARGET 259
 357 #endif
 358 #ifndef EFX_RXQ_LIMIT_TARGET
 359 #define EFX_RXQ_LIMIT_TARGET 512
 360 #endif
 361 #ifndef EFX_TXQ_DC_SIZE
 362 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 363 #endif
 364 #ifndef EFX_RXQ_DC_SIZE
 365 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 366 #endif
 367
 368 #if EFSYS_OPT_FILTER
 369
 370 #if EFSYS_OPT_SIENA
 371
 372 typedef struct siena_filter_spec_s {
 373         uint8_t         sfs_type;
 374         uint32_t        sfs_flags;
 375         uint32_t        sfs_dmaq_id;
 376         uint32_t        sfs_dword[3];
 377 } siena_filter_spec_t;
 378
 379 typedef enum siena_filter_type_e {
 380         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 381         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 382         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 383         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 384         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 385         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 386
 387         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 388         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 389         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 390         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 391         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 392         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 393
 394         EFX_SIENA_FILTER_NTYPES
 395 } siena_filter_type_t;
 396
 397 typedef enum siena_filter_tbl_id_e {
 398         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 399         EFX_SIENA_FILTER_TBL_RX_MAC,
 400         EFX_SIENA_FILTER_TBL_TX_IP,
 401         EFX_SIENA_FILTER_TBL_TX_MAC,
 402         EFX_SIENA_FILTER_NTBLS
 403 } siena_filter_tbl_id_t;
 404
 405 typedef struct siena_filter_tbl_s {
 406         int                     sft_size;       /* number of entries */
 407         int                     sft_used;       /* active count */
 408         uint32_t                *sft_bitmap;    /* active bitmap */
 409         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 410 } siena_filter_tbl_t;
 411
 412 typedef struct siena_filter_s {
 413         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 414         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 415 } siena_filter_t;
 416
 417 #endif  /* EFSYS_OPT_SIENA */
 418
 419 typedef struct efx_filter_s {
 420 #if EFSYS_OPT_SIENA
 421         siena_filter_t          *ef_siena_filter;
 422 #endif /* EFSYS_OPT_SIENA */
 423 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 424         ef10_filter_table_t     *ef_ef10_filter_table;
 425 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 426 } efx_filter_t;
 427
 428 #if EFSYS_OPT_SIENA
 429
 430 extern                  void
 431 siena_filter_tbl_clear(
 432         __in            efx_nic_t *enp,
 433         __in            siena_filter_tbl_id_t tbl);
 434
 435 #endif  /* EFSYS_OPT_SIENA */
 436
 437 #endif  /* EFSYS_OPT_FILTER */
 438
 439 #if EFSYS_OPT_MCDI
 440
 441 typedef struct efx_mcdi_ops_s {
 442         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 443         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 444                                         void *, size_t);
 445         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 446         boolean_t       (*emco_poll_response)(efx_nic_t *);
 447         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 448         void            (*emco_fini)(efx_nic_t *);
 449         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 450                                             efx_mcdi_feature_id_t, boolean_t *);
 451         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 452                                             uint32_t *);
 453 } efx_mcdi_ops_t;
 454
 455 typedef struct efx_mcdi_s {
 456         const efx_mcdi_ops_t            *em_emcop;
 457         const efx_mcdi_transport_t      *em_emtp;
 458         efx_mcdi_iface_t                em_emip;
 459 } efx_mcdi_t;
 460
 461 #endif /* EFSYS_OPT_MCDI */
 462
 463 #if EFSYS_OPT_NVRAM
 464
 465 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 466 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 467
 468 typedef struct efx_nvram_ops_s {
 469 #if EFSYS_OPT_DIAG
 470         efx_rc_t        (*envo_test)(efx_nic_t *);
 471 #endif  /* EFSYS_OPT_DIAG */
 472         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 473                                             uint32_t *);
 474         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 475         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 476         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 477                                             unsigned int, caddr_t, size_t);
 478         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 479                                             unsigned int, caddr_t, size_t);
 480         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 481                                             unsigned int, size_t);
 482         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 483                                             unsigned int, caddr_t, size_t);
 484         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 485                                             uint32_t *);
 486         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 487                                             uint32_t *, uint16_t *);
 488         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 489                                             uint16_t *);
 490         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 491                                             caddr_t, size_t);
 492 } efx_nvram_ops_t;
 493 #endif /* EFSYS_OPT_NVRAM */
 494
 495 #if EFSYS_OPT_VPD
 496 typedef struct efx_vpd_ops_s {
 497         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 498         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 499         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 500         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 501         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 502         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 503                                         efx_vpd_value_t *);
 504         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 505                                         efx_vpd_value_t *);
 506         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 507                                         efx_vpd_value_t *, unsigned int *);
 508         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 509         void            (*evpdo_fini)(efx_nic_t *);
 510 } efx_vpd_ops_t;
 511 #endif  /* EFSYS_OPT_VPD */
 512
 513 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 514
 515         __checkReturn           efx_rc_t
 516 efx_mcdi_nvram_partitions(
 517         __in                    efx_nic_t *enp,
 518         __out_bcount(size)      caddr_t data,
 519         __in                    size_t size,
 520         __out                   unsigned int *npartnp);
 521
 522         __checkReturn           efx_rc_t
 523 efx_mcdi_nvram_metadata(
 524         __in                    efx_nic_t *enp,
 525         __in                    uint32_t partn,
 526         __out                   uint32_t *subtypep,
 527         __out_ecount(4)         uint16_t version[4],
 528         __out_bcount_opt(size)  char *descp,
 529         __in                    size_t size);
 530
 531         __checkReturn           efx_rc_t
 532 efx_mcdi_nvram_info(
 533         __in                    efx_nic_t *enp,
 534         __in                    uint32_t partn,
 535         __out_opt               size_t *sizep,
 536         __out_opt               uint32_t *addressp,
 537         __out_opt               uint32_t *erase_sizep,
 538         __out_opt               uint32_t *write_sizep);
 539
 540         __checkReturn           efx_rc_t
 541 efx_mcdi_nvram_update_start(
 542         __in                    efx_nic_t *enp,
 543         __in                    uint32_t partn);
 544
 545         __checkReturn           efx_rc_t
 546 efx_mcdi_nvram_read(
 547         __in                    efx_nic_t *enp,
 548         __in                    uint32_t partn,
 549         __in                    uint32_t offset,
 550         __out_bcount(size)      caddr_t data,
 551         __in                    size_t size,
 552         __in                    uint32_t mode);
 553
 554         __checkReturn           efx_rc_t
 555 efx_mcdi_nvram_erase(
 556         __in                    efx_nic_t *enp,
 557         __in                    uint32_t partn,
 558         __in                    uint32_t offset,
 559         __in                    size_t size);
 560
 561         __checkReturn           efx_rc_t
 562 efx_mcdi_nvram_write(
 563         __in                    efx_nic_t *enp,
 564         __in                    uint32_t partn,
 565         __in                    uint32_t offset,
 566         __out_bcount(size)      caddr_t data,
 567         __in                    size_t size);
 568
 569         __checkReturn           efx_rc_t
 570 efx_mcdi_nvram_update_finish(
 571         __in                    efx_nic_t *enp,
 572         __in                    uint32_t partn,
 573         __in                    boolean_t reboot,
 574         __out_opt               uint32_t *verify_resultp);
 575
 576 #if EFSYS_OPT_DIAG
 577
 578         __checkReturn           efx_rc_t
 579 efx_mcdi_nvram_test(
 580         __in                    efx_nic_t *enp,
 581         __in                    uint32_t partn);
 582
 583 #endif  /* EFSYS_OPT_DIAG */
 584
 585 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 586
 587 #if EFSYS_OPT_LICENSING
 588
 589 typedef struct efx_lic_ops_s {
 590         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 591         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 592         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 593         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 594                                       size_t *, uint8_t *);
 595         efx_rc_t        (*elo_find_start)
 596                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 597         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 598                                 uint32_t, uint32_t *);
 599         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 600                                 uint32_t, uint32_t *, uint32_t *);
 601         boolean_t       (*elo_validate_key)(efx_nic_t *,
 602                                 caddr_t, uint32_t);
 603         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 604                                 caddr_t, size_t, uint32_t, uint32_t,
 605                                 caddr_t, size_t, uint32_t *);
 606         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 607                                 caddr_t, size_t, uint32_t,
 608                                 caddr_t, uint32_t, uint32_t *);
 609         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 610                                 caddr_t, size_t, uint32_t,
 611                                 uint32_t, uint32_t, uint32_t *);
 612         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 613                                 caddr_t, size_t);
 614         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 615                                 caddr_t, size_t);
 616 } efx_lic_ops_t;
 617
 618 #endif
 619
 620 typedef struct efx_drv_cfg_s {
 621         uint32_t                edc_min_vi_count;
 622         uint32_t                edc_max_vi_count;
 623
 624         uint32_t                edc_max_piobuf_count;
 625         uint32_t                edc_pio_alloc_size;
 626 } efx_drv_cfg_t;
 627
 628 struct efx_nic_s {
 629         uint32_t                en_magic;
 630         efx_family_t            en_family;
 631         uint32_t                en_features;
 632         efsys_identifier_t      *en_esip;
 633         efsys_lock_t            *en_eslp;
 634         efsys_bar_t             *en_esbp;
 635         unsigned int            en_mod_flags;
 636         unsigned int            en_reset_flags;
 637         efx_nic_cfg_t           en_nic_cfg;
 638         efx_drv_cfg_t           en_drv_cfg;
 639         efx_port_t              en_port;
 640         efx_mon_t               en_mon;
 641         efx_intr_t              en_intr;
 642         uint32_t                en_ev_qcount;
 643         uint32_t                en_rx_qcount;
 644         uint32_t                en_tx_qcount;
 645         const efx_nic_ops_t     *en_enop;
 646         const efx_ev_ops_t      *en_eevop;
 647         const efx_tx_ops_t      *en_etxop;
 648         const efx_rx_ops_t      *en_erxop;
 649 #if EFSYS_OPT_FILTER
 650         efx_filter_t            en_filter;
 651         const efx_filter_ops_t  *en_efop;
 652 #endif  /* EFSYS_OPT_FILTER */
 653 #if EFSYS_OPT_MCDI
 654         efx_mcdi_t              en_mcdi;
 655 #endif  /* EFSYS_OPT_MCDI */
 656 #if EFSYS_OPT_NVRAM
 657         uint32_t                en_nvram_partn_locked;
 658         const efx_nvram_ops_t   *en_envop;
 659 #endif  /* EFSYS_OPT_NVRAM */
 660 #if EFSYS_OPT_VPD
 661         const efx_vpd_ops_t     *en_evpdop;
 662 #endif  /* EFSYS_OPT_VPD */
 663 #if EFSYS_OPT_RX_SCALE
 664         efx_rx_hash_support_t           en_hash_support;
 665         efx_rx_scale_context_type_t     en_rss_context_type;
 666         uint32_t                        en_rss_context;
 667 #endif  /* EFSYS_OPT_RX_SCALE */
 668         uint32_t                en_vport_id;
 669 #if EFSYS_OPT_LICENSING
 670         const efx_lic_ops_t     *en_elop;
 671         boolean_t               en_licensing_supported;
 672 #endif
 673         union {
 674 #if EFSYS_OPT_SIENA
 675                 struct {
 676 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 677                         unsigned int            enu_partn_mask;
 678 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 679 #if EFSYS_OPT_VPD
 680                         caddr_t                 enu_svpd;
 681                         size_t                  enu_svpd_length;
 682 #endif  /* EFSYS_OPT_VPD */
 683                         int                     enu_unused;
 684                 } siena;
 685 #endif  /* EFSYS_OPT_SIENA */
 686                 int     enu_unused;
 687         } en_u;
 688 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 689         union en_arch {
 690                 struct {
 691                         int                     ena_vi_base;
 692                         int                     ena_vi_count;
 693                         int                     ena_vi_shift;
 694 #if EFSYS_OPT_VPD
 695                         caddr_t                 ena_svpd;
 696                         size_t                  ena_svpd_length;
 697 #endif  /* EFSYS_OPT_VPD */
 698                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 699                         uint32_t                ena_piobuf_count;
 700                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 701                         uint32_t                ena_pio_write_vi_base;
 702                         /* Memory BAR mapping regions */
 703                         uint32_t                ena_uc_mem_map_offset;
 704                         size_t                  ena_uc_mem_map_size;
 705                         uint32_t                ena_wc_mem_map_offset;
 706                         size_t                  ena_wc_mem_map_size;
 707                 } ef10;
 708         } en_arch;
 709 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 710 };
 711
 712
 713 #define EFX_NIC_MAGIC   0x02121996
 714
 715 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 716     const efx_ev_callbacks_t *, void *);
 717
 718 typedef struct efx_evq_rxq_state_s {
 719         unsigned int                    eers_rx_read_ptr;
 720         unsigned int                    eers_rx_mask;
 721 #if EFSYS_OPT_RX_PACKED_STREAM
 722         unsigned int                    eers_rx_stream_npackets;
 723         boolean_t                       eers_rx_packed_stream;
 724         unsigned int                    eers_rx_packed_stream_credits;
 725 #endif
 726 } efx_evq_rxq_state_t;
 727
 728 struct efx_evq_s {
 729         uint32_t                        ee_magic;
 730         efx_nic_t                       *ee_enp;
 731         unsigned int                    ee_index;
 732         unsigned int                    ee_mask;
 733         efsys_mem_t                     *ee_esmp;
 734 #if EFSYS_OPT_QSTATS
 735         uint32_t                        ee_stat[EV_NQSTATS];
 736 #endif  /* EFSYS_OPT_QSTATS */
 737
 738         efx_ev_handler_t                ee_rx;
 739         efx_ev_handler_t                ee_tx;
 740         efx_ev_handler_t                ee_driver;
 741         efx_ev_handler_t                ee_global;
 742         efx_ev_handler_t                ee_drv_gen;
 743 #if EFSYS_OPT_MCDI
 744         efx_ev_handler_t                ee_mcdi;
 745 #endif  /* EFSYS_OPT_MCDI */
 746
 747         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 748
 749         uint32_t                        ee_flags;
 750 };
 751
 752 #define EFX_EVQ_MAGIC   0x08081997
 753
 754 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 755
 756 struct efx_rxq_s {
 757         uint32_t                        er_magic;
 758         efx_nic_t                       *er_enp;
 759         efx_evq_t                       *er_eep;
 760         unsigned int                    er_index;
 761         unsigned int                    er_label;
 762         unsigned int                    er_mask;
 763         efsys_mem_t                     *er_esmp;
 764         efx_evq_rxq_state_t             *er_ev_qstate;
 765 };
 766
 767 #define EFX_RXQ_MAGIC   0x15022005
 768
 769 struct efx_txq_s {
 770         uint32_t                        et_magic;
 771         efx_nic_t                       *et_enp;
 772         unsigned int                    et_index;
 773         unsigned int                    et_mask;
 774         efsys_mem_t                     *et_esmp;
 775 #if EFSYS_OPT_HUNTINGTON
 776         uint32_t                        et_pio_bufnum;
 777         uint32_t                        et_pio_blknum;
 778         uint32_t                        et_pio_write_offset;
 779         uint32_t                        et_pio_offset;
 780         size_t                          et_pio_size;
 781 #endif
 782 #if EFSYS_OPT_QSTATS
 783         uint32_t                        et_stat[TX_NQSTATS];
 784 #endif  /* EFSYS_OPT_QSTATS */
 785 };
 786
 787 #define EFX_TXQ_MAGIC   0x05092005
 788
 789 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 790         do {                                                            \
 791                 (_dst)[0] = (_src)[0];                                  \
 792                 (_dst)[1] = (_src)[1];                                  \
 793                 (_dst)[2] = (_src)[2];                                  \
 794                 (_dst)[3] = (_src)[3];                                  \
 795                 (_dst)[4] = (_src)[4];                                  \
 796                 (_dst)[5] = (_src)[5];                                  \
 797         _NOTE(CONSTANTCONDITION)                                        \
 798         } while (B_FALSE)
 799
 800 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 801         do {                                                            \
 802                 uint16_t *_d = (uint16_t *)(_dst);                      \
 803                 _d[0] = 0xffff;                                         \
 804                 _d[1] = 0xffff;                                         \
 805                 _d[2] = 0xffff;                                         \
 806         _NOTE(CONSTANTCONDITION)                                        \
 807         } while (B_FALSE)
 808
 809 #if EFSYS_OPT_CHECK_REG
 810 #define EFX_CHECK_REG(_enp, _reg)                                       \
 811         do {                                                            \
 812                 const char *name = #_reg;                               \
 813                 char min = name[4];                                     \
 814                 char max = name[5];                                     \
 815                 char rev;                                               \
 816                                                                         \
 817                 switch ((_enp)->en_family) {                            \
 818                 case EFX_FAMILY_SIENA:                                  \
 819                         rev = 'C';                                      \
 820                         break;                                          \
 821                                                                         \
 822                 case EFX_FAMILY_HUNTINGTON:                             \
 823                         rev = 'D';                                      \
 824                         break;                                          \
 825                                                                         \
 826                 case EFX_FAMILY_MEDFORD:                                \
 827                         rev = 'E';                                      \
 828                         break;                                          \
 829                                                                         \
 830                 default:                                                \
 831                         rev = '?';                                      \
 832                         break;                                          \
 833                 }                                                       \
 834                                                                         \
 835                 EFSYS_ASSERT3S(rev, >=, min);                           \
 836                 EFSYS_ASSERT3S(rev, <=, max);                           \
 837                                                                         \
 838         _NOTE(CONSTANTCONDITION)                                        \
 839         } while (B_FALSE)
 840 #else
 841 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 842         _NOTE(CONSTANTCONDITION)                                        \
 843         } while (B_FALSE)
 844 #endif
 845
 846 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 847         do {                                                            \
 848                 EFX_CHECK_REG((_enp), (_reg));                          \
 849                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 850                     (_edp), (_lock));                                   \
 851                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 852                     uint32_t, _reg ## _OFST,                            \
 853                     uint32_t, (_edp)->ed_u32[0]);                       \
 854         _NOTE(CONSTANTCONDITION)                                        \
 855         } while (B_FALSE)
 856
 857 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 858         do {                                                            \
 859                 EFX_CHECK_REG((_enp), (_reg));                          \
 860                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 861                     uint32_t, _reg ## _OFST,                            \
 862                     uint32_t, (_edp)->ed_u32[0]);                       \
 863                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 864                     (_edp), (_lock));                                   \
 865         _NOTE(CONSTANTCONDITION)                                        \
 866         } while (B_FALSE)
 867
 868 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 869         do {                                                            \
 870                 EFX_CHECK_REG((_enp), (_reg));                          \
 871                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 872                     (_eqp));                                            \
 873                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 874                     uint32_t, _reg ## _OFST,                            \
 875                     uint32_t, (_eqp)->eq_u32[1],                        \
 876                     uint32_t, (_eqp)->eq_u32[0]);                       \
 877         _NOTE(CONSTANTCONDITION)                                        \
 878         } while (B_FALSE)
 879
 880 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 881         do {                                                            \
 882                 EFX_CHECK_REG((_enp), (_reg));                          \
 883                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 884                     uint32_t, _reg ## _OFST,                            \
 885                     uint32_t, (_eqp)->eq_u32[1],                        \
 886                     uint32_t, (_eqp)->eq_u32[0]);                       \
 887                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 888                     (_eqp));                                            \
 889         _NOTE(CONSTANTCONDITION)                                        \
 890         } while (B_FALSE)
 891
 892 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 893         do {                                                            \
 894                 EFX_CHECK_REG((_enp), (_reg));                          \
 895                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 896                     (_eop), B_TRUE);                                    \
 897                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 898                     uint32_t, _reg ## _OFST,                            \
 899                     uint32_t, (_eop)->eo_u32[3],                        \
 900                     uint32_t, (_eop)->eo_u32[2],                        \
 901                     uint32_t, (_eop)->eo_u32[1],                        \
 902                     uint32_t, (_eop)->eo_u32[0]);                       \
 903         _NOTE(CONSTANTCONDITION)                                        \
 904         } while (B_FALSE)
 905
 906 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 907         do {                                                            \
 908                 EFX_CHECK_REG((_enp), (_reg));                          \
 909                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 910                     uint32_t, _reg ## _OFST,                            \
 911                     uint32_t, (_eop)->eo_u32[3],                        \
 912                     uint32_t, (_eop)->eo_u32[2],                        \
 913                     uint32_t, (_eop)->eo_u32[1],                        \
 914                     uint32_t, (_eop)->eo_u32[0]);                       \
 915                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 916                     (_eop), B_TRUE);                                    \
 917         _NOTE(CONSTANTCONDITION)                                        \
 918         } while (B_FALSE)
 919
 920 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 921         do {                                                            \
 922                 EFX_CHECK_REG((_enp), (_reg));                          \
 923                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 924                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 925                     (_edp), (_lock));                                   \
 926                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 927                     uint32_t, (_index),                                 \
 928                     uint32_t, _reg ## _OFST,                            \
 929                     uint32_t, (_edp)->ed_u32[0]);                       \
 930         _NOTE(CONSTANTCONDITION)                                        \
 931         } while (B_FALSE)
 932
 933 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 934         do {                                                            \
 935                 EFX_CHECK_REG((_enp), (_reg));                          \
 936                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 937                     uint32_t, (_index),                                 \
 938                     uint32_t, _reg ## _OFST,                            \
 939                     uint32_t, (_edp)->ed_u32[0]);                       \
 940                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 941                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 942                     (_edp), (_lock));                                   \
 943         _NOTE(CONSTANTCONDITION)                                        \
 944         } while (B_FALSE)
 945
 946 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 947         do {                                                            \
 948                 EFX_CHECK_REG((_enp), (_reg));                          \
 949                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 950                     uint32_t, (_index),                                 \
 951                     uint32_t, _reg ## _OFST,                            \
 952                     uint32_t, (_edp)->ed_u32[0]);                       \
 953                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 954                     (_reg ## _OFST +                                    \
 955                     (2 * sizeof (efx_dword_t)) +                        \
 956                     ((_index) * _reg ## _STEP)),                        \
 957                     (_edp), (_lock));                                   \
 958         _NOTE(CONSTANTCONDITION)                                        \
 959         } while (B_FALSE)
 960
 961 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 962         do {                                                            \
 963                 EFX_CHECK_REG((_enp), (_reg));                          \
 964                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 965                     uint32_t, (_index),                                 \
 966                     uint32_t, _reg ## _OFST,                            \
 967                     uint32_t, (_edp)->ed_u32[0]);                       \
 968                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 969                     (_reg ## _OFST +                                    \
 970                     (3 * sizeof (efx_dword_t)) +                        \
 971                     ((_index) * _reg ## _STEP)),                        \
 972                     (_edp), (_lock));                                   \
 973         _NOTE(CONSTANTCONDITION)                                        \
 974         } while (B_FALSE)
 975
 976 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 977         do {                                                            \
 978                 EFX_CHECK_REG((_enp), (_reg));                          \
 979                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 980                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 981                     (_eqp));                                            \
 982                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 983                     uint32_t, (_index),                                 \
 984                     uint32_t, _reg ## _OFST,                            \
 985                     uint32_t, (_eqp)->eq_u32[1],                        \
 986                     uint32_t, (_eqp)->eq_u32[0]);                       \
 987         _NOTE(CONSTANTCONDITION)                                        \
 988         } while (B_FALSE)
 989
 990 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 991         do {                                                            \
 992                 EFX_CHECK_REG((_enp), (_reg));                          \
 993                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 994                     uint32_t, (_index),                                 \
 995                     uint32_t, _reg ## _OFST,                            \
 996                     uint32_t, (_eqp)->eq_u32[1],                        \
 997                     uint32_t, (_eqp)->eq_u32[0]);                       \
 998                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 999                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1000                     (_eqp));                                            \
1001         _NOTE(CONSTANTCONDITION)                                        \
1002         } while (B_FALSE)
1003
1004 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1005         do {                                                            \
1006                 EFX_CHECK_REG((_enp), (_reg));                          \
1007                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1008                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1009                     (_eop), (_lock));                                   \
1010                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1011                     uint32_t, (_index),                                 \
1012                     uint32_t, _reg ## _OFST,                            \
1013                     uint32_t, (_eop)->eo_u32[3],                        \
1014                     uint32_t, (_eop)->eo_u32[2],                        \
1015                     uint32_t, (_eop)->eo_u32[1],                        \
1016                     uint32_t, (_eop)->eo_u32[0]);                       \
1017         _NOTE(CONSTANTCONDITION)                                        \
1018         } while (B_FALSE)
1019
1020 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1021         do {                                                            \
1022                 EFX_CHECK_REG((_enp), (_reg));                          \
1023                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1024                     uint32_t, (_index),                                 \
1025                     uint32_t, _reg ## _OFST,                            \
1026                     uint32_t, (_eop)->eo_u32[3],                        \
1027                     uint32_t, (_eop)->eo_u32[2],                        \
1028                     uint32_t, (_eop)->eo_u32[1],                        \
1029                     uint32_t, (_eop)->eo_u32[0]);                       \
1030                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1031                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1032                     (_eop), (_lock));                                   \
1033         _NOTE(CONSTANTCONDITION)                                        \
1034         } while (B_FALSE)
1035
1036 /*
1037  * Allow drivers to perform optimised 128-bit doorbell writes.
1038  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1039  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1040  * the need for locking in the host, and are the only ones known to be safe to
1041  * use 128-bites write with.
1042  */
1043 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1044         do {                                                            \
1045                 EFX_CHECK_REG((_enp), (_reg));                          \
1046                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1047                     const char *,                                       \
1048                     #_reg,                                              \
1049                     uint32_t, (_index),                                 \
1050                     uint32_t, _reg ## _OFST,                            \
1051                     uint32_t, (_eop)->eo_u32[3],                        \
1052                     uint32_t, (_eop)->eo_u32[2],                        \
1053                     uint32_t, (_eop)->eo_u32[1],                        \
1054                     uint32_t, (_eop)->eo_u32[0]);                       \
1055                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1056                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1057                     (_eop));                                            \
1058         _NOTE(CONSTANTCONDITION)                                        \
1059         } while (B_FALSE)
1060
1061 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1062         do {                                                            \
1063                 unsigned int _new = (_wptr);                            \
1064                 unsigned int _old = (_owptr);                           \
1065                                                                         \
1066                 if ((_new) >= (_old))                                   \
1067                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1068                             (_old) * sizeof (efx_desc_t),               \
1069                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1070                 else                                                    \
1071                         /*                                              \
1072                          * It is cheaper to sync entire map than sync   \
1073                          * two parts especially when offset/size are    \
1074                          * ignored and entire map is synced in any case.\
1075                          */                                             \
1076                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1077                             0,                                          \
1078                             (_entries) * sizeof (efx_desc_t));          \
1079         _NOTE(CONSTANTCONDITION)                                        \
1080         } while (B_FALSE)
1081
1082 extern  __checkReturn   efx_rc_t
1083 efx_nic_biu_test(
1084         __in            efx_nic_t *enp);
1085
1086 extern  __checkReturn   efx_rc_t
1087 efx_mac_select(
1088         __in            efx_nic_t *enp);
1089
1090 extern  void
1091 efx_mac_multicast_hash_compute(
1092         __in_ecount(6*count)            uint8_t const *addrs,
1093         __in                            int count,
1094         __out                           efx_oword_t *hash_low,
1095         __out                           efx_oword_t *hash_high);
1096
1097 extern  __checkReturn   efx_rc_t
1098 efx_phy_probe(
1099         __in            efx_nic_t *enp);
1100
1101 extern                  void
1102 efx_phy_unprobe(
1103         __in            efx_nic_t *enp);
1104
1105 #if EFSYS_OPT_VPD
1106
1107 /* VPD utility functions */
1108
1109 extern  __checkReturn           efx_rc_t
1110 efx_vpd_hunk_length(
1111         __in_bcount(size)       caddr_t data,
1112         __in                    size_t size,
1113         __out                   size_t *lengthp);
1114
1115 extern  __checkReturn           efx_rc_t
1116 efx_vpd_hunk_verify(
1117         __in_bcount(size)       caddr_t data,
1118         __in                    size_t size,
1119         __out_opt               boolean_t *cksummedp);
1120
1121 extern  __checkReturn           efx_rc_t
1122 efx_vpd_hunk_reinit(
1123         __in_bcount(size)       caddr_t data,
1124         __in                    size_t size,
1125         __in                    boolean_t wantpid);
1126
1127 extern  __checkReturn           efx_rc_t
1128 efx_vpd_hunk_get(
1129         __in_bcount(size)       caddr_t data,
1130         __in                    size_t size,
1131         __in                    efx_vpd_tag_t tag,
1132         __in                    efx_vpd_keyword_t keyword,
1133         __out                   unsigned int *payloadp,
1134         __out                   uint8_t *paylenp);
1135
1136 extern  __checkReturn                   efx_rc_t
1137 efx_vpd_hunk_next(
1138         __in_bcount(size)               caddr_t data,
1139         __in                            size_t size,
1140         __out                           efx_vpd_tag_t *tagp,
1141         __out                           efx_vpd_keyword_t *keyword,
1142         __out_opt                       unsigned int *payloadp,
1143         __out_opt                       uint8_t *paylenp,
1144         __inout                         unsigned int *contp);
1145
1146 extern  __checkReturn           efx_rc_t
1147 efx_vpd_hunk_set(
1148         __in_bcount(size)       caddr_t data,
1149         __in                    size_t size,
1150         __in                    efx_vpd_value_t *evvp);
1151
1152 #endif  /* EFSYS_OPT_VPD */
1153
1154 #if EFSYS_OPT_DIAG
1155
1156 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1157
1158 typedef struct efx_register_set_s {
1159         unsigned int            address;
1160         unsigned int            step;
1161         unsigned int            rows;
1162         efx_oword_t             mask;
1163 } efx_register_set_t;
1164
1165 extern  __checkReturn   efx_rc_t
1166 efx_nic_test_registers(
1167         __in            efx_nic_t *enp,
1168         __in            efx_register_set_t *rsp,
1169         __in            size_t count);
1170
1171 extern  __checkReturn   efx_rc_t
1172 efx_nic_test_tables(
1173         __in            efx_nic_t *enp,
1174         __in            efx_register_set_t *rsp,
1175         __in            efx_pattern_type_t pattern,
1176         __in            size_t count);
1177
1178 #endif  /* EFSYS_OPT_DIAG */
1179
1180 #if EFSYS_OPT_MCDI
1181
1182 extern  __checkReturn           efx_rc_t
1183 efx_mcdi_set_workaround(
1184         __in                    efx_nic_t *enp,
1185         __in                    uint32_t type,
1186         __in                    boolean_t enabled,
1187         __out_opt               uint32_t *flagsp);
1188
1189 extern  __checkReturn           efx_rc_t
1190 efx_mcdi_get_workarounds(
1191         __in                    efx_nic_t *enp,
1192         __out_opt               uint32_t *implementedp,
1193         __out_opt               uint32_t *enabledp);
1194
1195 #endif /* EFSYS_OPT_MCDI */
1196
1197 #if EFSYS_OPT_MAC_STATS
1198
1199 /*
1200  * Closed range of stats (i.e. the first and the last are included).
1201  * The last must be greater or equal (if the range is one item only) to
1202  * the first.
1203  */
1204 struct efx_mac_stats_range {
1205         efx_mac_stat_t          first;
1206         efx_mac_stat_t          last;
1207 };
1208
1209 extern                                  efx_rc_t
1210 efx_mac_stats_mask_add_ranges(
1211         __inout_bcount(mask_size)       uint32_t *maskp,
1212         __in                            size_t mask_size,
1213         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1214         __in                            unsigned int rng_count);
1215
1216 #endif  /* EFSYS_OPT_MAC_STATS */
1217
1218 #ifdef  __cplusplus
1219 }
1220 #endif
1221
1222 #endif  /* _SYS_EFX_IMPL_H */