2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_FILTER 0x00001000
76 #define EFX_MOD_LIC 0x00002000
78 #define EFX_RESET_PHY 0x00000001
79 #define EFX_RESET_RXQ_ERR 0x00000002
80 #define EFX_RESET_TXQ_ERR 0x00000004
82 typedef enum efx_mac_type_e {
90 typedef struct efx_ev_ops_s {
91 efx_rc_t (*eevo_init)(efx_nic_t *);
92 void (*eevo_fini)(efx_nic_t *);
93 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
94 efsys_mem_t *, size_t, uint32_t,
95 uint32_t, uint32_t, efx_evq_t *);
96 void (*eevo_qdestroy)(efx_evq_t *);
97 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
98 void (*eevo_qpost)(efx_evq_t *, uint16_t);
99 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
101 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
105 typedef struct efx_tx_ops_s {
106 efx_rc_t (*etxo_init)(efx_nic_t *);
107 void (*etxo_fini)(efx_nic_t *);
108 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
109 unsigned int, unsigned int,
110 efsys_mem_t *, size_t,
112 efx_evq_t *, efx_txq_t *,
114 void (*etxo_qdestroy)(efx_txq_t *);
115 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
116 unsigned int, unsigned int,
118 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
119 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
120 efx_rc_t (*etxo_qflush)(efx_txq_t *);
121 void (*etxo_qenable)(efx_txq_t *);
122 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
123 void (*etxo_qpio_disable)(efx_txq_t *);
124 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
126 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
128 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
129 unsigned int, unsigned int,
131 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143 void (*etxo_qstats_update)(efx_txq_t *,
148 typedef struct efx_rx_ops_s {
149 efx_rc_t (*erxo_init)(efx_nic_t *);
150 void (*erxo_fini)(efx_nic_t *);
151 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
153 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
154 unsigned int, unsigned int,
156 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
157 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
158 void (*erxo_qenable)(efx_rxq_t *);
159 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
160 unsigned int, efx_rxq_type_t,
161 efsys_mem_t *, size_t, uint32_t,
162 efx_evq_t *, efx_rxq_t *);
163 void (*erxo_qdestroy)(efx_rxq_t *);
166 typedef struct efx_mac_ops_s {
167 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
168 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
169 efx_rc_t (*emo_addr_set)(efx_nic_t *);
170 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
171 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
172 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
173 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
174 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
175 efx_rxq_t *, boolean_t);
176 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
179 typedef struct efx_phy_ops_s {
180 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
181 efx_rc_t (*epo_reset)(efx_nic_t *);
182 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
183 efx_rc_t (*epo_verify)(efx_nic_t *);
184 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
185 #if EFSYS_OPT_PHY_STATS
186 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
188 #endif /* EFSYS_OPT_PHY_STATS */
190 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
191 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
192 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
193 efx_bist_result_t *, uint32_t *,
194 unsigned long *, size_t);
195 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
196 #endif /* EFSYS_OPT_BIST */
200 typedef struct efx_filter_ops_s {
201 efx_rc_t (*efo_init)(efx_nic_t *);
202 void (*efo_fini)(efx_nic_t *);
203 efx_rc_t (*efo_restore)(efx_nic_t *);
204 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
205 boolean_t may_replace);
206 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
207 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
208 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
209 boolean_t, boolean_t, boolean_t,
210 uint8_t const *, uint32_t);
213 extern __checkReturn efx_rc_t
214 efx_filter_reconfigure(
216 __in_ecount(6) uint8_t const *mac_addr,
217 __in boolean_t all_unicst,
218 __in boolean_t mulcst,
219 __in boolean_t all_mulcst,
220 __in boolean_t brdcst,
221 __in_ecount(6*count) uint8_t const *addrs,
222 __in uint32_t count);
224 #endif /* EFSYS_OPT_FILTER */
227 typedef struct efx_port_s {
228 efx_mac_type_t ep_mac_type;
229 uint32_t ep_phy_type;
232 uint8_t ep_mac_addr[6];
233 efx_link_mode_t ep_link_mode;
234 boolean_t ep_all_unicst;
236 boolean_t ep_all_mulcst;
238 unsigned int ep_fcntl;
239 boolean_t ep_fcntl_autoneg;
240 efx_oword_t ep_multicst_hash[2];
241 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
242 EFX_MAC_MULTICAST_LIST_MAX];
243 uint32_t ep_mulcst_addr_count;
244 #if EFSYS_OPT_PHY_FLAGS
245 uint32_t ep_phy_flags;
246 #endif /* EFSYS_OPT_PHY_FLAGS */
247 efx_phy_media_type_t ep_fixed_port_type;
248 efx_phy_media_type_t ep_module_type;
249 uint32_t ep_adv_cap_mask;
250 uint32_t ep_lp_cap_mask;
251 uint32_t ep_default_adv_cap_mask;
252 uint32_t ep_phy_cap_mask;
253 boolean_t ep_mac_drain;
254 boolean_t ep_mac_stats_pending;
256 efx_bist_type_t ep_current_bist;
258 const efx_mac_ops_t *ep_emop;
259 const efx_phy_ops_t *ep_epop;
262 typedef struct efx_mon_ops_s {
265 typedef struct efx_mon_s {
266 efx_mon_type_t em_type;
267 const efx_mon_ops_t *em_emop;
270 typedef struct efx_intr_ops_s {
271 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
272 void (*eio_enable)(efx_nic_t *);
273 void (*eio_disable)(efx_nic_t *);
274 void (*eio_disable_unlocked)(efx_nic_t *);
275 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
276 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
277 void (*eio_status_message)(efx_nic_t *, unsigned int,
279 void (*eio_fatal)(efx_nic_t *);
280 void (*eio_fini)(efx_nic_t *);
283 typedef struct efx_intr_s {
284 const efx_intr_ops_t *ei_eiop;
285 efsys_mem_t *ei_esmp;
286 efx_intr_type_t ei_type;
287 unsigned int ei_level;
290 typedef struct efx_nic_ops_s {
291 efx_rc_t (*eno_probe)(efx_nic_t *);
292 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
293 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
294 efx_rc_t (*eno_reset)(efx_nic_t *);
295 efx_rc_t (*eno_init)(efx_nic_t *);
296 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
297 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
298 uint32_t *, size_t *);
300 efx_rc_t (*eno_register_test)(efx_nic_t *);
301 #endif /* EFSYS_OPT_DIAG */
302 void (*eno_fini)(efx_nic_t *);
303 void (*eno_unprobe)(efx_nic_t *);
306 #ifndef EFX_TXQ_LIMIT_TARGET
307 #define EFX_TXQ_LIMIT_TARGET 259
309 #ifndef EFX_RXQ_LIMIT_TARGET
310 #define EFX_RXQ_LIMIT_TARGET 512
312 #ifndef EFX_TXQ_DC_SIZE
313 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
315 #ifndef EFX_RXQ_DC_SIZE
316 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
323 typedef struct siena_filter_spec_s {
326 uint32_t sfs_dmaq_id;
327 uint32_t sfs_dword[3];
328 } siena_filter_spec_t;
330 typedef enum siena_filter_type_e {
331 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
332 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
333 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
334 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
335 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
336 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
338 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
339 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
340 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
341 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
342 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
343 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
345 EFX_SIENA_FILTER_NTYPES
346 } siena_filter_type_t;
348 typedef enum siena_filter_tbl_id_e {
349 EFX_SIENA_FILTER_TBL_RX_IP = 0,
350 EFX_SIENA_FILTER_TBL_RX_MAC,
351 EFX_SIENA_FILTER_TBL_TX_IP,
352 EFX_SIENA_FILTER_TBL_TX_MAC,
353 EFX_SIENA_FILTER_NTBLS
354 } siena_filter_tbl_id_t;
356 typedef struct siena_filter_tbl_s {
357 int sft_size; /* number of entries */
358 int sft_used; /* active count */
359 uint32_t *sft_bitmap; /* active bitmap */
360 siena_filter_spec_t *sft_spec; /* array of saved specs */
361 } siena_filter_tbl_t;
363 typedef struct siena_filter_s {
364 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
365 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
368 #endif /* EFSYS_OPT_SIENA */
370 typedef struct efx_filter_s {
372 siena_filter_t *ef_siena_filter;
373 #endif /* EFSYS_OPT_SIENA */
374 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
375 ef10_filter_table_t *ef_ef10_filter_table;
376 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
382 siena_filter_tbl_clear(
384 __in siena_filter_tbl_id_t tbl);
386 #endif /* EFSYS_OPT_SIENA */
388 #endif /* EFSYS_OPT_FILTER */
392 typedef struct efx_mcdi_ops_s {
393 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
394 void (*emco_send_request)(efx_nic_t *, void *, size_t,
396 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
397 boolean_t (*emco_poll_response)(efx_nic_t *);
398 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
399 void (*emco_fini)(efx_nic_t *);
400 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
401 efx_mcdi_feature_id_t, boolean_t *);
402 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
406 typedef struct efx_mcdi_s {
407 const efx_mcdi_ops_t *em_emcop;
408 const efx_mcdi_transport_t *em_emtp;
409 efx_mcdi_iface_t em_emip;
412 #endif /* EFSYS_OPT_MCDI */
414 typedef struct efx_drv_cfg_s {
415 uint32_t edc_min_vi_count;
416 uint32_t edc_max_vi_count;
418 uint32_t edc_max_piobuf_count;
419 uint32_t edc_pio_alloc_size;
424 efx_family_t en_family;
425 uint32_t en_features;
426 efsys_identifier_t *en_esip;
427 efsys_lock_t *en_eslp;
428 efsys_bar_t *en_esbp;
429 unsigned int en_mod_flags;
430 unsigned int en_reset_flags;
431 efx_nic_cfg_t en_nic_cfg;
432 efx_drv_cfg_t en_drv_cfg;
436 uint32_t en_ev_qcount;
437 uint32_t en_rx_qcount;
438 uint32_t en_tx_qcount;
439 const efx_nic_ops_t *en_enop;
440 const efx_ev_ops_t *en_eevop;
441 const efx_tx_ops_t *en_etxop;
442 const efx_rx_ops_t *en_erxop;
444 efx_filter_t en_filter;
445 const efx_filter_ops_t *en_efop;
446 #endif /* EFSYS_OPT_FILTER */
449 #endif /* EFSYS_OPT_MCDI */
450 uint32_t en_vport_id;
456 #endif /* EFSYS_OPT_SIENA */
459 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
465 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
466 uint32_t ena_piobuf_count;
467 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
468 uint32_t ena_pio_write_vi_base;
469 /* Memory BAR mapping regions */
470 uint32_t ena_uc_mem_map_offset;
471 size_t ena_uc_mem_map_size;
472 uint32_t ena_wc_mem_map_offset;
473 size_t ena_wc_mem_map_size;
476 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
480 #define EFX_NIC_MAGIC 0x02121996
482 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
483 const efx_ev_callbacks_t *, void *);
485 typedef struct efx_evq_rxq_state_s {
486 unsigned int eers_rx_read_ptr;
487 unsigned int eers_rx_mask;
488 } efx_evq_rxq_state_t;
493 unsigned int ee_index;
494 unsigned int ee_mask;
495 efsys_mem_t *ee_esmp;
497 uint32_t ee_stat[EV_NQSTATS];
498 #endif /* EFSYS_OPT_QSTATS */
500 efx_ev_handler_t ee_rx;
501 efx_ev_handler_t ee_tx;
502 efx_ev_handler_t ee_driver;
503 efx_ev_handler_t ee_global;
504 efx_ev_handler_t ee_drv_gen;
506 efx_ev_handler_t ee_mcdi;
507 #endif /* EFSYS_OPT_MCDI */
509 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
514 #define EFX_EVQ_MAGIC 0x08081997
516 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
522 unsigned int er_index;
523 unsigned int er_label;
524 unsigned int er_mask;
525 efsys_mem_t *er_esmp;
528 #define EFX_RXQ_MAGIC 0x15022005
533 unsigned int et_index;
534 unsigned int et_mask;
535 efsys_mem_t *et_esmp;
536 #if EFSYS_OPT_HUNTINGTON
537 uint32_t et_pio_bufnum;
538 uint32_t et_pio_blknum;
539 uint32_t et_pio_write_offset;
540 uint32_t et_pio_offset;
544 uint32_t et_stat[TX_NQSTATS];
545 #endif /* EFSYS_OPT_QSTATS */
548 #define EFX_TXQ_MAGIC 0x05092005
550 #define EFX_MAC_ADDR_COPY(_dst, _src) \
552 (_dst)[0] = (_src)[0]; \
553 (_dst)[1] = (_src)[1]; \
554 (_dst)[2] = (_src)[2]; \
555 (_dst)[3] = (_src)[3]; \
556 (_dst)[4] = (_src)[4]; \
557 (_dst)[5] = (_src)[5]; \
558 _NOTE(CONSTANTCONDITION) \
561 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
563 uint16_t *_d = (uint16_t *)(_dst); \
567 _NOTE(CONSTANTCONDITION) \
570 #if EFSYS_OPT_CHECK_REG
571 #define EFX_CHECK_REG(_enp, _reg) \
573 const char *name = #_reg; \
574 char min = name[4]; \
575 char max = name[5]; \
578 switch ((_enp)->en_family) { \
579 case EFX_FAMILY_SIENA: \
583 case EFX_FAMILY_HUNTINGTON: \
587 case EFX_FAMILY_MEDFORD: \
596 EFSYS_ASSERT3S(rev, >=, min); \
597 EFSYS_ASSERT3S(rev, <=, max); \
599 _NOTE(CONSTANTCONDITION) \
602 #define EFX_CHECK_REG(_enp, _reg) do { \
603 _NOTE(CONSTANTCONDITION) \
607 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
609 EFX_CHECK_REG((_enp), (_reg)); \
610 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
612 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
613 uint32_t, _reg ## _OFST, \
614 uint32_t, (_edp)->ed_u32[0]); \
615 _NOTE(CONSTANTCONDITION) \
618 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
620 EFX_CHECK_REG((_enp), (_reg)); \
621 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
622 uint32_t, _reg ## _OFST, \
623 uint32_t, (_edp)->ed_u32[0]); \
624 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
626 _NOTE(CONSTANTCONDITION) \
629 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
631 EFX_CHECK_REG((_enp), (_reg)); \
632 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
634 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
635 uint32_t, _reg ## _OFST, \
636 uint32_t, (_eqp)->eq_u32[1], \
637 uint32_t, (_eqp)->eq_u32[0]); \
638 _NOTE(CONSTANTCONDITION) \
641 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
643 EFX_CHECK_REG((_enp), (_reg)); \
644 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
645 uint32_t, _reg ## _OFST, \
646 uint32_t, (_eqp)->eq_u32[1], \
647 uint32_t, (_eqp)->eq_u32[0]); \
648 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
650 _NOTE(CONSTANTCONDITION) \
653 #define EFX_BAR_READO(_enp, _reg, _eop) \
655 EFX_CHECK_REG((_enp), (_reg)); \
656 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
658 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
659 uint32_t, _reg ## _OFST, \
660 uint32_t, (_eop)->eo_u32[3], \
661 uint32_t, (_eop)->eo_u32[2], \
662 uint32_t, (_eop)->eo_u32[1], \
663 uint32_t, (_eop)->eo_u32[0]); \
664 _NOTE(CONSTANTCONDITION) \
667 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
669 EFX_CHECK_REG((_enp), (_reg)); \
670 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
671 uint32_t, _reg ## _OFST, \
672 uint32_t, (_eop)->eo_u32[3], \
673 uint32_t, (_eop)->eo_u32[2], \
674 uint32_t, (_eop)->eo_u32[1], \
675 uint32_t, (_eop)->eo_u32[0]); \
676 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
678 _NOTE(CONSTANTCONDITION) \
681 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
683 EFX_CHECK_REG((_enp), (_reg)); \
684 EFSYS_BAR_READD((_enp)->en_esbp, \
685 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
687 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
688 uint32_t, (_index), \
689 uint32_t, _reg ## _OFST, \
690 uint32_t, (_edp)->ed_u32[0]); \
691 _NOTE(CONSTANTCONDITION) \
694 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
696 EFX_CHECK_REG((_enp), (_reg)); \
697 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
698 uint32_t, (_index), \
699 uint32_t, _reg ## _OFST, \
700 uint32_t, (_edp)->ed_u32[0]); \
701 EFSYS_BAR_WRITED((_enp)->en_esbp, \
702 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
704 _NOTE(CONSTANTCONDITION) \
707 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
709 EFX_CHECK_REG((_enp), (_reg)); \
710 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
711 uint32_t, (_index), \
712 uint32_t, _reg ## _OFST, \
713 uint32_t, (_edp)->ed_u32[0]); \
714 EFSYS_BAR_WRITED((_enp)->en_esbp, \
716 (2 * sizeof (efx_dword_t)) + \
717 ((_index) * _reg ## _STEP)), \
719 _NOTE(CONSTANTCONDITION) \
722 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
724 EFX_CHECK_REG((_enp), (_reg)); \
725 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
726 uint32_t, (_index), \
727 uint32_t, _reg ## _OFST, \
728 uint32_t, (_edp)->ed_u32[0]); \
729 EFSYS_BAR_WRITED((_enp)->en_esbp, \
731 (3 * sizeof (efx_dword_t)) + \
732 ((_index) * _reg ## _STEP)), \
734 _NOTE(CONSTANTCONDITION) \
737 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
739 EFX_CHECK_REG((_enp), (_reg)); \
740 EFSYS_BAR_READQ((_enp)->en_esbp, \
741 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
743 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
744 uint32_t, (_index), \
745 uint32_t, _reg ## _OFST, \
746 uint32_t, (_eqp)->eq_u32[1], \
747 uint32_t, (_eqp)->eq_u32[0]); \
748 _NOTE(CONSTANTCONDITION) \
751 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
753 EFX_CHECK_REG((_enp), (_reg)); \
754 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
755 uint32_t, (_index), \
756 uint32_t, _reg ## _OFST, \
757 uint32_t, (_eqp)->eq_u32[1], \
758 uint32_t, (_eqp)->eq_u32[0]); \
759 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
760 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
762 _NOTE(CONSTANTCONDITION) \
765 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
767 EFX_CHECK_REG((_enp), (_reg)); \
768 EFSYS_BAR_READO((_enp)->en_esbp, \
769 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
771 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
772 uint32_t, (_index), \
773 uint32_t, _reg ## _OFST, \
774 uint32_t, (_eop)->eo_u32[3], \
775 uint32_t, (_eop)->eo_u32[2], \
776 uint32_t, (_eop)->eo_u32[1], \
777 uint32_t, (_eop)->eo_u32[0]); \
778 _NOTE(CONSTANTCONDITION) \
781 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
783 EFX_CHECK_REG((_enp), (_reg)); \
784 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
785 uint32_t, (_index), \
786 uint32_t, _reg ## _OFST, \
787 uint32_t, (_eop)->eo_u32[3], \
788 uint32_t, (_eop)->eo_u32[2], \
789 uint32_t, (_eop)->eo_u32[1], \
790 uint32_t, (_eop)->eo_u32[0]); \
791 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
792 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
794 _NOTE(CONSTANTCONDITION) \
798 * Allow drivers to perform optimised 128-bit doorbell writes.
799 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
800 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
801 * the need for locking in the host, and are the only ones known to be safe to
802 * use 128-bites write with.
804 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
806 EFX_CHECK_REG((_enp), (_reg)); \
807 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
810 uint32_t, (_index), \
811 uint32_t, _reg ## _OFST, \
812 uint32_t, (_eop)->eo_u32[3], \
813 uint32_t, (_eop)->eo_u32[2], \
814 uint32_t, (_eop)->eo_u32[1], \
815 uint32_t, (_eop)->eo_u32[0]); \
816 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
817 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
819 _NOTE(CONSTANTCONDITION) \
822 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
824 unsigned int _new = (_wptr); \
825 unsigned int _old = (_owptr); \
827 if ((_new) >= (_old)) \
828 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
829 (_old) * sizeof (efx_desc_t), \
830 ((_new) - (_old)) * sizeof (efx_desc_t)); \
833 * It is cheaper to sync entire map than sync \
834 * two parts especially when offset/size are \
835 * ignored and entire map is synced in any case.\
837 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
839 (_entries) * sizeof (efx_desc_t)); \
840 _NOTE(CONSTANTCONDITION) \
843 extern __checkReturn efx_rc_t
845 __in efx_nic_t *enp);
847 extern __checkReturn efx_rc_t
849 __in efx_nic_t *enp);
852 efx_mac_multicast_hash_compute(
853 __in_ecount(6*count) uint8_t const *addrs,
855 __out efx_oword_t *hash_low,
856 __out efx_oword_t *hash_high);
858 extern __checkReturn efx_rc_t
860 __in efx_nic_t *enp);
864 __in efx_nic_t *enp);
868 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
870 typedef struct efx_register_set_s {
871 unsigned int address;
875 } efx_register_set_t;
877 extern __checkReturn efx_rc_t
878 efx_nic_test_registers(
880 __in efx_register_set_t *rsp,
883 extern __checkReturn efx_rc_t
886 __in efx_register_set_t *rsp,
887 __in efx_pattern_type_t pattern,
890 #endif /* EFSYS_OPT_DIAG */
894 extern __checkReturn efx_rc_t
895 efx_mcdi_set_workaround(
898 __in boolean_t enabled,
899 __out_opt uint32_t *flagsp);
901 extern __checkReturn efx_rc_t
902 efx_mcdi_get_workarounds(
904 __out_opt uint32_t *implementedp,
905 __out_opt uint32_t *enabledp);
907 #endif /* EFSYS_OPT_MCDI */
913 #endif /* _SYS_EFX_IMPL_H */