1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
14 /* FIXME: Add definition for driver generated software events */
15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
21 #include "siena_impl.h"
22 #endif /* EFSYS_OPT_SIENA */
24 #if EFSYS_OPT_HUNTINGTON
25 #include "hunt_impl.h"
26 #endif /* EFSYS_OPT_HUNTINGTON */
29 #include "medford_impl.h"
30 #endif /* EFSYS_OPT_MEDFORD */
32 #if EFSYS_OPT_MEDFORD2
33 #include "medford2_impl.h"
34 #endif /* EFSYS_OPT_MEDFORD2 */
36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
37 #include "ef10_impl.h"
38 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
44 #define EFX_MOD_MCDI 0x00000001
45 #define EFX_MOD_PROBE 0x00000002
46 #define EFX_MOD_NVRAM 0x00000004
47 #define EFX_MOD_VPD 0x00000008
48 #define EFX_MOD_NIC 0x00000010
49 #define EFX_MOD_INTR 0x00000020
50 #define EFX_MOD_EV 0x00000040
51 #define EFX_MOD_RX 0x00000080
52 #define EFX_MOD_TX 0x00000100
53 #define EFX_MOD_PORT 0x00000200
54 #define EFX_MOD_MON 0x00000400
55 #define EFX_MOD_FILTER 0x00001000
56 #define EFX_MOD_LIC 0x00002000
57 #define EFX_MOD_TUNNEL 0x00004000
59 #define EFX_RESET_PHY 0x00000001
60 #define EFX_RESET_RXQ_ERR 0x00000002
61 #define EFX_RESET_TXQ_ERR 0x00000004
63 typedef enum efx_mac_type_e {
72 typedef struct efx_ev_ops_s {
73 efx_rc_t (*eevo_init)(efx_nic_t *);
74 void (*eevo_fini)(efx_nic_t *);
75 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
76 efsys_mem_t *, size_t, uint32_t,
77 uint32_t, uint32_t, efx_evq_t *);
78 void (*eevo_qdestroy)(efx_evq_t *);
79 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
80 void (*eevo_qpost)(efx_evq_t *, uint16_t);
81 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
83 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
87 typedef struct efx_tx_ops_s {
88 efx_rc_t (*etxo_init)(efx_nic_t *);
89 void (*etxo_fini)(efx_nic_t *);
90 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
91 unsigned int, unsigned int,
92 efsys_mem_t *, size_t,
94 efx_evq_t *, efx_txq_t *,
96 void (*etxo_qdestroy)(efx_txq_t *);
97 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
98 unsigned int, unsigned int,
100 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
101 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
102 efx_rc_t (*etxo_qflush)(efx_txq_t *);
103 void (*etxo_qenable)(efx_txq_t *);
104 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
105 void (*etxo_qpio_disable)(efx_txq_t *);
106 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
108 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
110 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
111 unsigned int, unsigned int,
113 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
116 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
119 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
122 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
124 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
127 void (*etxo_qstats_update)(efx_txq_t *,
132 typedef struct efx_rx_ops_s {
133 efx_rc_t (*erxo_init)(efx_nic_t *);
134 void (*erxo_fini)(efx_nic_t *);
135 #if EFSYS_OPT_RX_SCATTER
136 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
138 #if EFSYS_OPT_RX_SCALE
139 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
140 efx_rx_scale_context_type_t,
141 uint32_t, uint32_t *);
142 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
143 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
145 efx_rx_hash_type_t, boolean_t);
146 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
148 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
149 unsigned int *, size_t);
150 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
152 #endif /* EFSYS_OPT_RX_SCALE */
153 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
155 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
156 unsigned int, unsigned int,
158 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
159 #if EFSYS_OPT_RX_PACKED_STREAM
160 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
161 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
163 uint16_t *, uint32_t *, uint32_t *);
165 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
166 void (*erxo_qenable)(efx_rxq_t *);
167 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
168 unsigned int, efx_rxq_type_t, uint32_t,
169 efsys_mem_t *, size_t, uint32_t,
171 efx_evq_t *, efx_rxq_t *);
172 void (*erxo_qdestroy)(efx_rxq_t *);
175 typedef struct efx_mac_ops_s {
176 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
177 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
178 efx_rc_t (*emo_addr_set)(efx_nic_t *);
179 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
180 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
181 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
182 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
183 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
184 efx_rxq_t *, boolean_t);
185 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
186 #if EFSYS_OPT_LOOPBACK
187 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
188 efx_loopback_type_t);
189 #endif /* EFSYS_OPT_LOOPBACK */
190 #if EFSYS_OPT_MAC_STATS
191 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
192 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
193 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
194 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
195 uint16_t, boolean_t);
196 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
197 efsys_stat_t *, uint32_t *);
198 #endif /* EFSYS_OPT_MAC_STATS */
201 typedef struct efx_phy_ops_s {
202 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
203 efx_rc_t (*epo_reset)(efx_nic_t *);
204 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
205 efx_rc_t (*epo_verify)(efx_nic_t *);
206 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
207 #if EFSYS_OPT_PHY_STATS
208 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
210 #endif /* EFSYS_OPT_PHY_STATS */
212 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
213 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
214 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
215 efx_bist_result_t *, uint32_t *,
216 unsigned long *, size_t);
217 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
218 #endif /* EFSYS_OPT_BIST */
222 typedef struct efx_filter_ops_s {
223 efx_rc_t (*efo_init)(efx_nic_t *);
224 void (*efo_fini)(efx_nic_t *);
225 efx_rc_t (*efo_restore)(efx_nic_t *);
226 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
227 boolean_t may_replace);
228 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
229 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
231 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
232 boolean_t, boolean_t, boolean_t,
233 uint8_t const *, uint32_t);
236 extern __checkReturn efx_rc_t
237 efx_filter_reconfigure(
239 __in_ecount(6) uint8_t const *mac_addr,
240 __in boolean_t all_unicst,
241 __in boolean_t mulcst,
242 __in boolean_t all_mulcst,
243 __in boolean_t brdcst,
244 __in_ecount(6*count) uint8_t const *addrs,
245 __in uint32_t count);
247 #endif /* EFSYS_OPT_FILTER */
250 typedef struct efx_tunnel_ops_s {
251 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
252 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
254 #endif /* EFSYS_OPT_TUNNEL */
256 typedef struct efx_port_s {
257 efx_mac_type_t ep_mac_type;
258 uint32_t ep_phy_type;
261 uint8_t ep_mac_addr[6];
262 efx_link_mode_t ep_link_mode;
263 boolean_t ep_all_unicst;
265 boolean_t ep_all_mulcst;
267 unsigned int ep_fcntl;
268 boolean_t ep_fcntl_autoneg;
269 efx_oword_t ep_multicst_hash[2];
270 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
271 EFX_MAC_MULTICAST_LIST_MAX];
272 uint32_t ep_mulcst_addr_count;
273 #if EFSYS_OPT_LOOPBACK
274 efx_loopback_type_t ep_loopback_type;
275 efx_link_mode_t ep_loopback_link_mode;
276 #endif /* EFSYS_OPT_LOOPBACK */
277 #if EFSYS_OPT_PHY_FLAGS
278 uint32_t ep_phy_flags;
279 #endif /* EFSYS_OPT_PHY_FLAGS */
280 #if EFSYS_OPT_PHY_LED_CONTROL
281 efx_phy_led_mode_t ep_phy_led_mode;
282 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
283 efx_phy_media_type_t ep_fixed_port_type;
284 efx_phy_media_type_t ep_module_type;
285 uint32_t ep_adv_cap_mask;
286 uint32_t ep_lp_cap_mask;
287 uint32_t ep_default_adv_cap_mask;
288 uint32_t ep_phy_cap_mask;
289 boolean_t ep_mac_drain;
291 efx_bist_type_t ep_current_bist;
293 const efx_mac_ops_t *ep_emop;
294 const efx_phy_ops_t *ep_epop;
297 typedef struct efx_mon_ops_s {
298 #if EFSYS_OPT_MON_STATS
299 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
300 efx_mon_stat_value_t *);
301 #endif /* EFSYS_OPT_MON_STATS */
304 typedef struct efx_mon_s {
305 efx_mon_type_t em_type;
306 const efx_mon_ops_t *em_emop;
309 typedef struct efx_intr_ops_s {
310 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
311 void (*eio_enable)(efx_nic_t *);
312 void (*eio_disable)(efx_nic_t *);
313 void (*eio_disable_unlocked)(efx_nic_t *);
314 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
315 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
316 void (*eio_status_message)(efx_nic_t *, unsigned int,
318 void (*eio_fatal)(efx_nic_t *);
319 void (*eio_fini)(efx_nic_t *);
322 typedef struct efx_intr_s {
323 const efx_intr_ops_t *ei_eiop;
324 efsys_mem_t *ei_esmp;
325 efx_intr_type_t ei_type;
326 unsigned int ei_level;
329 typedef struct efx_nic_ops_s {
330 efx_rc_t (*eno_probe)(efx_nic_t *);
331 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
332 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
333 efx_rc_t (*eno_reset)(efx_nic_t *);
334 efx_rc_t (*eno_init)(efx_nic_t *);
335 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
336 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
337 uint32_t *, size_t *);
339 efx_rc_t (*eno_register_test)(efx_nic_t *);
340 #endif /* EFSYS_OPT_DIAG */
341 void (*eno_fini)(efx_nic_t *);
342 void (*eno_unprobe)(efx_nic_t *);
345 #ifndef EFX_TXQ_LIMIT_TARGET
346 #define EFX_TXQ_LIMIT_TARGET 259
348 #ifndef EFX_RXQ_LIMIT_TARGET
349 #define EFX_RXQ_LIMIT_TARGET 512
357 typedef struct siena_filter_spec_s {
360 uint32_t sfs_dmaq_id;
361 uint32_t sfs_dword[3];
362 } siena_filter_spec_t;
364 typedef enum siena_filter_type_e {
365 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
366 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
367 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
368 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
369 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
370 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
372 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
373 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
374 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
375 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
376 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
377 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
379 EFX_SIENA_FILTER_NTYPES
380 } siena_filter_type_t;
382 typedef enum siena_filter_tbl_id_e {
383 EFX_SIENA_FILTER_TBL_RX_IP = 0,
384 EFX_SIENA_FILTER_TBL_RX_MAC,
385 EFX_SIENA_FILTER_TBL_TX_IP,
386 EFX_SIENA_FILTER_TBL_TX_MAC,
387 EFX_SIENA_FILTER_NTBLS
388 } siena_filter_tbl_id_t;
390 typedef struct siena_filter_tbl_s {
391 int sft_size; /* number of entries */
392 int sft_used; /* active count */
393 uint32_t *sft_bitmap; /* active bitmap */
394 siena_filter_spec_t *sft_spec; /* array of saved specs */
395 } siena_filter_tbl_t;
397 typedef struct siena_filter_s {
398 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
399 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
402 #endif /* EFSYS_OPT_SIENA */
404 typedef struct efx_filter_s {
406 siena_filter_t *ef_siena_filter;
407 #endif /* EFSYS_OPT_SIENA */
408 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
409 ef10_filter_table_t *ef_ef10_filter_table;
410 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
416 siena_filter_tbl_clear(
418 __in siena_filter_tbl_id_t tbl);
420 #endif /* EFSYS_OPT_SIENA */
422 #endif /* EFSYS_OPT_FILTER */
426 #define EFX_TUNNEL_MAXNENTRIES (16)
430 typedef struct efx_tunnel_udp_entry_s {
431 uint16_t etue_port; /* host/cpu-endian */
432 uint16_t etue_protocol;
433 } efx_tunnel_udp_entry_t;
435 typedef struct efx_tunnel_cfg_s {
436 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
437 unsigned int etc_udp_entries_num;
440 #endif /* EFSYS_OPT_TUNNEL */
442 typedef struct efx_mcdi_ops_s {
443 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
444 void (*emco_send_request)(efx_nic_t *, void *, size_t,
446 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
447 boolean_t (*emco_poll_response)(efx_nic_t *);
448 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
449 void (*emco_fini)(efx_nic_t *);
450 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
451 efx_mcdi_feature_id_t, boolean_t *);
452 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
456 typedef struct efx_mcdi_s {
457 const efx_mcdi_ops_t *em_emcop;
458 const efx_mcdi_transport_t *em_emtp;
459 efx_mcdi_iface_t em_emip;
462 #endif /* EFSYS_OPT_MCDI */
466 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
467 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
469 typedef struct efx_nvram_ops_s {
471 efx_rc_t (*envo_test)(efx_nic_t *);
472 #endif /* EFSYS_OPT_DIAG */
473 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
475 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
476 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
477 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
478 unsigned int, caddr_t, size_t);
479 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
480 unsigned int, caddr_t, size_t);
481 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
482 unsigned int, size_t);
483 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
484 unsigned int, caddr_t, size_t);
485 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
487 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
488 uint32_t *, uint16_t *);
489 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
491 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
494 #endif /* EFSYS_OPT_NVRAM */
497 typedef struct efx_vpd_ops_s {
498 efx_rc_t (*evpdo_init)(efx_nic_t *);
499 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
500 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
501 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
502 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
503 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
505 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
507 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
508 efx_vpd_value_t *, unsigned int *);
509 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
510 void (*evpdo_fini)(efx_nic_t *);
512 #endif /* EFSYS_OPT_VPD */
514 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
516 __checkReturn efx_rc_t
517 efx_mcdi_nvram_partitions(
519 __out_bcount(size) caddr_t data,
521 __out unsigned int *npartnp);
523 __checkReturn efx_rc_t
524 efx_mcdi_nvram_metadata(
527 __out uint32_t *subtypep,
528 __out_ecount(4) uint16_t version[4],
529 __out_bcount_opt(size) char *descp,
532 __checkReturn efx_rc_t
536 __out_opt size_t *sizep,
537 __out_opt uint32_t *addressp,
538 __out_opt uint32_t *erase_sizep,
539 __out_opt uint32_t *write_sizep);
541 __checkReturn efx_rc_t
542 efx_mcdi_nvram_update_start(
544 __in uint32_t partn);
546 __checkReturn efx_rc_t
550 __in uint32_t offset,
551 __out_bcount(size) caddr_t data,
555 __checkReturn efx_rc_t
556 efx_mcdi_nvram_erase(
559 __in uint32_t offset,
562 __checkReturn efx_rc_t
563 efx_mcdi_nvram_write(
566 __in uint32_t offset,
567 __out_bcount(size) caddr_t data,
570 __checkReturn efx_rc_t
571 efx_mcdi_nvram_update_finish(
574 __in boolean_t reboot,
575 __out_opt uint32_t *verify_resultp);
579 __checkReturn efx_rc_t
582 __in uint32_t partn);
584 #endif /* EFSYS_OPT_DIAG */
586 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
588 #if EFSYS_OPT_LICENSING
590 typedef struct efx_lic_ops_s {
591 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
592 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
593 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
594 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
595 size_t *, uint8_t *);
596 efx_rc_t (*elo_find_start)
597 (efx_nic_t *, caddr_t, size_t, uint32_t *);
598 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
599 uint32_t, uint32_t *);
600 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
601 uint32_t, uint32_t *, uint32_t *);
602 boolean_t (*elo_validate_key)(efx_nic_t *,
604 efx_rc_t (*elo_read_key)(efx_nic_t *,
605 caddr_t, size_t, uint32_t, uint32_t,
606 caddr_t, size_t, uint32_t *);
607 efx_rc_t (*elo_write_key)(efx_nic_t *,
608 caddr_t, size_t, uint32_t,
609 caddr_t, uint32_t, uint32_t *);
610 efx_rc_t (*elo_delete_key)(efx_nic_t *,
611 caddr_t, size_t, uint32_t,
612 uint32_t, uint32_t, uint32_t *);
613 efx_rc_t (*elo_create_partition)(efx_nic_t *,
615 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
621 typedef struct efx_drv_cfg_s {
622 uint32_t edc_min_vi_count;
623 uint32_t edc_max_vi_count;
625 uint32_t edc_max_piobuf_count;
626 uint32_t edc_pio_alloc_size;
631 efx_family_t en_family;
632 uint32_t en_features;
633 efsys_identifier_t *en_esip;
634 efsys_lock_t *en_eslp;
635 efsys_bar_t *en_esbp;
636 unsigned int en_mod_flags;
637 unsigned int en_reset_flags;
638 efx_nic_cfg_t en_nic_cfg;
639 efx_drv_cfg_t en_drv_cfg;
643 uint32_t en_ev_qcount;
644 uint32_t en_rx_qcount;
645 uint32_t en_tx_qcount;
646 const efx_nic_ops_t *en_enop;
647 const efx_ev_ops_t *en_eevop;
648 const efx_tx_ops_t *en_etxop;
649 const efx_rx_ops_t *en_erxop;
651 efx_filter_t en_filter;
652 const efx_filter_ops_t *en_efop;
653 #endif /* EFSYS_OPT_FILTER */
655 efx_tunnel_cfg_t en_tunnel_cfg;
656 const efx_tunnel_ops_t *en_etop;
657 #endif /* EFSYS_OPT_TUNNEL */
660 #endif /* EFSYS_OPT_MCDI */
662 uint32_t en_nvram_partn_locked;
663 const efx_nvram_ops_t *en_envop;
664 #endif /* EFSYS_OPT_NVRAM */
666 const efx_vpd_ops_t *en_evpdop;
667 #endif /* EFSYS_OPT_VPD */
668 #if EFSYS_OPT_RX_SCALE
669 efx_rx_hash_support_t en_hash_support;
670 efx_rx_scale_context_type_t en_rss_context_type;
671 uint32_t en_rss_context;
672 #endif /* EFSYS_OPT_RX_SCALE */
673 uint32_t en_vport_id;
674 #if EFSYS_OPT_LICENSING
675 const efx_lic_ops_t *en_elop;
676 boolean_t en_licensing_supported;
681 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
682 unsigned int enu_partn_mask;
683 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
686 size_t enu_svpd_length;
687 #endif /* EFSYS_OPT_VPD */
690 #endif /* EFSYS_OPT_SIENA */
693 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
701 size_t ena_svpd_length;
702 #endif /* EFSYS_OPT_VPD */
703 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
704 uint32_t ena_piobuf_count;
705 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
706 uint32_t ena_pio_write_vi_base;
707 /* Memory BAR mapping regions */
708 uint32_t ena_uc_mem_map_offset;
709 size_t ena_uc_mem_map_size;
710 uint32_t ena_wc_mem_map_offset;
711 size_t ena_wc_mem_map_size;
714 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
718 #define EFX_NIC_MAGIC 0x02121996
720 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
721 const efx_ev_callbacks_t *, void *);
723 typedef struct efx_evq_rxq_state_s {
724 unsigned int eers_rx_read_ptr;
725 unsigned int eers_rx_mask;
726 #if EFSYS_OPT_RX_PACKED_STREAM
727 unsigned int eers_rx_stream_npackets;
728 boolean_t eers_rx_packed_stream;
729 unsigned int eers_rx_packed_stream_credits;
731 } efx_evq_rxq_state_t;
736 unsigned int ee_index;
737 unsigned int ee_mask;
738 efsys_mem_t *ee_esmp;
740 uint32_t ee_stat[EV_NQSTATS];
741 #endif /* EFSYS_OPT_QSTATS */
743 efx_ev_handler_t ee_rx;
744 efx_ev_handler_t ee_tx;
745 efx_ev_handler_t ee_driver;
746 efx_ev_handler_t ee_global;
747 efx_ev_handler_t ee_drv_gen;
749 efx_ev_handler_t ee_mcdi;
750 #endif /* EFSYS_OPT_MCDI */
752 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
757 #define EFX_EVQ_MAGIC 0x08081997
759 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
765 unsigned int er_index;
766 unsigned int er_label;
767 unsigned int er_mask;
768 efsys_mem_t *er_esmp;
769 efx_evq_rxq_state_t *er_ev_qstate;
772 #define EFX_RXQ_MAGIC 0x15022005
777 unsigned int et_index;
778 unsigned int et_mask;
779 efsys_mem_t *et_esmp;
780 #if EFSYS_OPT_HUNTINGTON
781 uint32_t et_pio_bufnum;
782 uint32_t et_pio_blknum;
783 uint32_t et_pio_write_offset;
784 uint32_t et_pio_offset;
788 uint32_t et_stat[TX_NQSTATS];
789 #endif /* EFSYS_OPT_QSTATS */
792 #define EFX_TXQ_MAGIC 0x05092005
794 #define EFX_MAC_ADDR_COPY(_dst, _src) \
796 (_dst)[0] = (_src)[0]; \
797 (_dst)[1] = (_src)[1]; \
798 (_dst)[2] = (_src)[2]; \
799 (_dst)[3] = (_src)[3]; \
800 (_dst)[4] = (_src)[4]; \
801 (_dst)[5] = (_src)[5]; \
802 _NOTE(CONSTANTCONDITION) \
805 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
807 uint16_t *_d = (uint16_t *)(_dst); \
811 _NOTE(CONSTANTCONDITION) \
814 #if EFSYS_OPT_CHECK_REG
815 #define EFX_CHECK_REG(_enp, _reg) \
817 const char *name = #_reg; \
818 char min = name[4]; \
819 char max = name[5]; \
822 switch ((_enp)->en_family) { \
823 case EFX_FAMILY_SIENA: \
827 case EFX_FAMILY_HUNTINGTON: \
831 case EFX_FAMILY_MEDFORD: \
835 case EFX_FAMILY_MEDFORD2: \
844 EFSYS_ASSERT3S(rev, >=, min); \
845 EFSYS_ASSERT3S(rev, <=, max); \
847 _NOTE(CONSTANTCONDITION) \
850 #define EFX_CHECK_REG(_enp, _reg) do { \
851 _NOTE(CONSTANTCONDITION) \
855 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
857 EFX_CHECK_REG((_enp), (_reg)); \
858 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
860 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
861 uint32_t, _reg ## _OFST, \
862 uint32_t, (_edp)->ed_u32[0]); \
863 _NOTE(CONSTANTCONDITION) \
866 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
868 EFX_CHECK_REG((_enp), (_reg)); \
869 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
870 uint32_t, _reg ## _OFST, \
871 uint32_t, (_edp)->ed_u32[0]); \
872 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
874 _NOTE(CONSTANTCONDITION) \
877 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
879 EFX_CHECK_REG((_enp), (_reg)); \
880 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
882 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
883 uint32_t, _reg ## _OFST, \
884 uint32_t, (_eqp)->eq_u32[1], \
885 uint32_t, (_eqp)->eq_u32[0]); \
886 _NOTE(CONSTANTCONDITION) \
889 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
891 EFX_CHECK_REG((_enp), (_reg)); \
892 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
893 uint32_t, _reg ## _OFST, \
894 uint32_t, (_eqp)->eq_u32[1], \
895 uint32_t, (_eqp)->eq_u32[0]); \
896 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
898 _NOTE(CONSTANTCONDITION) \
901 #define EFX_BAR_READO(_enp, _reg, _eop) \
903 EFX_CHECK_REG((_enp), (_reg)); \
904 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
906 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
907 uint32_t, _reg ## _OFST, \
908 uint32_t, (_eop)->eo_u32[3], \
909 uint32_t, (_eop)->eo_u32[2], \
910 uint32_t, (_eop)->eo_u32[1], \
911 uint32_t, (_eop)->eo_u32[0]); \
912 _NOTE(CONSTANTCONDITION) \
915 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
917 EFX_CHECK_REG((_enp), (_reg)); \
918 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
919 uint32_t, _reg ## _OFST, \
920 uint32_t, (_eop)->eo_u32[3], \
921 uint32_t, (_eop)->eo_u32[2], \
922 uint32_t, (_eop)->eo_u32[1], \
923 uint32_t, (_eop)->eo_u32[0]); \
924 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
926 _NOTE(CONSTANTCONDITION) \
930 * Accessors for memory BAR non-VI tables.
932 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
933 * to ensure the correct runtime VI window size is used on Medford2.
935 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
938 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
940 EFX_CHECK_REG((_enp), (_reg)); \
941 EFSYS_BAR_READD((_enp)->en_esbp, \
942 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
944 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
945 uint32_t, (_index), \
946 uint32_t, _reg ## _OFST, \
947 uint32_t, (_edp)->ed_u32[0]); \
948 _NOTE(CONSTANTCONDITION) \
951 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
953 EFX_CHECK_REG((_enp), (_reg)); \
954 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
955 uint32_t, (_index), \
956 uint32_t, _reg ## _OFST, \
957 uint32_t, (_edp)->ed_u32[0]); \
958 EFSYS_BAR_WRITED((_enp)->en_esbp, \
959 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
961 _NOTE(CONSTANTCONDITION) \
964 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
966 EFX_CHECK_REG((_enp), (_reg)); \
967 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
968 uint32_t, (_index), \
969 uint32_t, _reg ## _OFST, \
970 uint32_t, (_edp)->ed_u32[0]); \
971 EFSYS_BAR_WRITED((_enp)->en_esbp, \
973 (3 * sizeof (efx_dword_t)) + \
974 ((_index) * _reg ## _STEP)), \
976 _NOTE(CONSTANTCONDITION) \
979 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
981 EFX_CHECK_REG((_enp), (_reg)); \
982 EFSYS_BAR_READQ((_enp)->en_esbp, \
983 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
985 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
986 uint32_t, (_index), \
987 uint32_t, _reg ## _OFST, \
988 uint32_t, (_eqp)->eq_u32[1], \
989 uint32_t, (_eqp)->eq_u32[0]); \
990 _NOTE(CONSTANTCONDITION) \
993 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
995 EFX_CHECK_REG((_enp), (_reg)); \
996 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
997 uint32_t, (_index), \
998 uint32_t, _reg ## _OFST, \
999 uint32_t, (_eqp)->eq_u32[1], \
1000 uint32_t, (_eqp)->eq_u32[0]); \
1001 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1002 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1004 _NOTE(CONSTANTCONDITION) \
1007 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1009 EFX_CHECK_REG((_enp), (_reg)); \
1010 EFSYS_BAR_READO((_enp)->en_esbp, \
1011 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1013 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1014 uint32_t, (_index), \
1015 uint32_t, _reg ## _OFST, \
1016 uint32_t, (_eop)->eo_u32[3], \
1017 uint32_t, (_eop)->eo_u32[2], \
1018 uint32_t, (_eop)->eo_u32[1], \
1019 uint32_t, (_eop)->eo_u32[0]); \
1020 _NOTE(CONSTANTCONDITION) \
1023 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1025 EFX_CHECK_REG((_enp), (_reg)); \
1026 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1027 uint32_t, (_index), \
1028 uint32_t, _reg ## _OFST, \
1029 uint32_t, (_eop)->eo_u32[3], \
1030 uint32_t, (_eop)->eo_u32[2], \
1031 uint32_t, (_eop)->eo_u32[1], \
1032 uint32_t, (_eop)->eo_u32[0]); \
1033 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1034 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1036 _NOTE(CONSTANTCONDITION) \
1040 * Accessors for memory BAR per-VI registers.
1042 * The VI window size is 8KB for Medford and all earlier controllers.
1043 * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1046 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \
1048 EFX_CHECK_REG((_enp), (_reg)); \
1049 EFSYS_BAR_READD((_enp)->en_esbp, \
1050 ((_reg ## _OFST) + \
1051 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1053 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \
1054 uint32_t, (_index), \
1055 uint32_t, _reg ## _OFST, \
1056 uint32_t, (_edp)->ed_u32[0]); \
1057 _NOTE(CONSTANTCONDITION) \
1060 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \
1062 EFX_CHECK_REG((_enp), (_reg)); \
1063 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1064 uint32_t, (_index), \
1065 uint32_t, _reg ## _OFST, \
1066 uint32_t, (_edp)->ed_u32[0]); \
1067 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1068 ((_reg ## _OFST) + \
1069 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1071 _NOTE(CONSTANTCONDITION) \
1074 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \
1076 EFX_CHECK_REG((_enp), (_reg)); \
1077 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1078 uint32_t, (_index), \
1079 uint32_t, _reg ## _OFST, \
1080 uint32_t, (_edp)->ed_u32[0]); \
1081 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1082 ((_reg ## _OFST) + \
1083 (2 * sizeof (efx_dword_t)) + \
1084 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1086 _NOTE(CONSTANTCONDITION) \
1090 * Allow drivers to perform optimised 128-bit VI doorbell writes.
1091 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1092 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1093 * the need for locking in the host, and are the only ones known to be safe to
1094 * use 128-bites write with.
1096 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1098 EFX_CHECK_REG((_enp), (_reg)); \
1099 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \
1100 const char *, #_reg, \
1101 uint32_t, (_index), \
1102 uint32_t, _reg ## _OFST, \
1103 uint32_t, (_eop)->eo_u32[3], \
1104 uint32_t, (_eop)->eo_u32[2], \
1105 uint32_t, (_eop)->eo_u32[1], \
1106 uint32_t, (_eop)->eo_u32[0]); \
1107 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1109 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1111 _NOTE(CONSTANTCONDITION) \
1114 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1116 unsigned int _new = (_wptr); \
1117 unsigned int _old = (_owptr); \
1119 if ((_new) >= (_old)) \
1120 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1121 (_old) * sizeof (efx_desc_t), \
1122 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1125 * It is cheaper to sync entire map than sync \
1126 * two parts especially when offset/size are \
1127 * ignored and entire map is synced in any case.\
1129 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1131 (_entries) * sizeof (efx_desc_t)); \
1132 _NOTE(CONSTANTCONDITION) \
1135 extern __checkReturn efx_rc_t
1137 __in efx_nic_t *enp);
1140 efx_mac_multicast_hash_compute(
1141 __in_ecount(6*count) uint8_t const *addrs,
1143 __out efx_oword_t *hash_low,
1144 __out efx_oword_t *hash_high);
1146 extern __checkReturn efx_rc_t
1148 __in efx_nic_t *enp);
1152 __in efx_nic_t *enp);
1156 /* VPD utility functions */
1158 extern __checkReturn efx_rc_t
1159 efx_vpd_hunk_length(
1160 __in_bcount(size) caddr_t data,
1162 __out size_t *lengthp);
1164 extern __checkReturn efx_rc_t
1165 efx_vpd_hunk_verify(
1166 __in_bcount(size) caddr_t data,
1168 __out_opt boolean_t *cksummedp);
1170 extern __checkReturn efx_rc_t
1171 efx_vpd_hunk_reinit(
1172 __in_bcount(size) caddr_t data,
1174 __in boolean_t wantpid);
1176 extern __checkReturn efx_rc_t
1178 __in_bcount(size) caddr_t data,
1180 __in efx_vpd_tag_t tag,
1181 __in efx_vpd_keyword_t keyword,
1182 __out unsigned int *payloadp,
1183 __out uint8_t *paylenp);
1185 extern __checkReturn efx_rc_t
1187 __in_bcount(size) caddr_t data,
1189 __out efx_vpd_tag_t *tagp,
1190 __out efx_vpd_keyword_t *keyword,
1191 __out_opt unsigned int *payloadp,
1192 __out_opt uint8_t *paylenp,
1193 __inout unsigned int *contp);
1195 extern __checkReturn efx_rc_t
1197 __in_bcount(size) caddr_t data,
1199 __in efx_vpd_value_t *evvp);
1201 #endif /* EFSYS_OPT_VPD */
1205 extern __checkReturn efx_rc_t
1206 efx_mcdi_set_workaround(
1207 __in efx_nic_t *enp,
1209 __in boolean_t enabled,
1210 __out_opt uint32_t *flagsp);
1212 extern __checkReturn efx_rc_t
1213 efx_mcdi_get_workarounds(
1214 __in efx_nic_t *enp,
1215 __out_opt uint32_t *implementedp,
1216 __out_opt uint32_t *enabledp);
1218 #endif /* EFSYS_OPT_MCDI */
1220 #if EFSYS_OPT_MAC_STATS
1223 * Closed range of stats (i.e. the first and the last are included).
1224 * The last must be greater or equal (if the range is one item only) to
1227 struct efx_mac_stats_range {
1228 efx_mac_stat_t first;
1229 efx_mac_stat_t last;
1233 efx_mac_stats_mask_add_ranges(
1234 __inout_bcount(mask_size) uint32_t *maskp,
1235 __in size_t mask_size,
1236 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1237 __in unsigned int rng_count);
1239 #endif /* EFSYS_OPT_MAC_STATS */
1245 #endif /* _SYS_EFX_IMPL_H */