2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_FILTER 0x00001000
76 #define EFX_MOD_LIC 0x00002000
77 #define EFX_MOD_TUNNEL 0x00004000
79 #define EFX_RESET_PHY 0x00000001
80 #define EFX_RESET_RXQ_ERR 0x00000002
81 #define EFX_RESET_TXQ_ERR 0x00000004
83 typedef enum efx_mac_type_e {
91 typedef struct efx_ev_ops_s {
92 efx_rc_t (*eevo_init)(efx_nic_t *);
93 void (*eevo_fini)(efx_nic_t *);
94 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
95 efsys_mem_t *, size_t, uint32_t,
96 uint32_t, uint32_t, efx_evq_t *);
97 void (*eevo_qdestroy)(efx_evq_t *);
98 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
99 void (*eevo_qpost)(efx_evq_t *, uint16_t);
100 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
102 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
106 typedef struct efx_tx_ops_s {
107 efx_rc_t (*etxo_init)(efx_nic_t *);
108 void (*etxo_fini)(efx_nic_t *);
109 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
110 unsigned int, unsigned int,
111 efsys_mem_t *, size_t,
113 efx_evq_t *, efx_txq_t *,
115 void (*etxo_qdestroy)(efx_txq_t *);
116 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
117 unsigned int, unsigned int,
119 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
120 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
121 efx_rc_t (*etxo_qflush)(efx_txq_t *);
122 void (*etxo_qenable)(efx_txq_t *);
123 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
124 void (*etxo_qpio_disable)(efx_txq_t *);
125 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
127 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
129 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
130 unsigned int, unsigned int,
132 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
135 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
138 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
144 void (*etxo_qstats_update)(efx_txq_t *,
149 typedef struct efx_rx_ops_s {
150 efx_rc_t (*erxo_init)(efx_nic_t *);
151 void (*erxo_fini)(efx_nic_t *);
152 #if EFSYS_OPT_RX_SCATTER
153 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
155 #if EFSYS_OPT_RX_SCALE
156 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
157 efx_rx_scale_context_type_t,
158 uint32_t, uint32_t *);
159 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
160 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
162 efx_rx_hash_type_t, boolean_t);
163 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
165 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
166 unsigned int *, size_t);
167 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
169 #endif /* EFSYS_OPT_RX_SCALE */
170 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
172 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
173 unsigned int, unsigned int,
175 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
176 #if EFSYS_OPT_RX_PACKED_STREAM
177 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
178 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
180 uint16_t *, uint32_t *, uint32_t *);
182 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
183 void (*erxo_qenable)(efx_rxq_t *);
184 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
185 unsigned int, efx_rxq_type_t, uint32_t,
186 efsys_mem_t *, size_t, uint32_t,
188 efx_evq_t *, efx_rxq_t *);
189 void (*erxo_qdestroy)(efx_rxq_t *);
192 typedef struct efx_mac_ops_s {
193 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
194 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
195 efx_rc_t (*emo_addr_set)(efx_nic_t *);
196 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
197 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
198 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
199 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
200 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
201 efx_rxq_t *, boolean_t);
202 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
203 #if EFSYS_OPT_LOOPBACK
204 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
205 efx_loopback_type_t);
206 #endif /* EFSYS_OPT_LOOPBACK */
207 #if EFSYS_OPT_MAC_STATS
208 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
209 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
210 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
211 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
212 uint16_t, boolean_t);
213 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
214 efsys_stat_t *, uint32_t *);
215 #endif /* EFSYS_OPT_MAC_STATS */
218 typedef struct efx_phy_ops_s {
219 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
220 efx_rc_t (*epo_reset)(efx_nic_t *);
221 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
222 efx_rc_t (*epo_verify)(efx_nic_t *);
223 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
224 #if EFSYS_OPT_PHY_STATS
225 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
227 #endif /* EFSYS_OPT_PHY_STATS */
229 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
230 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
231 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
232 efx_bist_result_t *, uint32_t *,
233 unsigned long *, size_t);
234 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
235 #endif /* EFSYS_OPT_BIST */
239 typedef struct efx_filter_ops_s {
240 efx_rc_t (*efo_init)(efx_nic_t *);
241 void (*efo_fini)(efx_nic_t *);
242 efx_rc_t (*efo_restore)(efx_nic_t *);
243 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
244 boolean_t may_replace);
245 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
246 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
248 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
249 boolean_t, boolean_t, boolean_t,
250 uint8_t const *, uint32_t);
253 extern __checkReturn efx_rc_t
254 efx_filter_reconfigure(
256 __in_ecount(6) uint8_t const *mac_addr,
257 __in boolean_t all_unicst,
258 __in boolean_t mulcst,
259 __in boolean_t all_mulcst,
260 __in boolean_t brdcst,
261 __in_ecount(6*count) uint8_t const *addrs,
262 __in uint32_t count);
264 #endif /* EFSYS_OPT_FILTER */
267 typedef struct efx_tunnel_ops_s {
268 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
269 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
271 #endif /* EFSYS_OPT_TUNNEL */
273 typedef struct efx_port_s {
274 efx_mac_type_t ep_mac_type;
275 uint32_t ep_phy_type;
278 uint8_t ep_mac_addr[6];
279 efx_link_mode_t ep_link_mode;
280 boolean_t ep_all_unicst;
282 boolean_t ep_all_mulcst;
284 unsigned int ep_fcntl;
285 boolean_t ep_fcntl_autoneg;
286 efx_oword_t ep_multicst_hash[2];
287 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
288 EFX_MAC_MULTICAST_LIST_MAX];
289 uint32_t ep_mulcst_addr_count;
290 #if EFSYS_OPT_LOOPBACK
291 efx_loopback_type_t ep_loopback_type;
292 efx_link_mode_t ep_loopback_link_mode;
293 #endif /* EFSYS_OPT_LOOPBACK */
294 #if EFSYS_OPT_PHY_FLAGS
295 uint32_t ep_phy_flags;
296 #endif /* EFSYS_OPT_PHY_FLAGS */
297 #if EFSYS_OPT_PHY_LED_CONTROL
298 efx_phy_led_mode_t ep_phy_led_mode;
299 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
300 efx_phy_media_type_t ep_fixed_port_type;
301 efx_phy_media_type_t ep_module_type;
302 uint32_t ep_adv_cap_mask;
303 uint32_t ep_lp_cap_mask;
304 uint32_t ep_default_adv_cap_mask;
305 uint32_t ep_phy_cap_mask;
306 boolean_t ep_mac_drain;
308 efx_bist_type_t ep_current_bist;
310 const efx_mac_ops_t *ep_emop;
311 const efx_phy_ops_t *ep_epop;
314 typedef struct efx_mon_ops_s {
315 #if EFSYS_OPT_MON_STATS
316 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
317 efx_mon_stat_value_t *);
318 #endif /* EFSYS_OPT_MON_STATS */
321 typedef struct efx_mon_s {
322 efx_mon_type_t em_type;
323 const efx_mon_ops_t *em_emop;
326 typedef struct efx_intr_ops_s {
327 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
328 void (*eio_enable)(efx_nic_t *);
329 void (*eio_disable)(efx_nic_t *);
330 void (*eio_disable_unlocked)(efx_nic_t *);
331 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
332 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
333 void (*eio_status_message)(efx_nic_t *, unsigned int,
335 void (*eio_fatal)(efx_nic_t *);
336 void (*eio_fini)(efx_nic_t *);
339 typedef struct efx_intr_s {
340 const efx_intr_ops_t *ei_eiop;
341 efsys_mem_t *ei_esmp;
342 efx_intr_type_t ei_type;
343 unsigned int ei_level;
346 typedef struct efx_nic_ops_s {
347 efx_rc_t (*eno_probe)(efx_nic_t *);
348 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
349 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
350 efx_rc_t (*eno_reset)(efx_nic_t *);
351 efx_rc_t (*eno_init)(efx_nic_t *);
352 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
353 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
354 uint32_t *, size_t *);
356 efx_rc_t (*eno_register_test)(efx_nic_t *);
357 #endif /* EFSYS_OPT_DIAG */
358 void (*eno_fini)(efx_nic_t *);
359 void (*eno_unprobe)(efx_nic_t *);
362 #ifndef EFX_TXQ_LIMIT_TARGET
363 #define EFX_TXQ_LIMIT_TARGET 259
365 #ifndef EFX_RXQ_LIMIT_TARGET
366 #define EFX_RXQ_LIMIT_TARGET 512
374 typedef struct siena_filter_spec_s {
377 uint32_t sfs_dmaq_id;
378 uint32_t sfs_dword[3];
379 } siena_filter_spec_t;
381 typedef enum siena_filter_type_e {
382 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
383 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
384 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
385 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
386 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
387 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
389 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
390 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
391 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
392 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
393 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
394 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
396 EFX_SIENA_FILTER_NTYPES
397 } siena_filter_type_t;
399 typedef enum siena_filter_tbl_id_e {
400 EFX_SIENA_FILTER_TBL_RX_IP = 0,
401 EFX_SIENA_FILTER_TBL_RX_MAC,
402 EFX_SIENA_FILTER_TBL_TX_IP,
403 EFX_SIENA_FILTER_TBL_TX_MAC,
404 EFX_SIENA_FILTER_NTBLS
405 } siena_filter_tbl_id_t;
407 typedef struct siena_filter_tbl_s {
408 int sft_size; /* number of entries */
409 int sft_used; /* active count */
410 uint32_t *sft_bitmap; /* active bitmap */
411 siena_filter_spec_t *sft_spec; /* array of saved specs */
412 } siena_filter_tbl_t;
414 typedef struct siena_filter_s {
415 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
416 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
419 #endif /* EFSYS_OPT_SIENA */
421 typedef struct efx_filter_s {
423 siena_filter_t *ef_siena_filter;
424 #endif /* EFSYS_OPT_SIENA */
425 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
426 ef10_filter_table_t *ef_ef10_filter_table;
427 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
433 siena_filter_tbl_clear(
435 __in siena_filter_tbl_id_t tbl);
437 #endif /* EFSYS_OPT_SIENA */
439 #endif /* EFSYS_OPT_FILTER */
443 #define EFX_TUNNEL_MAXNENTRIES (16)
447 typedef struct efx_tunnel_udp_entry_s {
448 uint16_t etue_port; /* host/cpu-endian */
449 uint16_t etue_protocol;
450 } efx_tunnel_udp_entry_t;
452 typedef struct efx_tunnel_cfg_s {
453 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
454 unsigned int etc_udp_entries_num;
457 #endif /* EFSYS_OPT_TUNNEL */
459 typedef struct efx_mcdi_ops_s {
460 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
461 void (*emco_send_request)(efx_nic_t *, void *, size_t,
463 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
464 boolean_t (*emco_poll_response)(efx_nic_t *);
465 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
466 void (*emco_fini)(efx_nic_t *);
467 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
468 efx_mcdi_feature_id_t, boolean_t *);
469 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
473 typedef struct efx_mcdi_s {
474 const efx_mcdi_ops_t *em_emcop;
475 const efx_mcdi_transport_t *em_emtp;
476 efx_mcdi_iface_t em_emip;
479 #endif /* EFSYS_OPT_MCDI */
483 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
484 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
486 typedef struct efx_nvram_ops_s {
488 efx_rc_t (*envo_test)(efx_nic_t *);
489 #endif /* EFSYS_OPT_DIAG */
490 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
492 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
493 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
494 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
495 unsigned int, caddr_t, size_t);
496 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
497 unsigned int, caddr_t, size_t);
498 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
499 unsigned int, size_t);
500 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
501 unsigned int, caddr_t, size_t);
502 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
504 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
505 uint32_t *, uint16_t *);
506 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
508 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
511 #endif /* EFSYS_OPT_NVRAM */
514 typedef struct efx_vpd_ops_s {
515 efx_rc_t (*evpdo_init)(efx_nic_t *);
516 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
517 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
518 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
519 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
520 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
522 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
524 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
525 efx_vpd_value_t *, unsigned int *);
526 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
527 void (*evpdo_fini)(efx_nic_t *);
529 #endif /* EFSYS_OPT_VPD */
531 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
533 __checkReturn efx_rc_t
534 efx_mcdi_nvram_partitions(
536 __out_bcount(size) caddr_t data,
538 __out unsigned int *npartnp);
540 __checkReturn efx_rc_t
541 efx_mcdi_nvram_metadata(
544 __out uint32_t *subtypep,
545 __out_ecount(4) uint16_t version[4],
546 __out_bcount_opt(size) char *descp,
549 __checkReturn efx_rc_t
553 __out_opt size_t *sizep,
554 __out_opt uint32_t *addressp,
555 __out_opt uint32_t *erase_sizep,
556 __out_opt uint32_t *write_sizep);
558 __checkReturn efx_rc_t
559 efx_mcdi_nvram_update_start(
561 __in uint32_t partn);
563 __checkReturn efx_rc_t
567 __in uint32_t offset,
568 __out_bcount(size) caddr_t data,
572 __checkReturn efx_rc_t
573 efx_mcdi_nvram_erase(
576 __in uint32_t offset,
579 __checkReturn efx_rc_t
580 efx_mcdi_nvram_write(
583 __in uint32_t offset,
584 __out_bcount(size) caddr_t data,
587 __checkReturn efx_rc_t
588 efx_mcdi_nvram_update_finish(
591 __in boolean_t reboot,
592 __out_opt uint32_t *verify_resultp);
596 __checkReturn efx_rc_t
599 __in uint32_t partn);
601 #endif /* EFSYS_OPT_DIAG */
603 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
605 #if EFSYS_OPT_LICENSING
607 typedef struct efx_lic_ops_s {
608 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
609 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
610 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
611 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
612 size_t *, uint8_t *);
613 efx_rc_t (*elo_find_start)
614 (efx_nic_t *, caddr_t, size_t, uint32_t *);
615 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
616 uint32_t, uint32_t *);
617 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
618 uint32_t, uint32_t *, uint32_t *);
619 boolean_t (*elo_validate_key)(efx_nic_t *,
621 efx_rc_t (*elo_read_key)(efx_nic_t *,
622 caddr_t, size_t, uint32_t, uint32_t,
623 caddr_t, size_t, uint32_t *);
624 efx_rc_t (*elo_write_key)(efx_nic_t *,
625 caddr_t, size_t, uint32_t,
626 caddr_t, uint32_t, uint32_t *);
627 efx_rc_t (*elo_delete_key)(efx_nic_t *,
628 caddr_t, size_t, uint32_t,
629 uint32_t, uint32_t, uint32_t *);
630 efx_rc_t (*elo_create_partition)(efx_nic_t *,
632 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
638 typedef struct efx_drv_cfg_s {
639 uint32_t edc_min_vi_count;
640 uint32_t edc_max_vi_count;
642 uint32_t edc_max_piobuf_count;
643 uint32_t edc_pio_alloc_size;
648 efx_family_t en_family;
649 uint32_t en_features;
650 efsys_identifier_t *en_esip;
651 efsys_lock_t *en_eslp;
652 efsys_bar_t *en_esbp;
653 unsigned int en_mod_flags;
654 unsigned int en_reset_flags;
655 efx_nic_cfg_t en_nic_cfg;
656 efx_drv_cfg_t en_drv_cfg;
660 uint32_t en_ev_qcount;
661 uint32_t en_rx_qcount;
662 uint32_t en_tx_qcount;
663 const efx_nic_ops_t *en_enop;
664 const efx_ev_ops_t *en_eevop;
665 const efx_tx_ops_t *en_etxop;
666 const efx_rx_ops_t *en_erxop;
668 efx_filter_t en_filter;
669 const efx_filter_ops_t *en_efop;
670 #endif /* EFSYS_OPT_FILTER */
672 efx_tunnel_cfg_t en_tunnel_cfg;
673 const efx_tunnel_ops_t *en_etop;
674 #endif /* EFSYS_OPT_TUNNEL */
677 #endif /* EFSYS_OPT_MCDI */
679 uint32_t en_nvram_partn_locked;
680 const efx_nvram_ops_t *en_envop;
681 #endif /* EFSYS_OPT_NVRAM */
683 const efx_vpd_ops_t *en_evpdop;
684 #endif /* EFSYS_OPT_VPD */
685 #if EFSYS_OPT_RX_SCALE
686 efx_rx_hash_support_t en_hash_support;
687 efx_rx_scale_context_type_t en_rss_context_type;
688 uint32_t en_rss_context;
689 #endif /* EFSYS_OPT_RX_SCALE */
690 uint32_t en_vport_id;
691 #if EFSYS_OPT_LICENSING
692 const efx_lic_ops_t *en_elop;
693 boolean_t en_licensing_supported;
698 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
699 unsigned int enu_partn_mask;
700 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
703 size_t enu_svpd_length;
704 #endif /* EFSYS_OPT_VPD */
707 #endif /* EFSYS_OPT_SIENA */
710 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
718 size_t ena_svpd_length;
719 #endif /* EFSYS_OPT_VPD */
720 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
721 uint32_t ena_piobuf_count;
722 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
723 uint32_t ena_pio_write_vi_base;
724 /* Memory BAR mapping regions */
725 uint32_t ena_uc_mem_map_offset;
726 size_t ena_uc_mem_map_size;
727 uint32_t ena_wc_mem_map_offset;
728 size_t ena_wc_mem_map_size;
731 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
735 #define EFX_NIC_MAGIC 0x02121996
737 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
738 const efx_ev_callbacks_t *, void *);
740 typedef struct efx_evq_rxq_state_s {
741 unsigned int eers_rx_read_ptr;
742 unsigned int eers_rx_mask;
743 #if EFSYS_OPT_RX_PACKED_STREAM
744 unsigned int eers_rx_stream_npackets;
745 boolean_t eers_rx_packed_stream;
746 unsigned int eers_rx_packed_stream_credits;
748 } efx_evq_rxq_state_t;
753 unsigned int ee_index;
754 unsigned int ee_mask;
755 efsys_mem_t *ee_esmp;
757 uint32_t ee_stat[EV_NQSTATS];
758 #endif /* EFSYS_OPT_QSTATS */
760 efx_ev_handler_t ee_rx;
761 efx_ev_handler_t ee_tx;
762 efx_ev_handler_t ee_driver;
763 efx_ev_handler_t ee_global;
764 efx_ev_handler_t ee_drv_gen;
766 efx_ev_handler_t ee_mcdi;
767 #endif /* EFSYS_OPT_MCDI */
769 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
774 #define EFX_EVQ_MAGIC 0x08081997
776 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
782 unsigned int er_index;
783 unsigned int er_label;
784 unsigned int er_mask;
785 efsys_mem_t *er_esmp;
786 efx_evq_rxq_state_t *er_ev_qstate;
789 #define EFX_RXQ_MAGIC 0x15022005
794 unsigned int et_index;
795 unsigned int et_mask;
796 efsys_mem_t *et_esmp;
797 #if EFSYS_OPT_HUNTINGTON
798 uint32_t et_pio_bufnum;
799 uint32_t et_pio_blknum;
800 uint32_t et_pio_write_offset;
801 uint32_t et_pio_offset;
805 uint32_t et_stat[TX_NQSTATS];
806 #endif /* EFSYS_OPT_QSTATS */
809 #define EFX_TXQ_MAGIC 0x05092005
811 #define EFX_MAC_ADDR_COPY(_dst, _src) \
813 (_dst)[0] = (_src)[0]; \
814 (_dst)[1] = (_src)[1]; \
815 (_dst)[2] = (_src)[2]; \
816 (_dst)[3] = (_src)[3]; \
817 (_dst)[4] = (_src)[4]; \
818 (_dst)[5] = (_src)[5]; \
819 _NOTE(CONSTANTCONDITION) \
822 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
824 uint16_t *_d = (uint16_t *)(_dst); \
828 _NOTE(CONSTANTCONDITION) \
831 #if EFSYS_OPT_CHECK_REG
832 #define EFX_CHECK_REG(_enp, _reg) \
834 const char *name = #_reg; \
835 char min = name[4]; \
836 char max = name[5]; \
839 switch ((_enp)->en_family) { \
840 case EFX_FAMILY_SIENA: \
844 case EFX_FAMILY_HUNTINGTON: \
848 case EFX_FAMILY_MEDFORD: \
857 EFSYS_ASSERT3S(rev, >=, min); \
858 EFSYS_ASSERT3S(rev, <=, max); \
860 _NOTE(CONSTANTCONDITION) \
863 #define EFX_CHECK_REG(_enp, _reg) do { \
864 _NOTE(CONSTANTCONDITION) \
868 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
870 EFX_CHECK_REG((_enp), (_reg)); \
871 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
873 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
874 uint32_t, _reg ## _OFST, \
875 uint32_t, (_edp)->ed_u32[0]); \
876 _NOTE(CONSTANTCONDITION) \
879 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
881 EFX_CHECK_REG((_enp), (_reg)); \
882 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
883 uint32_t, _reg ## _OFST, \
884 uint32_t, (_edp)->ed_u32[0]); \
885 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
887 _NOTE(CONSTANTCONDITION) \
890 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
892 EFX_CHECK_REG((_enp), (_reg)); \
893 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
895 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
896 uint32_t, _reg ## _OFST, \
897 uint32_t, (_eqp)->eq_u32[1], \
898 uint32_t, (_eqp)->eq_u32[0]); \
899 _NOTE(CONSTANTCONDITION) \
902 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
904 EFX_CHECK_REG((_enp), (_reg)); \
905 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
906 uint32_t, _reg ## _OFST, \
907 uint32_t, (_eqp)->eq_u32[1], \
908 uint32_t, (_eqp)->eq_u32[0]); \
909 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
911 _NOTE(CONSTANTCONDITION) \
914 #define EFX_BAR_READO(_enp, _reg, _eop) \
916 EFX_CHECK_REG((_enp), (_reg)); \
917 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
919 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
920 uint32_t, _reg ## _OFST, \
921 uint32_t, (_eop)->eo_u32[3], \
922 uint32_t, (_eop)->eo_u32[2], \
923 uint32_t, (_eop)->eo_u32[1], \
924 uint32_t, (_eop)->eo_u32[0]); \
925 _NOTE(CONSTANTCONDITION) \
928 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
930 EFX_CHECK_REG((_enp), (_reg)); \
931 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
932 uint32_t, _reg ## _OFST, \
933 uint32_t, (_eop)->eo_u32[3], \
934 uint32_t, (_eop)->eo_u32[2], \
935 uint32_t, (_eop)->eo_u32[1], \
936 uint32_t, (_eop)->eo_u32[0]); \
937 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
939 _NOTE(CONSTANTCONDITION) \
942 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
944 EFX_CHECK_REG((_enp), (_reg)); \
945 EFSYS_BAR_READD((_enp)->en_esbp, \
946 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
948 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
949 uint32_t, (_index), \
950 uint32_t, _reg ## _OFST, \
951 uint32_t, (_edp)->ed_u32[0]); \
952 _NOTE(CONSTANTCONDITION) \
955 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
957 EFX_CHECK_REG((_enp), (_reg)); \
958 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
959 uint32_t, (_index), \
960 uint32_t, _reg ## _OFST, \
961 uint32_t, (_edp)->ed_u32[0]); \
962 EFSYS_BAR_WRITED((_enp)->en_esbp, \
963 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
965 _NOTE(CONSTANTCONDITION) \
968 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
970 EFX_CHECK_REG((_enp), (_reg)); \
971 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
972 uint32_t, (_index), \
973 uint32_t, _reg ## _OFST, \
974 uint32_t, (_edp)->ed_u32[0]); \
975 EFSYS_BAR_WRITED((_enp)->en_esbp, \
977 (2 * sizeof (efx_dword_t)) + \
978 ((_index) * _reg ## _STEP)), \
980 _NOTE(CONSTANTCONDITION) \
983 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
985 EFX_CHECK_REG((_enp), (_reg)); \
986 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
987 uint32_t, (_index), \
988 uint32_t, _reg ## _OFST, \
989 uint32_t, (_edp)->ed_u32[0]); \
990 EFSYS_BAR_WRITED((_enp)->en_esbp, \
992 (3 * sizeof (efx_dword_t)) + \
993 ((_index) * _reg ## _STEP)), \
995 _NOTE(CONSTANTCONDITION) \
998 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
1000 EFX_CHECK_REG((_enp), (_reg)); \
1001 EFSYS_BAR_READQ((_enp)->en_esbp, \
1002 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1004 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
1005 uint32_t, (_index), \
1006 uint32_t, _reg ## _OFST, \
1007 uint32_t, (_eqp)->eq_u32[1], \
1008 uint32_t, (_eqp)->eq_u32[0]); \
1009 _NOTE(CONSTANTCONDITION) \
1012 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1014 EFX_CHECK_REG((_enp), (_reg)); \
1015 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1016 uint32_t, (_index), \
1017 uint32_t, _reg ## _OFST, \
1018 uint32_t, (_eqp)->eq_u32[1], \
1019 uint32_t, (_eqp)->eq_u32[0]); \
1020 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1021 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1023 _NOTE(CONSTANTCONDITION) \
1026 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1028 EFX_CHECK_REG((_enp), (_reg)); \
1029 EFSYS_BAR_READO((_enp)->en_esbp, \
1030 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1032 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1033 uint32_t, (_index), \
1034 uint32_t, _reg ## _OFST, \
1035 uint32_t, (_eop)->eo_u32[3], \
1036 uint32_t, (_eop)->eo_u32[2], \
1037 uint32_t, (_eop)->eo_u32[1], \
1038 uint32_t, (_eop)->eo_u32[0]); \
1039 _NOTE(CONSTANTCONDITION) \
1042 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1044 EFX_CHECK_REG((_enp), (_reg)); \
1045 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1046 uint32_t, (_index), \
1047 uint32_t, _reg ## _OFST, \
1048 uint32_t, (_eop)->eo_u32[3], \
1049 uint32_t, (_eop)->eo_u32[2], \
1050 uint32_t, (_eop)->eo_u32[1], \
1051 uint32_t, (_eop)->eo_u32[0]); \
1052 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1053 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1055 _NOTE(CONSTANTCONDITION) \
1059 * Allow drivers to perform optimised 128-bit doorbell writes.
1060 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1061 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1062 * the need for locking in the host, and are the only ones known to be safe to
1063 * use 128-bites write with.
1065 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1067 EFX_CHECK_REG((_enp), (_reg)); \
1068 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1069 const char *, #_reg, \
1070 uint32_t, (_index), \
1071 uint32_t, _reg ## _OFST, \
1072 uint32_t, (_eop)->eo_u32[3], \
1073 uint32_t, (_eop)->eo_u32[2], \
1074 uint32_t, (_eop)->eo_u32[1], \
1075 uint32_t, (_eop)->eo_u32[0]); \
1076 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1077 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1079 _NOTE(CONSTANTCONDITION) \
1082 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1084 unsigned int _new = (_wptr); \
1085 unsigned int _old = (_owptr); \
1087 if ((_new) >= (_old)) \
1088 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1089 (_old) * sizeof (efx_desc_t), \
1090 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1093 * It is cheaper to sync entire map than sync \
1094 * two parts especially when offset/size are \
1095 * ignored and entire map is synced in any case.\
1097 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1099 (_entries) * sizeof (efx_desc_t)); \
1100 _NOTE(CONSTANTCONDITION) \
1103 extern __checkReturn efx_rc_t
1105 __in efx_nic_t *enp);
1108 efx_mac_multicast_hash_compute(
1109 __in_ecount(6*count) uint8_t const *addrs,
1111 __out efx_oword_t *hash_low,
1112 __out efx_oword_t *hash_high);
1114 extern __checkReturn efx_rc_t
1116 __in efx_nic_t *enp);
1120 __in efx_nic_t *enp);
1124 /* VPD utility functions */
1126 extern __checkReturn efx_rc_t
1127 efx_vpd_hunk_length(
1128 __in_bcount(size) caddr_t data,
1130 __out size_t *lengthp);
1132 extern __checkReturn efx_rc_t
1133 efx_vpd_hunk_verify(
1134 __in_bcount(size) caddr_t data,
1136 __out_opt boolean_t *cksummedp);
1138 extern __checkReturn efx_rc_t
1139 efx_vpd_hunk_reinit(
1140 __in_bcount(size) caddr_t data,
1142 __in boolean_t wantpid);
1144 extern __checkReturn efx_rc_t
1146 __in_bcount(size) caddr_t data,
1148 __in efx_vpd_tag_t tag,
1149 __in efx_vpd_keyword_t keyword,
1150 __out unsigned int *payloadp,
1151 __out uint8_t *paylenp);
1153 extern __checkReturn efx_rc_t
1155 __in_bcount(size) caddr_t data,
1157 __out efx_vpd_tag_t *tagp,
1158 __out efx_vpd_keyword_t *keyword,
1159 __out_opt unsigned int *payloadp,
1160 __out_opt uint8_t *paylenp,
1161 __inout unsigned int *contp);
1163 extern __checkReturn efx_rc_t
1165 __in_bcount(size) caddr_t data,
1167 __in efx_vpd_value_t *evvp);
1169 #endif /* EFSYS_OPT_VPD */
1173 extern __checkReturn efx_rc_t
1174 efx_mcdi_set_workaround(
1175 __in efx_nic_t *enp,
1177 __in boolean_t enabled,
1178 __out_opt uint32_t *flagsp);
1180 extern __checkReturn efx_rc_t
1181 efx_mcdi_get_workarounds(
1182 __in efx_nic_t *enp,
1183 __out_opt uint32_t *implementedp,
1184 __out_opt uint32_t *enabledp);
1186 #endif /* EFSYS_OPT_MCDI */
1188 #if EFSYS_OPT_MAC_STATS
1191 * Closed range of stats (i.e. the first and the last are included).
1192 * The last must be greater or equal (if the range is one item only) to
1195 struct efx_mac_stats_range {
1196 efx_mac_stat_t first;
1197 efx_mac_stat_t last;
1201 efx_mac_stats_mask_add_ranges(
1202 __inout_bcount(mask_size) uint32_t *maskp,
1203 __in size_t mask_size,
1204 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1205 __in unsigned int rng_count);
1207 #endif /* EFSYS_OPT_MAC_STATS */
1213 #endif /* _SYS_EFX_IMPL_H */