2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_FILTER 0x00001000
76 #define EFX_MOD_LIC 0x00002000
78 #define EFX_RESET_PHY 0x00000001
79 #define EFX_RESET_RXQ_ERR 0x00000002
80 #define EFX_RESET_TXQ_ERR 0x00000004
82 typedef enum efx_mac_type_e {
90 typedef struct efx_ev_ops_s {
91 efx_rc_t (*eevo_init)(efx_nic_t *);
92 void (*eevo_fini)(efx_nic_t *);
93 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
94 efsys_mem_t *, size_t, uint32_t,
95 uint32_t, uint32_t, efx_evq_t *);
96 void (*eevo_qdestroy)(efx_evq_t *);
97 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
98 void (*eevo_qpost)(efx_evq_t *, uint16_t);
99 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
101 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
105 typedef struct efx_tx_ops_s {
106 efx_rc_t (*etxo_init)(efx_nic_t *);
107 void (*etxo_fini)(efx_nic_t *);
108 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
109 unsigned int, unsigned int,
110 efsys_mem_t *, size_t,
112 efx_evq_t *, efx_txq_t *,
114 void (*etxo_qdestroy)(efx_txq_t *);
115 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
116 unsigned int, unsigned int,
118 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
119 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
120 efx_rc_t (*etxo_qflush)(efx_txq_t *);
121 void (*etxo_qenable)(efx_txq_t *);
122 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
123 void (*etxo_qpio_disable)(efx_txq_t *);
124 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
126 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
128 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
129 unsigned int, unsigned int,
131 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143 void (*etxo_qstats_update)(efx_txq_t *,
148 typedef struct efx_rx_ops_s {
149 efx_rc_t (*erxo_init)(efx_nic_t *);
150 void (*erxo_fini)(efx_nic_t *);
151 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
153 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
154 unsigned int, unsigned int,
156 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
157 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
158 void (*erxo_qenable)(efx_rxq_t *);
159 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
160 unsigned int, efx_rxq_type_t,
161 efsys_mem_t *, size_t, uint32_t,
162 efx_evq_t *, efx_rxq_t *);
163 void (*erxo_qdestroy)(efx_rxq_t *);
166 typedef struct efx_mac_ops_s {
167 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
168 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
169 efx_rc_t (*emo_addr_set)(efx_nic_t *);
170 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
171 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
172 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
173 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
174 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
175 efx_rxq_t *, boolean_t);
176 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
179 typedef struct efx_phy_ops_s {
180 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
181 efx_rc_t (*epo_reset)(efx_nic_t *);
182 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
183 efx_rc_t (*epo_verify)(efx_nic_t *);
184 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
186 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
187 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
188 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
189 efx_bist_result_t *, uint32_t *,
190 unsigned long *, size_t);
191 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
192 #endif /* EFSYS_OPT_BIST */
196 typedef struct efx_filter_ops_s {
197 efx_rc_t (*efo_init)(efx_nic_t *);
198 void (*efo_fini)(efx_nic_t *);
199 efx_rc_t (*efo_restore)(efx_nic_t *);
200 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
201 boolean_t may_replace);
202 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
203 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
204 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
205 boolean_t, boolean_t, boolean_t,
206 uint8_t const *, uint32_t);
209 extern __checkReturn efx_rc_t
210 efx_filter_reconfigure(
212 __in_ecount(6) uint8_t const *mac_addr,
213 __in boolean_t all_unicst,
214 __in boolean_t mulcst,
215 __in boolean_t all_mulcst,
216 __in boolean_t brdcst,
217 __in_ecount(6*count) uint8_t const *addrs,
218 __in uint32_t count);
220 #endif /* EFSYS_OPT_FILTER */
223 typedef struct efx_port_s {
224 efx_mac_type_t ep_mac_type;
225 uint32_t ep_phy_type;
228 uint8_t ep_mac_addr[6];
229 efx_link_mode_t ep_link_mode;
230 boolean_t ep_all_unicst;
232 boolean_t ep_all_mulcst;
234 unsigned int ep_fcntl;
235 boolean_t ep_fcntl_autoneg;
236 efx_oword_t ep_multicst_hash[2];
237 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
238 EFX_MAC_MULTICAST_LIST_MAX];
239 uint32_t ep_mulcst_addr_count;
240 efx_phy_media_type_t ep_fixed_port_type;
241 efx_phy_media_type_t ep_module_type;
242 uint32_t ep_adv_cap_mask;
243 uint32_t ep_lp_cap_mask;
244 uint32_t ep_default_adv_cap_mask;
245 uint32_t ep_phy_cap_mask;
246 boolean_t ep_mac_drain;
247 boolean_t ep_mac_stats_pending;
249 efx_bist_type_t ep_current_bist;
251 const efx_mac_ops_t *ep_emop;
252 const efx_phy_ops_t *ep_epop;
255 typedef struct efx_mon_ops_s {
258 typedef struct efx_mon_s {
259 efx_mon_type_t em_type;
260 const efx_mon_ops_t *em_emop;
263 typedef struct efx_intr_ops_s {
264 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
265 void (*eio_enable)(efx_nic_t *);
266 void (*eio_disable)(efx_nic_t *);
267 void (*eio_disable_unlocked)(efx_nic_t *);
268 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
269 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
270 void (*eio_status_message)(efx_nic_t *, unsigned int,
272 void (*eio_fatal)(efx_nic_t *);
273 void (*eio_fini)(efx_nic_t *);
276 typedef struct efx_intr_s {
277 const efx_intr_ops_t *ei_eiop;
278 efsys_mem_t *ei_esmp;
279 efx_intr_type_t ei_type;
280 unsigned int ei_level;
283 typedef struct efx_nic_ops_s {
284 efx_rc_t (*eno_probe)(efx_nic_t *);
285 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
286 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
287 efx_rc_t (*eno_reset)(efx_nic_t *);
288 efx_rc_t (*eno_init)(efx_nic_t *);
289 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
290 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
291 uint32_t *, size_t *);
293 efx_rc_t (*eno_register_test)(efx_nic_t *);
294 #endif /* EFSYS_OPT_DIAG */
295 void (*eno_fini)(efx_nic_t *);
296 void (*eno_unprobe)(efx_nic_t *);
299 #ifndef EFX_TXQ_LIMIT_TARGET
300 #define EFX_TXQ_LIMIT_TARGET 259
302 #ifndef EFX_RXQ_LIMIT_TARGET
303 #define EFX_RXQ_LIMIT_TARGET 512
305 #ifndef EFX_TXQ_DC_SIZE
306 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
308 #ifndef EFX_RXQ_DC_SIZE
309 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
316 typedef struct siena_filter_spec_s {
319 uint32_t sfs_dmaq_id;
320 uint32_t sfs_dword[3];
321 } siena_filter_spec_t;
323 typedef enum siena_filter_type_e {
324 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
325 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
326 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
327 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
328 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
329 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
331 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
332 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
333 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
334 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
335 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
336 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
338 EFX_SIENA_FILTER_NTYPES
339 } siena_filter_type_t;
341 typedef enum siena_filter_tbl_id_e {
342 EFX_SIENA_FILTER_TBL_RX_IP = 0,
343 EFX_SIENA_FILTER_TBL_RX_MAC,
344 EFX_SIENA_FILTER_TBL_TX_IP,
345 EFX_SIENA_FILTER_TBL_TX_MAC,
346 EFX_SIENA_FILTER_NTBLS
347 } siena_filter_tbl_id_t;
349 typedef struct siena_filter_tbl_s {
350 int sft_size; /* number of entries */
351 int sft_used; /* active count */
352 uint32_t *sft_bitmap; /* active bitmap */
353 siena_filter_spec_t *sft_spec; /* array of saved specs */
354 } siena_filter_tbl_t;
356 typedef struct siena_filter_s {
357 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
358 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
361 #endif /* EFSYS_OPT_SIENA */
363 typedef struct efx_filter_s {
365 siena_filter_t *ef_siena_filter;
366 #endif /* EFSYS_OPT_SIENA */
367 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
368 ef10_filter_table_t *ef_ef10_filter_table;
369 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
375 siena_filter_tbl_clear(
377 __in siena_filter_tbl_id_t tbl);
379 #endif /* EFSYS_OPT_SIENA */
381 #endif /* EFSYS_OPT_FILTER */
385 typedef struct efx_mcdi_ops_s {
386 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
387 void (*emco_send_request)(efx_nic_t *, void *, size_t,
389 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
390 boolean_t (*emco_poll_response)(efx_nic_t *);
391 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
392 void (*emco_fini)(efx_nic_t *);
393 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
394 efx_mcdi_feature_id_t, boolean_t *);
395 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
399 typedef struct efx_mcdi_s {
400 const efx_mcdi_ops_t *em_emcop;
401 const efx_mcdi_transport_t *em_emtp;
402 efx_mcdi_iface_t em_emip;
405 #endif /* EFSYS_OPT_MCDI */
407 typedef struct efx_drv_cfg_s {
408 uint32_t edc_min_vi_count;
409 uint32_t edc_max_vi_count;
411 uint32_t edc_max_piobuf_count;
412 uint32_t edc_pio_alloc_size;
417 efx_family_t en_family;
418 uint32_t en_features;
419 efsys_identifier_t *en_esip;
420 efsys_lock_t *en_eslp;
421 efsys_bar_t *en_esbp;
422 unsigned int en_mod_flags;
423 unsigned int en_reset_flags;
424 efx_nic_cfg_t en_nic_cfg;
425 efx_drv_cfg_t en_drv_cfg;
429 uint32_t en_ev_qcount;
430 uint32_t en_rx_qcount;
431 uint32_t en_tx_qcount;
432 const efx_nic_ops_t *en_enop;
433 const efx_ev_ops_t *en_eevop;
434 const efx_tx_ops_t *en_etxop;
435 const efx_rx_ops_t *en_erxop;
437 efx_filter_t en_filter;
438 const efx_filter_ops_t *en_efop;
439 #endif /* EFSYS_OPT_FILTER */
442 #endif /* EFSYS_OPT_MCDI */
443 uint32_t en_vport_id;
449 #endif /* EFSYS_OPT_SIENA */
452 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
458 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
459 uint32_t ena_piobuf_count;
460 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
461 uint32_t ena_pio_write_vi_base;
462 /* Memory BAR mapping regions */
463 uint32_t ena_uc_mem_map_offset;
464 size_t ena_uc_mem_map_size;
465 uint32_t ena_wc_mem_map_offset;
466 size_t ena_wc_mem_map_size;
469 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
473 #define EFX_NIC_MAGIC 0x02121996
475 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
476 const efx_ev_callbacks_t *, void *);
478 typedef struct efx_evq_rxq_state_s {
479 unsigned int eers_rx_read_ptr;
480 unsigned int eers_rx_mask;
481 } efx_evq_rxq_state_t;
486 unsigned int ee_index;
487 unsigned int ee_mask;
488 efsys_mem_t *ee_esmp;
490 uint32_t ee_stat[EV_NQSTATS];
491 #endif /* EFSYS_OPT_QSTATS */
493 efx_ev_handler_t ee_rx;
494 efx_ev_handler_t ee_tx;
495 efx_ev_handler_t ee_driver;
496 efx_ev_handler_t ee_global;
497 efx_ev_handler_t ee_drv_gen;
499 efx_ev_handler_t ee_mcdi;
500 #endif /* EFSYS_OPT_MCDI */
502 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
507 #define EFX_EVQ_MAGIC 0x08081997
509 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
515 unsigned int er_index;
516 unsigned int er_label;
517 unsigned int er_mask;
518 efsys_mem_t *er_esmp;
521 #define EFX_RXQ_MAGIC 0x15022005
526 unsigned int et_index;
527 unsigned int et_mask;
528 efsys_mem_t *et_esmp;
529 #if EFSYS_OPT_HUNTINGTON
530 uint32_t et_pio_bufnum;
531 uint32_t et_pio_blknum;
532 uint32_t et_pio_write_offset;
533 uint32_t et_pio_offset;
537 uint32_t et_stat[TX_NQSTATS];
538 #endif /* EFSYS_OPT_QSTATS */
541 #define EFX_TXQ_MAGIC 0x05092005
543 #define EFX_MAC_ADDR_COPY(_dst, _src) \
545 (_dst)[0] = (_src)[0]; \
546 (_dst)[1] = (_src)[1]; \
547 (_dst)[2] = (_src)[2]; \
548 (_dst)[3] = (_src)[3]; \
549 (_dst)[4] = (_src)[4]; \
550 (_dst)[5] = (_src)[5]; \
551 _NOTE(CONSTANTCONDITION) \
554 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
556 uint16_t *_d = (uint16_t *)(_dst); \
560 _NOTE(CONSTANTCONDITION) \
563 #if EFSYS_OPT_CHECK_REG
564 #define EFX_CHECK_REG(_enp, _reg) \
566 const char *name = #_reg; \
567 char min = name[4]; \
568 char max = name[5]; \
571 switch ((_enp)->en_family) { \
572 case EFX_FAMILY_SIENA: \
576 case EFX_FAMILY_HUNTINGTON: \
580 case EFX_FAMILY_MEDFORD: \
589 EFSYS_ASSERT3S(rev, >=, min); \
590 EFSYS_ASSERT3S(rev, <=, max); \
592 _NOTE(CONSTANTCONDITION) \
595 #define EFX_CHECK_REG(_enp, _reg) do { \
596 _NOTE(CONSTANTCONDITION) \
600 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
602 EFX_CHECK_REG((_enp), (_reg)); \
603 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
605 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
606 uint32_t, _reg ## _OFST, \
607 uint32_t, (_edp)->ed_u32[0]); \
608 _NOTE(CONSTANTCONDITION) \
611 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
613 EFX_CHECK_REG((_enp), (_reg)); \
614 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
615 uint32_t, _reg ## _OFST, \
616 uint32_t, (_edp)->ed_u32[0]); \
617 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
619 _NOTE(CONSTANTCONDITION) \
622 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
624 EFX_CHECK_REG((_enp), (_reg)); \
625 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
627 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
628 uint32_t, _reg ## _OFST, \
629 uint32_t, (_eqp)->eq_u32[1], \
630 uint32_t, (_eqp)->eq_u32[0]); \
631 _NOTE(CONSTANTCONDITION) \
634 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
636 EFX_CHECK_REG((_enp), (_reg)); \
637 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
638 uint32_t, _reg ## _OFST, \
639 uint32_t, (_eqp)->eq_u32[1], \
640 uint32_t, (_eqp)->eq_u32[0]); \
641 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
643 _NOTE(CONSTANTCONDITION) \
646 #define EFX_BAR_READO(_enp, _reg, _eop) \
648 EFX_CHECK_REG((_enp), (_reg)); \
649 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
651 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
652 uint32_t, _reg ## _OFST, \
653 uint32_t, (_eop)->eo_u32[3], \
654 uint32_t, (_eop)->eo_u32[2], \
655 uint32_t, (_eop)->eo_u32[1], \
656 uint32_t, (_eop)->eo_u32[0]); \
657 _NOTE(CONSTANTCONDITION) \
660 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
662 EFX_CHECK_REG((_enp), (_reg)); \
663 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
664 uint32_t, _reg ## _OFST, \
665 uint32_t, (_eop)->eo_u32[3], \
666 uint32_t, (_eop)->eo_u32[2], \
667 uint32_t, (_eop)->eo_u32[1], \
668 uint32_t, (_eop)->eo_u32[0]); \
669 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
671 _NOTE(CONSTANTCONDITION) \
674 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
676 EFX_CHECK_REG((_enp), (_reg)); \
677 EFSYS_BAR_READD((_enp)->en_esbp, \
678 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
680 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
681 uint32_t, (_index), \
682 uint32_t, _reg ## _OFST, \
683 uint32_t, (_edp)->ed_u32[0]); \
684 _NOTE(CONSTANTCONDITION) \
687 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
689 EFX_CHECK_REG((_enp), (_reg)); \
690 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
691 uint32_t, (_index), \
692 uint32_t, _reg ## _OFST, \
693 uint32_t, (_edp)->ed_u32[0]); \
694 EFSYS_BAR_WRITED((_enp)->en_esbp, \
695 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
697 _NOTE(CONSTANTCONDITION) \
700 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
702 EFX_CHECK_REG((_enp), (_reg)); \
703 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
704 uint32_t, (_index), \
705 uint32_t, _reg ## _OFST, \
706 uint32_t, (_edp)->ed_u32[0]); \
707 EFSYS_BAR_WRITED((_enp)->en_esbp, \
709 (2 * sizeof (efx_dword_t)) + \
710 ((_index) * _reg ## _STEP)), \
712 _NOTE(CONSTANTCONDITION) \
715 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
717 EFX_CHECK_REG((_enp), (_reg)); \
718 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
719 uint32_t, (_index), \
720 uint32_t, _reg ## _OFST, \
721 uint32_t, (_edp)->ed_u32[0]); \
722 EFSYS_BAR_WRITED((_enp)->en_esbp, \
724 (3 * sizeof (efx_dword_t)) + \
725 ((_index) * _reg ## _STEP)), \
727 _NOTE(CONSTANTCONDITION) \
730 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
732 EFX_CHECK_REG((_enp), (_reg)); \
733 EFSYS_BAR_READQ((_enp)->en_esbp, \
734 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
736 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
737 uint32_t, (_index), \
738 uint32_t, _reg ## _OFST, \
739 uint32_t, (_eqp)->eq_u32[1], \
740 uint32_t, (_eqp)->eq_u32[0]); \
741 _NOTE(CONSTANTCONDITION) \
744 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
746 EFX_CHECK_REG((_enp), (_reg)); \
747 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
748 uint32_t, (_index), \
749 uint32_t, _reg ## _OFST, \
750 uint32_t, (_eqp)->eq_u32[1], \
751 uint32_t, (_eqp)->eq_u32[0]); \
752 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
753 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
755 _NOTE(CONSTANTCONDITION) \
758 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
760 EFX_CHECK_REG((_enp), (_reg)); \
761 EFSYS_BAR_READO((_enp)->en_esbp, \
762 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
764 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
765 uint32_t, (_index), \
766 uint32_t, _reg ## _OFST, \
767 uint32_t, (_eop)->eo_u32[3], \
768 uint32_t, (_eop)->eo_u32[2], \
769 uint32_t, (_eop)->eo_u32[1], \
770 uint32_t, (_eop)->eo_u32[0]); \
771 _NOTE(CONSTANTCONDITION) \
774 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
776 EFX_CHECK_REG((_enp), (_reg)); \
777 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
778 uint32_t, (_index), \
779 uint32_t, _reg ## _OFST, \
780 uint32_t, (_eop)->eo_u32[3], \
781 uint32_t, (_eop)->eo_u32[2], \
782 uint32_t, (_eop)->eo_u32[1], \
783 uint32_t, (_eop)->eo_u32[0]); \
784 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
785 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
787 _NOTE(CONSTANTCONDITION) \
791 * Allow drivers to perform optimised 128-bit doorbell writes.
792 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
793 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
794 * the need for locking in the host, and are the only ones known to be safe to
795 * use 128-bites write with.
797 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
799 EFX_CHECK_REG((_enp), (_reg)); \
800 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
803 uint32_t, (_index), \
804 uint32_t, _reg ## _OFST, \
805 uint32_t, (_eop)->eo_u32[3], \
806 uint32_t, (_eop)->eo_u32[2], \
807 uint32_t, (_eop)->eo_u32[1], \
808 uint32_t, (_eop)->eo_u32[0]); \
809 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
810 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
812 _NOTE(CONSTANTCONDITION) \
815 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
817 unsigned int _new = (_wptr); \
818 unsigned int _old = (_owptr); \
820 if ((_new) >= (_old)) \
821 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
822 (_old) * sizeof (efx_desc_t), \
823 ((_new) - (_old)) * sizeof (efx_desc_t)); \
826 * It is cheaper to sync entire map than sync \
827 * two parts especially when offset/size are \
828 * ignored and entire map is synced in any case.\
830 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
832 (_entries) * sizeof (efx_desc_t)); \
833 _NOTE(CONSTANTCONDITION) \
836 extern __checkReturn efx_rc_t
838 __in efx_nic_t *enp);
840 extern __checkReturn efx_rc_t
842 __in efx_nic_t *enp);
845 efx_mac_multicast_hash_compute(
846 __in_ecount(6*count) uint8_t const *addrs,
848 __out efx_oword_t *hash_low,
849 __out efx_oword_t *hash_high);
851 extern __checkReturn efx_rc_t
853 __in efx_nic_t *enp);
857 __in efx_nic_t *enp);
861 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
863 typedef struct efx_register_set_s {
864 unsigned int address;
868 } efx_register_set_t;
870 extern __checkReturn efx_rc_t
871 efx_nic_test_registers(
873 __in efx_register_set_t *rsp,
876 extern __checkReturn efx_rc_t
879 __in efx_register_set_t *rsp,
880 __in efx_pattern_type_t pattern,
883 #endif /* EFSYS_OPT_DIAG */
887 extern __checkReturn efx_rc_t
888 efx_mcdi_set_workaround(
891 __in boolean_t enabled,
892 __out_opt uint32_t *flagsp);
894 extern __checkReturn efx_rc_t
895 efx_mcdi_get_workarounds(
897 __out_opt uint32_t *implementedp,
898 __out_opt uint32_t *enabledp);
900 #endif /* EFSYS_OPT_MCDI */
906 #endif /* _SYS_EFX_IMPL_H */