drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 } efx_ev_ops_t;
 101
 102 typedef struct efx_tx_ops_s {
 103         efx_rc_t        (*etxo_init)(efx_nic_t *);
 104         void            (*etxo_fini)(efx_nic_t *);
 105         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 106                                         unsigned int, unsigned int,
 107                                         efsys_mem_t *, size_t,
 108                                         uint32_t, uint16_t,
 109                                         efx_evq_t *, efx_txq_t *,
 110                                         unsigned int *);
 111         void            (*etxo_qdestroy)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 113                                       unsigned int, unsigned int,
 114                                       unsigned int *);
 115         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 116         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 117         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 118         void            (*etxo_qenable)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 120         void            (*etxo_qpio_disable)(efx_txq_t *);
 121         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 122                                            size_t);
 123         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 124                                            unsigned int *);
 125         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 126                                       unsigned int, unsigned int,
 127                                       unsigned int *);
 128         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 129                                                 size_t, boolean_t,
 130                                                 efx_desc_t *);
 131         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 132                                                 uint32_t, uint8_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint16_t,
 136                                                 efx_desc_t *, int);
 137         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 138                                                 efx_desc_t *);
 139 } efx_tx_ops_t;
 140
 141 typedef struct efx_rx_ops_s {
 142         efx_rc_t        (*erxo_init)(efx_nic_t *);
 143         void            (*erxo_fini)(efx_nic_t *);
 144         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 145                                               uint16_t *);
 146         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 147                                       unsigned int, unsigned int,
 148                                       unsigned int);
 149         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 150         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 151         void            (*erxo_qenable)(efx_rxq_t *);
 152         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 153                                         unsigned int, efx_rxq_type_t,
 154                                         efsys_mem_t *, size_t, uint32_t,
 155                                         efx_evq_t *, efx_rxq_t *);
 156         void            (*erxo_qdestroy)(efx_rxq_t *);
 157 } efx_rx_ops_t;
 158
 159 typedef struct efx_mac_ops_s {
 160         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 161         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 162         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 163         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 164         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 165         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 166         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 167         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 168                                                       efx_rxq_t *, boolean_t);
 169         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 170 } efx_mac_ops_t;
 171
 172 typedef struct efx_phy_ops_s {
 173         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 174         efx_rc_t        (*epo_reset)(efx_nic_t *);
 175         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 176         efx_rc_t        (*epo_verify)(efx_nic_t *);
 177         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 178 } efx_phy_ops_t;
 179
 180 #if EFSYS_OPT_FILTER
 181 typedef struct efx_filter_ops_s {
 182         efx_rc_t        (*efo_init)(efx_nic_t *);
 183         void            (*efo_fini)(efx_nic_t *);
 184         efx_rc_t        (*efo_restore)(efx_nic_t *);
 185         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 186                                    boolean_t may_replace);
 187         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 188         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 189         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 190                                    boolean_t, boolean_t, boolean_t,
 191                                    uint8_t const *, uint32_t);
 192 } efx_filter_ops_t;
 193
 194 extern  __checkReturn   efx_rc_t
 195 efx_filter_reconfigure(
 196         __in                            efx_nic_t *enp,
 197         __in_ecount(6)                  uint8_t const *mac_addr,
 198         __in                            boolean_t all_unicst,
 199         __in                            boolean_t mulcst,
 200         __in                            boolean_t all_mulcst,
 201         __in                            boolean_t brdcst,
 202         __in_ecount(6*count)            uint8_t const *addrs,
 203         __in                            uint32_t count);
 204
 205 #endif /* EFSYS_OPT_FILTER */
 206
 207
 208 typedef struct efx_port_s {
 209         efx_mac_type_t          ep_mac_type;
 210         uint32_t                ep_phy_type;
 211         uint8_t                 ep_port;
 212         uint32_t                ep_mac_pdu;
 213         uint8_t                 ep_mac_addr[6];
 214         efx_link_mode_t         ep_link_mode;
 215         boolean_t               ep_all_unicst;
 216         boolean_t               ep_mulcst;
 217         boolean_t               ep_all_mulcst;
 218         boolean_t               ep_brdcst;
 219         unsigned int            ep_fcntl;
 220         boolean_t               ep_fcntl_autoneg;
 221         efx_oword_t             ep_multicst_hash[2];
 222         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 223                                                     EFX_MAC_MULTICAST_LIST_MAX];
 224         uint32_t                ep_mulcst_addr_count;
 225         efx_phy_media_type_t    ep_fixed_port_type;
 226         efx_phy_media_type_t    ep_module_type;
 227         uint32_t                ep_adv_cap_mask;
 228         uint32_t                ep_lp_cap_mask;
 229         uint32_t                ep_default_adv_cap_mask;
 230         uint32_t                ep_phy_cap_mask;
 231         boolean_t               ep_mac_drain;
 232         boolean_t               ep_mac_stats_pending;
 233         const efx_mac_ops_t     *ep_emop;
 234         const efx_phy_ops_t     *ep_epop;
 235 } efx_port_t;
 236
 237 typedef struct efx_mon_ops_s {
 238 } efx_mon_ops_t;
 239
 240 typedef struct efx_mon_s {
 241         efx_mon_type_t          em_type;
 242         const efx_mon_ops_t     *em_emop;
 243 } efx_mon_t;
 244
 245 typedef struct efx_intr_ops_s {
 246         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 247         void            (*eio_enable)(efx_nic_t *);
 248         void            (*eio_disable)(efx_nic_t *);
 249         void            (*eio_disable_unlocked)(efx_nic_t *);
 250         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 251         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 252         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 253                                  boolean_t *);
 254         void            (*eio_fatal)(efx_nic_t *);
 255         void            (*eio_fini)(efx_nic_t *);
 256 } efx_intr_ops_t;
 257
 258 typedef struct efx_intr_s {
 259         const efx_intr_ops_t    *ei_eiop;
 260         efsys_mem_t             *ei_esmp;
 261         efx_intr_type_t         ei_type;
 262         unsigned int            ei_level;
 263 } efx_intr_t;
 264
 265 typedef struct efx_nic_ops_s {
 266         efx_rc_t        (*eno_probe)(efx_nic_t *);
 267         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 268         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 269         efx_rc_t        (*eno_reset)(efx_nic_t *);
 270         efx_rc_t        (*eno_init)(efx_nic_t *);
 271         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 272         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 273                                         uint32_t *, size_t *);
 274 #if EFSYS_OPT_DIAG
 275         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 276 #endif  /* EFSYS_OPT_DIAG */
 277         void            (*eno_fini)(efx_nic_t *);
 278         void            (*eno_unprobe)(efx_nic_t *);
 279 } efx_nic_ops_t;
 280
 281 #ifndef EFX_TXQ_LIMIT_TARGET
 282 #define EFX_TXQ_LIMIT_TARGET 259
 283 #endif
 284 #ifndef EFX_RXQ_LIMIT_TARGET
 285 #define EFX_RXQ_LIMIT_TARGET 512
 286 #endif
 287 #ifndef EFX_TXQ_DC_SIZE
 288 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 289 #endif
 290 #ifndef EFX_RXQ_DC_SIZE
 291 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 292 #endif
 293
 294 #if EFSYS_OPT_FILTER
 295
 296 #if EFSYS_OPT_SIENA
 297
 298 typedef struct siena_filter_spec_s {
 299         uint8_t         sfs_type;
 300         uint32_t        sfs_flags;
 301         uint32_t        sfs_dmaq_id;
 302         uint32_t        sfs_dword[3];
 303 } siena_filter_spec_t;
 304
 305 typedef enum siena_filter_type_e {
 306         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 307         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 308         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 309         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 310         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 311         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 312
 313         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 314         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 315         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 316         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 317         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 318         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 319
 320         EFX_SIENA_FILTER_NTYPES
 321 } siena_filter_type_t;
 322
 323 typedef enum siena_filter_tbl_id_e {
 324         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 325         EFX_SIENA_FILTER_TBL_RX_MAC,
 326         EFX_SIENA_FILTER_TBL_TX_IP,
 327         EFX_SIENA_FILTER_TBL_TX_MAC,
 328         EFX_SIENA_FILTER_NTBLS
 329 } siena_filter_tbl_id_t;
 330
 331 typedef struct siena_filter_tbl_s {
 332         int                     sft_size;       /* number of entries */
 333         int                     sft_used;       /* active count */
 334         uint32_t                *sft_bitmap;    /* active bitmap */
 335         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 336 } siena_filter_tbl_t;
 337
 338 typedef struct siena_filter_s {
 339         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 340         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 341 } siena_filter_t;
 342
 343 #endif  /* EFSYS_OPT_SIENA */
 344
 345 typedef struct efx_filter_s {
 346 #if EFSYS_OPT_SIENA
 347         siena_filter_t          *ef_siena_filter;
 348 #endif /* EFSYS_OPT_SIENA */
 349 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 350         ef10_filter_table_t     *ef_ef10_filter_table;
 351 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 352 } efx_filter_t;
 353
 354 #if EFSYS_OPT_SIENA
 355
 356 extern                  void
 357 siena_filter_tbl_clear(
 358         __in            efx_nic_t *enp,
 359         __in            siena_filter_tbl_id_t tbl);
 360
 361 #endif  /* EFSYS_OPT_SIENA */
 362
 363 #endif  /* EFSYS_OPT_FILTER */
 364
 365 #if EFSYS_OPT_MCDI
 366
 367 typedef struct efx_mcdi_ops_s {
 368         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 369         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 370                                         void *, size_t);
 371         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 372         boolean_t       (*emco_poll_response)(efx_nic_t *);
 373         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 374         void            (*emco_fini)(efx_nic_t *);
 375         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 376                                             efx_mcdi_feature_id_t, boolean_t *);
 377         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 378                                             uint32_t *);
 379 } efx_mcdi_ops_t;
 380
 381 typedef struct efx_mcdi_s {
 382         const efx_mcdi_ops_t            *em_emcop;
 383         const efx_mcdi_transport_t      *em_emtp;
 384         efx_mcdi_iface_t                em_emip;
 385 } efx_mcdi_t;
 386
 387 #endif /* EFSYS_OPT_MCDI */
 388
 389 typedef struct efx_drv_cfg_s {
 390         uint32_t                edc_min_vi_count;
 391         uint32_t                edc_max_vi_count;
 392
 393         uint32_t                edc_max_piobuf_count;
 394         uint32_t                edc_pio_alloc_size;
 395 } efx_drv_cfg_t;
 396
 397 struct efx_nic_s {
 398         uint32_t                en_magic;
 399         efx_family_t            en_family;
 400         uint32_t                en_features;
 401         efsys_identifier_t      *en_esip;
 402         efsys_lock_t            *en_eslp;
 403         efsys_bar_t             *en_esbp;
 404         unsigned int            en_mod_flags;
 405         unsigned int            en_reset_flags;
 406         efx_nic_cfg_t           en_nic_cfg;
 407         efx_drv_cfg_t           en_drv_cfg;
 408         efx_port_t              en_port;
 409         efx_mon_t               en_mon;
 410         efx_intr_t              en_intr;
 411         uint32_t                en_ev_qcount;
 412         uint32_t                en_rx_qcount;
 413         uint32_t                en_tx_qcount;
 414         const efx_nic_ops_t     *en_enop;
 415         const efx_ev_ops_t      *en_eevop;
 416         const efx_tx_ops_t      *en_etxop;
 417         const efx_rx_ops_t      *en_erxop;
 418 #if EFSYS_OPT_FILTER
 419         efx_filter_t            en_filter;
 420         const efx_filter_ops_t  *en_efop;
 421 #endif  /* EFSYS_OPT_FILTER */
 422 #if EFSYS_OPT_MCDI
 423         efx_mcdi_t              en_mcdi;
 424 #endif  /* EFSYS_OPT_MCDI */
 425         uint32_t                en_vport_id;
 426         union {
 427 #if EFSYS_OPT_SIENA
 428                 struct {
 429                         int                     enu_unused;
 430                 } siena;
 431 #endif  /* EFSYS_OPT_SIENA */
 432                 int     enu_unused;
 433         } en_u;
 434 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 435         union en_arch {
 436                 struct {
 437                         int                     ena_vi_base;
 438                         int                     ena_vi_count;
 439                         int                     ena_vi_shift;
 440                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 441                         uint32_t                ena_piobuf_count;
 442                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 443                         uint32_t                ena_pio_write_vi_base;
 444                         /* Memory BAR mapping regions */
 445                         uint32_t                ena_uc_mem_map_offset;
 446                         size_t                  ena_uc_mem_map_size;
 447                         uint32_t                ena_wc_mem_map_offset;
 448                         size_t                  ena_wc_mem_map_size;
 449                 } ef10;
 450         } en_arch;
 451 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 452 };
 453
 454
 455 #define EFX_NIC_MAGIC   0x02121996
 456
 457 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 458     const efx_ev_callbacks_t *, void *);
 459
 460 typedef struct efx_evq_rxq_state_s {
 461         unsigned int                    eers_rx_read_ptr;
 462         unsigned int                    eers_rx_mask;
 463 } efx_evq_rxq_state_t;
 464
 465 struct efx_evq_s {
 466         uint32_t                        ee_magic;
 467         efx_nic_t                       *ee_enp;
 468         unsigned int                    ee_index;
 469         unsigned int                    ee_mask;
 470         efsys_mem_t                     *ee_esmp;
 471
 472         efx_ev_handler_t                ee_rx;
 473         efx_ev_handler_t                ee_tx;
 474         efx_ev_handler_t                ee_driver;
 475         efx_ev_handler_t                ee_global;
 476         efx_ev_handler_t                ee_drv_gen;
 477 #if EFSYS_OPT_MCDI
 478         efx_ev_handler_t                ee_mcdi;
 479 #endif  /* EFSYS_OPT_MCDI */
 480
 481         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 482
 483         uint32_t                        ee_flags;
 484 };
 485
 486 #define EFX_EVQ_MAGIC   0x08081997
 487
 488 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 489
 490 struct efx_rxq_s {
 491         uint32_t                        er_magic;
 492         efx_nic_t                       *er_enp;
 493         efx_evq_t                       *er_eep;
 494         unsigned int                    er_index;
 495         unsigned int                    er_label;
 496         unsigned int                    er_mask;
 497         efsys_mem_t                     *er_esmp;
 498 };
 499
 500 #define EFX_RXQ_MAGIC   0x15022005
 501
 502 struct efx_txq_s {
 503         uint32_t                        et_magic;
 504         efx_nic_t                       *et_enp;
 505         unsigned int                    et_index;
 506         unsigned int                    et_mask;
 507         efsys_mem_t                     *et_esmp;
 508 #if EFSYS_OPT_HUNTINGTON
 509         uint32_t                        et_pio_bufnum;
 510         uint32_t                        et_pio_blknum;
 511         uint32_t                        et_pio_write_offset;
 512         uint32_t                        et_pio_offset;
 513         size_t                          et_pio_size;
 514 #endif
 515 };
 516
 517 #define EFX_TXQ_MAGIC   0x05092005
 518
 519 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 520         do {                                                            \
 521                 (_dst)[0] = (_src)[0];                                  \
 522                 (_dst)[1] = (_src)[1];                                  \
 523                 (_dst)[2] = (_src)[2];                                  \
 524                 (_dst)[3] = (_src)[3];                                  \
 525                 (_dst)[4] = (_src)[4];                                  \
 526                 (_dst)[5] = (_src)[5];                                  \
 527         _NOTE(CONSTANTCONDITION)                                        \
 528         } while (B_FALSE)
 529
 530 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 531         do {                                                            \
 532                 uint16_t *_d = (uint16_t *)(_dst);                      \
 533                 _d[0] = 0xffff;                                         \
 534                 _d[1] = 0xffff;                                         \
 535                 _d[2] = 0xffff;                                         \
 536         _NOTE(CONSTANTCONDITION)                                        \
 537         } while (B_FALSE)
 538
 539 #if EFSYS_OPT_CHECK_REG
 540 #define EFX_CHECK_REG(_enp, _reg)                                       \
 541         do {                                                            \
 542                 const char *name = #_reg;                               \
 543                 char min = name[4];                                     \
 544                 char max = name[5];                                     \
 545                 char rev;                                               \
 546                                                                         \
 547                 switch ((_enp)->en_family) {                            \
 548                 case EFX_FAMILY_SIENA:                                  \
 549                         rev = 'C';                                      \
 550                         break;                                          \
 551                                                                         \
 552                 case EFX_FAMILY_HUNTINGTON:                             \
 553                         rev = 'D';                                      \
 554                         break;                                          \
 555                                                                         \
 556                 case EFX_FAMILY_MEDFORD:                                \
 557                         rev = 'E';                                      \
 558                         break;                                          \
 559                                                                         \
 560                 default:                                                \
 561                         rev = '?';                                      \
 562                         break;                                          \
 563                 }                                                       \
 564                                                                         \
 565                 EFSYS_ASSERT3S(rev, >=, min);                           \
 566                 EFSYS_ASSERT3S(rev, <=, max);                           \
 567                                                                         \
 568         _NOTE(CONSTANTCONDITION)                                        \
 569         } while (B_FALSE)
 570 #else
 571 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 572         _NOTE(CONSTANTCONDITION)                                        \
 573         } while (B_FALSE)
 574 #endif
 575
 576 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 577         do {                                                            \
 578                 EFX_CHECK_REG((_enp), (_reg));                          \
 579                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 580                     (_edp), (_lock));                                   \
 581                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 582                     uint32_t, _reg ## _OFST,                            \
 583                     uint32_t, (_edp)->ed_u32[0]);                       \
 584         _NOTE(CONSTANTCONDITION)                                        \
 585         } while (B_FALSE)
 586
 587 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 588         do {                                                            \
 589                 EFX_CHECK_REG((_enp), (_reg));                          \
 590                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 591                     uint32_t, _reg ## _OFST,                            \
 592                     uint32_t, (_edp)->ed_u32[0]);                       \
 593                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 594                     (_edp), (_lock));                                   \
 595         _NOTE(CONSTANTCONDITION)                                        \
 596         } while (B_FALSE)
 597
 598 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 599         do {                                                            \
 600                 EFX_CHECK_REG((_enp), (_reg));                          \
 601                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 602                     (_eqp));                                            \
 603                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 604                     uint32_t, _reg ## _OFST,                            \
 605                     uint32_t, (_eqp)->eq_u32[1],                        \
 606                     uint32_t, (_eqp)->eq_u32[0]);                       \
 607         _NOTE(CONSTANTCONDITION)                                        \
 608         } while (B_FALSE)
 609
 610 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 611         do {                                                            \
 612                 EFX_CHECK_REG((_enp), (_reg));                          \
 613                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 614                     uint32_t, _reg ## _OFST,                            \
 615                     uint32_t, (_eqp)->eq_u32[1],                        \
 616                     uint32_t, (_eqp)->eq_u32[0]);                       \
 617                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 618                     (_eqp));                                            \
 619         _NOTE(CONSTANTCONDITION)                                        \
 620         } while (B_FALSE)
 621
 622 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 623         do {                                                            \
 624                 EFX_CHECK_REG((_enp), (_reg));                          \
 625                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 626                     (_eop), B_TRUE);                                    \
 627                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 628                     uint32_t, _reg ## _OFST,                            \
 629                     uint32_t, (_eop)->eo_u32[3],                        \
 630                     uint32_t, (_eop)->eo_u32[2],                        \
 631                     uint32_t, (_eop)->eo_u32[1],                        \
 632                     uint32_t, (_eop)->eo_u32[0]);                       \
 633         _NOTE(CONSTANTCONDITION)                                        \
 634         } while (B_FALSE)
 635
 636 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 637         do {                                                            \
 638                 EFX_CHECK_REG((_enp), (_reg));                          \
 639                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 640                     uint32_t, _reg ## _OFST,                            \
 641                     uint32_t, (_eop)->eo_u32[3],                        \
 642                     uint32_t, (_eop)->eo_u32[2],                        \
 643                     uint32_t, (_eop)->eo_u32[1],                        \
 644                     uint32_t, (_eop)->eo_u32[0]);                       \
 645                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 646                     (_eop), B_TRUE);                                    \
 647         _NOTE(CONSTANTCONDITION)                                        \
 648         } while (B_FALSE)
 649
 650 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 651         do {                                                            \
 652                 EFX_CHECK_REG((_enp), (_reg));                          \
 653                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 654                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 655                     (_edp), (_lock));                                   \
 656                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 657                     uint32_t, (_index),                                 \
 658                     uint32_t, _reg ## _OFST,                            \
 659                     uint32_t, (_edp)->ed_u32[0]);                       \
 660         _NOTE(CONSTANTCONDITION)                                        \
 661         } while (B_FALSE)
 662
 663 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 664         do {                                                            \
 665                 EFX_CHECK_REG((_enp), (_reg));                          \
 666                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 667                     uint32_t, (_index),                                 \
 668                     uint32_t, _reg ## _OFST,                            \
 669                     uint32_t, (_edp)->ed_u32[0]);                       \
 670                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 671                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 672                     (_edp), (_lock));                                   \
 673         _NOTE(CONSTANTCONDITION)                                        \
 674         } while (B_FALSE)
 675
 676 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 677         do {                                                            \
 678                 EFX_CHECK_REG((_enp), (_reg));                          \
 679                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 680                     uint32_t, (_index),                                 \
 681                     uint32_t, _reg ## _OFST,                            \
 682                     uint32_t, (_edp)->ed_u32[0]);                       \
 683                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 684                     (_reg ## _OFST +                                    \
 685                     (2 * sizeof (efx_dword_t)) +                        \
 686                     ((_index) * _reg ## _STEP)),                        \
 687                     (_edp), (_lock));                                   \
 688         _NOTE(CONSTANTCONDITION)                                        \
 689         } while (B_FALSE)
 690
 691 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 692         do {                                                            \
 693                 EFX_CHECK_REG((_enp), (_reg));                          \
 694                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 695                     uint32_t, (_index),                                 \
 696                     uint32_t, _reg ## _OFST,                            \
 697                     uint32_t, (_edp)->ed_u32[0]);                       \
 698                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 699                     (_reg ## _OFST +                                    \
 700                     (3 * sizeof (efx_dword_t)) +                        \
 701                     ((_index) * _reg ## _STEP)),                        \
 702                     (_edp), (_lock));                                   \
 703         _NOTE(CONSTANTCONDITION)                                        \
 704         } while (B_FALSE)
 705
 706 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 707         do {                                                            \
 708                 EFX_CHECK_REG((_enp), (_reg));                          \
 709                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 710                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 711                     (_eqp));                                            \
 712                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 713                     uint32_t, (_index),                                 \
 714                     uint32_t, _reg ## _OFST,                            \
 715                     uint32_t, (_eqp)->eq_u32[1],                        \
 716                     uint32_t, (_eqp)->eq_u32[0]);                       \
 717         _NOTE(CONSTANTCONDITION)                                        \
 718         } while (B_FALSE)
 719
 720 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 721         do {                                                            \
 722                 EFX_CHECK_REG((_enp), (_reg));                          \
 723                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 724                     uint32_t, (_index),                                 \
 725                     uint32_t, _reg ## _OFST,                            \
 726                     uint32_t, (_eqp)->eq_u32[1],                        \
 727                     uint32_t, (_eqp)->eq_u32[0]);                       \
 728                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 729                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 730                     (_eqp));                                            \
 731         _NOTE(CONSTANTCONDITION)                                        \
 732         } while (B_FALSE)
 733
 734 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 735         do {                                                            \
 736                 EFX_CHECK_REG((_enp), (_reg));                          \
 737                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 738                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 739                     (_eop), (_lock));                                   \
 740                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 741                     uint32_t, (_index),                                 \
 742                     uint32_t, _reg ## _OFST,                            \
 743                     uint32_t, (_eop)->eo_u32[3],                        \
 744                     uint32_t, (_eop)->eo_u32[2],                        \
 745                     uint32_t, (_eop)->eo_u32[1],                        \
 746                     uint32_t, (_eop)->eo_u32[0]);                       \
 747         _NOTE(CONSTANTCONDITION)                                        \
 748         } while (B_FALSE)
 749
 750 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 751         do {                                                            \
 752                 EFX_CHECK_REG((_enp), (_reg));                          \
 753                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 754                     uint32_t, (_index),                                 \
 755                     uint32_t, _reg ## _OFST,                            \
 756                     uint32_t, (_eop)->eo_u32[3],                        \
 757                     uint32_t, (_eop)->eo_u32[2],                        \
 758                     uint32_t, (_eop)->eo_u32[1],                        \
 759                     uint32_t, (_eop)->eo_u32[0]);                       \
 760                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 761                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 762                     (_eop), (_lock));                                   \
 763         _NOTE(CONSTANTCONDITION)                                        \
 764         } while (B_FALSE)
 765
 766 /*
 767  * Allow drivers to perform optimised 128-bit doorbell writes.
 768  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 769  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 770  * the need for locking in the host, and are the only ones known to be safe to
 771  * use 128-bites write with.
 772  */
 773 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 774         do {                                                            \
 775                 EFX_CHECK_REG((_enp), (_reg));                          \
 776                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 777                     const char *,                                       \
 778                     #_reg,                                              \
 779                     uint32_t, (_index),                                 \
 780                     uint32_t, _reg ## _OFST,                            \
 781                     uint32_t, (_eop)->eo_u32[3],                        \
 782                     uint32_t, (_eop)->eo_u32[2],                        \
 783                     uint32_t, (_eop)->eo_u32[1],                        \
 784                     uint32_t, (_eop)->eo_u32[0]);                       \
 785                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
 786                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 787                     (_eop));                                            \
 788         _NOTE(CONSTANTCONDITION)                                        \
 789         } while (B_FALSE)
 790
 791 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
 792         do {                                                            \
 793                 unsigned int _new = (_wptr);                            \
 794                 unsigned int _old = (_owptr);                           \
 795                                                                         \
 796                 if ((_new) >= (_old))                                   \
 797                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 798                             (_old) * sizeof (efx_desc_t),               \
 799                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
 800                 else                                                    \
 801                         /*                                              \
 802                          * It is cheaper to sync entire map than sync   \
 803                          * two parts especially when offset/size are    \
 804                          * ignored and entire map is synced in any case.\
 805                          */                                             \
 806                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 807                             0,                                          \
 808                             (_entries) * sizeof (efx_desc_t));          \
 809         _NOTE(CONSTANTCONDITION)                                        \
 810         } while (B_FALSE)
 811
 812 extern  __checkReturn   efx_rc_t
 813 efx_nic_biu_test(
 814         __in            efx_nic_t *enp);
 815
 816 extern  __checkReturn   efx_rc_t
 817 efx_mac_select(
 818         __in            efx_nic_t *enp);
 819
 820 extern  void
 821 efx_mac_multicast_hash_compute(
 822         __in_ecount(6*count)            uint8_t const *addrs,
 823         __in                            int count,
 824         __out                           efx_oword_t *hash_low,
 825         __out                           efx_oword_t *hash_high);
 826
 827 extern  __checkReturn   efx_rc_t
 828 efx_phy_probe(
 829         __in            efx_nic_t *enp);
 830
 831 extern                  void
 832 efx_phy_unprobe(
 833         __in            efx_nic_t *enp);
 834
 835 #if EFSYS_OPT_DIAG
 836
 837 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
 838
 839 typedef struct efx_register_set_s {
 840         unsigned int            address;
 841         unsigned int            step;
 842         unsigned int            rows;
 843         efx_oword_t             mask;
 844 } efx_register_set_t;
 845
 846 extern  __checkReturn   efx_rc_t
 847 efx_nic_test_registers(
 848         __in            efx_nic_t *enp,
 849         __in            efx_register_set_t *rsp,
 850         __in            size_t count);
 851
 852 extern  __checkReturn   efx_rc_t
 853 efx_nic_test_tables(
 854         __in            efx_nic_t *enp,
 855         __in            efx_register_set_t *rsp,
 856         __in            efx_pattern_type_t pattern,
 857         __in            size_t count);
 858
 859 #endif  /* EFSYS_OPT_DIAG */
 860
 861 #if EFSYS_OPT_MCDI
 862
 863 extern  __checkReturn           efx_rc_t
 864 efx_mcdi_set_workaround(
 865         __in                    efx_nic_t *enp,
 866         __in                    uint32_t type,
 867         __in                    boolean_t enabled,
 868         __out_opt               uint32_t *flagsp);
 869
 870 extern  __checkReturn           efx_rc_t
 871 efx_mcdi_get_workarounds(
 872         __in                    efx_nic_t *enp,
 873         __out_opt               uint32_t *implementedp,
 874         __out_opt               uint32_t *enabledp);
 875
 876 #endif /* EFSYS_OPT_MCDI */
 877
 878 #ifdef  __cplusplus
 879 }
 880 #endif
 881
 882 #endif  /* _SYS_EFX_IMPL_H */