2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_FILTER 0x00001000
76 #define EFX_MOD_LIC 0x00002000
78 #define EFX_RESET_PHY 0x00000001
79 #define EFX_RESET_RXQ_ERR 0x00000002
80 #define EFX_RESET_TXQ_ERR 0x00000004
82 typedef enum efx_mac_type_e {
90 typedef struct efx_ev_ops_s {
91 efx_rc_t (*eevo_init)(efx_nic_t *);
92 void (*eevo_fini)(efx_nic_t *);
93 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
94 efsys_mem_t *, size_t, uint32_t,
95 uint32_t, uint32_t, efx_evq_t *);
96 void (*eevo_qdestroy)(efx_evq_t *);
97 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
98 void (*eevo_qpost)(efx_evq_t *, uint16_t);
99 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
101 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
105 typedef struct efx_tx_ops_s {
106 efx_rc_t (*etxo_init)(efx_nic_t *);
107 void (*etxo_fini)(efx_nic_t *);
108 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
109 unsigned int, unsigned int,
110 efsys_mem_t *, size_t,
112 efx_evq_t *, efx_txq_t *,
114 void (*etxo_qdestroy)(efx_txq_t *);
115 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
116 unsigned int, unsigned int,
118 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
119 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
120 efx_rc_t (*etxo_qflush)(efx_txq_t *);
121 void (*etxo_qenable)(efx_txq_t *);
122 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
123 void (*etxo_qpio_disable)(efx_txq_t *);
124 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
126 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
128 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
129 unsigned int, unsigned int,
131 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143 void (*etxo_qstats_update)(efx_txq_t *,
148 typedef struct efx_rx_ops_s {
149 efx_rc_t (*erxo_init)(efx_nic_t *);
150 void (*erxo_fini)(efx_nic_t *);
151 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
153 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
154 unsigned int, unsigned int,
156 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
157 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
158 void (*erxo_qenable)(efx_rxq_t *);
159 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
160 unsigned int, efx_rxq_type_t,
161 efsys_mem_t *, size_t, uint32_t,
162 efx_evq_t *, efx_rxq_t *);
163 void (*erxo_qdestroy)(efx_rxq_t *);
166 typedef struct efx_mac_ops_s {
167 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
168 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
169 efx_rc_t (*emo_addr_set)(efx_nic_t *);
170 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
171 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
172 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
173 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
174 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
175 efx_rxq_t *, boolean_t);
176 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
177 #if EFSYS_OPT_MAC_STATS
178 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
179 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
180 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
181 uint16_t, boolean_t);
182 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
183 efsys_stat_t *, uint32_t *);
184 #endif /* EFSYS_OPT_MAC_STATS */
187 typedef struct efx_phy_ops_s {
188 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
189 efx_rc_t (*epo_reset)(efx_nic_t *);
190 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
191 efx_rc_t (*epo_verify)(efx_nic_t *);
192 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
193 #if EFSYS_OPT_PHY_STATS
194 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
196 #endif /* EFSYS_OPT_PHY_STATS */
198 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
199 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
200 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
201 efx_bist_result_t *, uint32_t *,
202 unsigned long *, size_t);
203 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
204 #endif /* EFSYS_OPT_BIST */
208 typedef struct efx_filter_ops_s {
209 efx_rc_t (*efo_init)(efx_nic_t *);
210 void (*efo_fini)(efx_nic_t *);
211 efx_rc_t (*efo_restore)(efx_nic_t *);
212 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
213 boolean_t may_replace);
214 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
215 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
216 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
217 boolean_t, boolean_t, boolean_t,
218 uint8_t const *, uint32_t);
221 extern __checkReturn efx_rc_t
222 efx_filter_reconfigure(
224 __in_ecount(6) uint8_t const *mac_addr,
225 __in boolean_t all_unicst,
226 __in boolean_t mulcst,
227 __in boolean_t all_mulcst,
228 __in boolean_t brdcst,
229 __in_ecount(6*count) uint8_t const *addrs,
230 __in uint32_t count);
232 #endif /* EFSYS_OPT_FILTER */
235 typedef struct efx_port_s {
236 efx_mac_type_t ep_mac_type;
237 uint32_t ep_phy_type;
240 uint8_t ep_mac_addr[6];
241 efx_link_mode_t ep_link_mode;
242 boolean_t ep_all_unicst;
244 boolean_t ep_all_mulcst;
246 unsigned int ep_fcntl;
247 boolean_t ep_fcntl_autoneg;
248 efx_oword_t ep_multicst_hash[2];
249 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
250 EFX_MAC_MULTICAST_LIST_MAX];
251 uint32_t ep_mulcst_addr_count;
252 #if EFSYS_OPT_PHY_FLAGS
253 uint32_t ep_phy_flags;
254 #endif /* EFSYS_OPT_PHY_FLAGS */
255 #if EFSYS_OPT_PHY_LED_CONTROL
256 efx_phy_led_mode_t ep_phy_led_mode;
257 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
258 efx_phy_media_type_t ep_fixed_port_type;
259 efx_phy_media_type_t ep_module_type;
260 uint32_t ep_adv_cap_mask;
261 uint32_t ep_lp_cap_mask;
262 uint32_t ep_default_adv_cap_mask;
263 uint32_t ep_phy_cap_mask;
264 boolean_t ep_mac_drain;
265 boolean_t ep_mac_stats_pending;
267 efx_bist_type_t ep_current_bist;
269 const efx_mac_ops_t *ep_emop;
270 const efx_phy_ops_t *ep_epop;
273 typedef struct efx_mon_ops_s {
276 typedef struct efx_mon_s {
277 efx_mon_type_t em_type;
278 const efx_mon_ops_t *em_emop;
281 typedef struct efx_intr_ops_s {
282 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
283 void (*eio_enable)(efx_nic_t *);
284 void (*eio_disable)(efx_nic_t *);
285 void (*eio_disable_unlocked)(efx_nic_t *);
286 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
287 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
288 void (*eio_status_message)(efx_nic_t *, unsigned int,
290 void (*eio_fatal)(efx_nic_t *);
291 void (*eio_fini)(efx_nic_t *);
294 typedef struct efx_intr_s {
295 const efx_intr_ops_t *ei_eiop;
296 efsys_mem_t *ei_esmp;
297 efx_intr_type_t ei_type;
298 unsigned int ei_level;
301 typedef struct efx_nic_ops_s {
302 efx_rc_t (*eno_probe)(efx_nic_t *);
303 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
304 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
305 efx_rc_t (*eno_reset)(efx_nic_t *);
306 efx_rc_t (*eno_init)(efx_nic_t *);
307 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
308 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
309 uint32_t *, size_t *);
311 efx_rc_t (*eno_register_test)(efx_nic_t *);
312 #endif /* EFSYS_OPT_DIAG */
313 void (*eno_fini)(efx_nic_t *);
314 void (*eno_unprobe)(efx_nic_t *);
317 #ifndef EFX_TXQ_LIMIT_TARGET
318 #define EFX_TXQ_LIMIT_TARGET 259
320 #ifndef EFX_RXQ_LIMIT_TARGET
321 #define EFX_RXQ_LIMIT_TARGET 512
323 #ifndef EFX_TXQ_DC_SIZE
324 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
326 #ifndef EFX_RXQ_DC_SIZE
327 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
334 typedef struct siena_filter_spec_s {
337 uint32_t sfs_dmaq_id;
338 uint32_t sfs_dword[3];
339 } siena_filter_spec_t;
341 typedef enum siena_filter_type_e {
342 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
343 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
344 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
345 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
346 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
347 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
349 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
350 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
351 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
352 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
353 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
354 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
356 EFX_SIENA_FILTER_NTYPES
357 } siena_filter_type_t;
359 typedef enum siena_filter_tbl_id_e {
360 EFX_SIENA_FILTER_TBL_RX_IP = 0,
361 EFX_SIENA_FILTER_TBL_RX_MAC,
362 EFX_SIENA_FILTER_TBL_TX_IP,
363 EFX_SIENA_FILTER_TBL_TX_MAC,
364 EFX_SIENA_FILTER_NTBLS
365 } siena_filter_tbl_id_t;
367 typedef struct siena_filter_tbl_s {
368 int sft_size; /* number of entries */
369 int sft_used; /* active count */
370 uint32_t *sft_bitmap; /* active bitmap */
371 siena_filter_spec_t *sft_spec; /* array of saved specs */
372 } siena_filter_tbl_t;
374 typedef struct siena_filter_s {
375 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
376 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
379 #endif /* EFSYS_OPT_SIENA */
381 typedef struct efx_filter_s {
383 siena_filter_t *ef_siena_filter;
384 #endif /* EFSYS_OPT_SIENA */
385 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
386 ef10_filter_table_t *ef_ef10_filter_table;
387 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
393 siena_filter_tbl_clear(
395 __in siena_filter_tbl_id_t tbl);
397 #endif /* EFSYS_OPT_SIENA */
399 #endif /* EFSYS_OPT_FILTER */
403 typedef struct efx_mcdi_ops_s {
404 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
405 void (*emco_send_request)(efx_nic_t *, void *, size_t,
407 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
408 boolean_t (*emco_poll_response)(efx_nic_t *);
409 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
410 void (*emco_fini)(efx_nic_t *);
411 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
412 efx_mcdi_feature_id_t, boolean_t *);
413 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
417 typedef struct efx_mcdi_s {
418 const efx_mcdi_ops_t *em_emcop;
419 const efx_mcdi_transport_t *em_emtp;
420 efx_mcdi_iface_t em_emip;
423 #endif /* EFSYS_OPT_MCDI */
425 typedef struct efx_drv_cfg_s {
426 uint32_t edc_min_vi_count;
427 uint32_t edc_max_vi_count;
429 uint32_t edc_max_piobuf_count;
430 uint32_t edc_pio_alloc_size;
435 efx_family_t en_family;
436 uint32_t en_features;
437 efsys_identifier_t *en_esip;
438 efsys_lock_t *en_eslp;
439 efsys_bar_t *en_esbp;
440 unsigned int en_mod_flags;
441 unsigned int en_reset_flags;
442 efx_nic_cfg_t en_nic_cfg;
443 efx_drv_cfg_t en_drv_cfg;
447 uint32_t en_ev_qcount;
448 uint32_t en_rx_qcount;
449 uint32_t en_tx_qcount;
450 const efx_nic_ops_t *en_enop;
451 const efx_ev_ops_t *en_eevop;
452 const efx_tx_ops_t *en_etxop;
453 const efx_rx_ops_t *en_erxop;
455 efx_filter_t en_filter;
456 const efx_filter_ops_t *en_efop;
457 #endif /* EFSYS_OPT_FILTER */
460 #endif /* EFSYS_OPT_MCDI */
461 uint32_t en_vport_id;
467 #endif /* EFSYS_OPT_SIENA */
470 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
476 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
477 uint32_t ena_piobuf_count;
478 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
479 uint32_t ena_pio_write_vi_base;
480 /* Memory BAR mapping regions */
481 uint32_t ena_uc_mem_map_offset;
482 size_t ena_uc_mem_map_size;
483 uint32_t ena_wc_mem_map_offset;
484 size_t ena_wc_mem_map_size;
487 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
491 #define EFX_NIC_MAGIC 0x02121996
493 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
494 const efx_ev_callbacks_t *, void *);
496 typedef struct efx_evq_rxq_state_s {
497 unsigned int eers_rx_read_ptr;
498 unsigned int eers_rx_mask;
499 } efx_evq_rxq_state_t;
504 unsigned int ee_index;
505 unsigned int ee_mask;
506 efsys_mem_t *ee_esmp;
508 uint32_t ee_stat[EV_NQSTATS];
509 #endif /* EFSYS_OPT_QSTATS */
511 efx_ev_handler_t ee_rx;
512 efx_ev_handler_t ee_tx;
513 efx_ev_handler_t ee_driver;
514 efx_ev_handler_t ee_global;
515 efx_ev_handler_t ee_drv_gen;
517 efx_ev_handler_t ee_mcdi;
518 #endif /* EFSYS_OPT_MCDI */
520 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
525 #define EFX_EVQ_MAGIC 0x08081997
527 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
533 unsigned int er_index;
534 unsigned int er_label;
535 unsigned int er_mask;
536 efsys_mem_t *er_esmp;
539 #define EFX_RXQ_MAGIC 0x15022005
544 unsigned int et_index;
545 unsigned int et_mask;
546 efsys_mem_t *et_esmp;
547 #if EFSYS_OPT_HUNTINGTON
548 uint32_t et_pio_bufnum;
549 uint32_t et_pio_blknum;
550 uint32_t et_pio_write_offset;
551 uint32_t et_pio_offset;
555 uint32_t et_stat[TX_NQSTATS];
556 #endif /* EFSYS_OPT_QSTATS */
559 #define EFX_TXQ_MAGIC 0x05092005
561 #define EFX_MAC_ADDR_COPY(_dst, _src) \
563 (_dst)[0] = (_src)[0]; \
564 (_dst)[1] = (_src)[1]; \
565 (_dst)[2] = (_src)[2]; \
566 (_dst)[3] = (_src)[3]; \
567 (_dst)[4] = (_src)[4]; \
568 (_dst)[5] = (_src)[5]; \
569 _NOTE(CONSTANTCONDITION) \
572 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
574 uint16_t *_d = (uint16_t *)(_dst); \
578 _NOTE(CONSTANTCONDITION) \
581 #if EFSYS_OPT_CHECK_REG
582 #define EFX_CHECK_REG(_enp, _reg) \
584 const char *name = #_reg; \
585 char min = name[4]; \
586 char max = name[5]; \
589 switch ((_enp)->en_family) { \
590 case EFX_FAMILY_SIENA: \
594 case EFX_FAMILY_HUNTINGTON: \
598 case EFX_FAMILY_MEDFORD: \
607 EFSYS_ASSERT3S(rev, >=, min); \
608 EFSYS_ASSERT3S(rev, <=, max); \
610 _NOTE(CONSTANTCONDITION) \
613 #define EFX_CHECK_REG(_enp, _reg) do { \
614 _NOTE(CONSTANTCONDITION) \
618 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
620 EFX_CHECK_REG((_enp), (_reg)); \
621 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
623 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
624 uint32_t, _reg ## _OFST, \
625 uint32_t, (_edp)->ed_u32[0]); \
626 _NOTE(CONSTANTCONDITION) \
629 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
631 EFX_CHECK_REG((_enp), (_reg)); \
632 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
633 uint32_t, _reg ## _OFST, \
634 uint32_t, (_edp)->ed_u32[0]); \
635 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
637 _NOTE(CONSTANTCONDITION) \
640 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
642 EFX_CHECK_REG((_enp), (_reg)); \
643 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
645 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
646 uint32_t, _reg ## _OFST, \
647 uint32_t, (_eqp)->eq_u32[1], \
648 uint32_t, (_eqp)->eq_u32[0]); \
649 _NOTE(CONSTANTCONDITION) \
652 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
654 EFX_CHECK_REG((_enp), (_reg)); \
655 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
656 uint32_t, _reg ## _OFST, \
657 uint32_t, (_eqp)->eq_u32[1], \
658 uint32_t, (_eqp)->eq_u32[0]); \
659 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
661 _NOTE(CONSTANTCONDITION) \
664 #define EFX_BAR_READO(_enp, _reg, _eop) \
666 EFX_CHECK_REG((_enp), (_reg)); \
667 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
669 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
670 uint32_t, _reg ## _OFST, \
671 uint32_t, (_eop)->eo_u32[3], \
672 uint32_t, (_eop)->eo_u32[2], \
673 uint32_t, (_eop)->eo_u32[1], \
674 uint32_t, (_eop)->eo_u32[0]); \
675 _NOTE(CONSTANTCONDITION) \
678 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
680 EFX_CHECK_REG((_enp), (_reg)); \
681 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
682 uint32_t, _reg ## _OFST, \
683 uint32_t, (_eop)->eo_u32[3], \
684 uint32_t, (_eop)->eo_u32[2], \
685 uint32_t, (_eop)->eo_u32[1], \
686 uint32_t, (_eop)->eo_u32[0]); \
687 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
689 _NOTE(CONSTANTCONDITION) \
692 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
694 EFX_CHECK_REG((_enp), (_reg)); \
695 EFSYS_BAR_READD((_enp)->en_esbp, \
696 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
698 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
699 uint32_t, (_index), \
700 uint32_t, _reg ## _OFST, \
701 uint32_t, (_edp)->ed_u32[0]); \
702 _NOTE(CONSTANTCONDITION) \
705 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
707 EFX_CHECK_REG((_enp), (_reg)); \
708 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
709 uint32_t, (_index), \
710 uint32_t, _reg ## _OFST, \
711 uint32_t, (_edp)->ed_u32[0]); \
712 EFSYS_BAR_WRITED((_enp)->en_esbp, \
713 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
715 _NOTE(CONSTANTCONDITION) \
718 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
720 EFX_CHECK_REG((_enp), (_reg)); \
721 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
722 uint32_t, (_index), \
723 uint32_t, _reg ## _OFST, \
724 uint32_t, (_edp)->ed_u32[0]); \
725 EFSYS_BAR_WRITED((_enp)->en_esbp, \
727 (2 * sizeof (efx_dword_t)) + \
728 ((_index) * _reg ## _STEP)), \
730 _NOTE(CONSTANTCONDITION) \
733 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
735 EFX_CHECK_REG((_enp), (_reg)); \
736 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
737 uint32_t, (_index), \
738 uint32_t, _reg ## _OFST, \
739 uint32_t, (_edp)->ed_u32[0]); \
740 EFSYS_BAR_WRITED((_enp)->en_esbp, \
742 (3 * sizeof (efx_dword_t)) + \
743 ((_index) * _reg ## _STEP)), \
745 _NOTE(CONSTANTCONDITION) \
748 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
750 EFX_CHECK_REG((_enp), (_reg)); \
751 EFSYS_BAR_READQ((_enp)->en_esbp, \
752 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
754 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
755 uint32_t, (_index), \
756 uint32_t, _reg ## _OFST, \
757 uint32_t, (_eqp)->eq_u32[1], \
758 uint32_t, (_eqp)->eq_u32[0]); \
759 _NOTE(CONSTANTCONDITION) \
762 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
764 EFX_CHECK_REG((_enp), (_reg)); \
765 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
766 uint32_t, (_index), \
767 uint32_t, _reg ## _OFST, \
768 uint32_t, (_eqp)->eq_u32[1], \
769 uint32_t, (_eqp)->eq_u32[0]); \
770 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
771 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
773 _NOTE(CONSTANTCONDITION) \
776 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
778 EFX_CHECK_REG((_enp), (_reg)); \
779 EFSYS_BAR_READO((_enp)->en_esbp, \
780 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
782 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
783 uint32_t, (_index), \
784 uint32_t, _reg ## _OFST, \
785 uint32_t, (_eop)->eo_u32[3], \
786 uint32_t, (_eop)->eo_u32[2], \
787 uint32_t, (_eop)->eo_u32[1], \
788 uint32_t, (_eop)->eo_u32[0]); \
789 _NOTE(CONSTANTCONDITION) \
792 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
794 EFX_CHECK_REG((_enp), (_reg)); \
795 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
796 uint32_t, (_index), \
797 uint32_t, _reg ## _OFST, \
798 uint32_t, (_eop)->eo_u32[3], \
799 uint32_t, (_eop)->eo_u32[2], \
800 uint32_t, (_eop)->eo_u32[1], \
801 uint32_t, (_eop)->eo_u32[0]); \
802 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
803 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
805 _NOTE(CONSTANTCONDITION) \
809 * Allow drivers to perform optimised 128-bit doorbell writes.
810 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
811 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
812 * the need for locking in the host, and are the only ones known to be safe to
813 * use 128-bites write with.
815 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
817 EFX_CHECK_REG((_enp), (_reg)); \
818 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
821 uint32_t, (_index), \
822 uint32_t, _reg ## _OFST, \
823 uint32_t, (_eop)->eo_u32[3], \
824 uint32_t, (_eop)->eo_u32[2], \
825 uint32_t, (_eop)->eo_u32[1], \
826 uint32_t, (_eop)->eo_u32[0]); \
827 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
828 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
830 _NOTE(CONSTANTCONDITION) \
833 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
835 unsigned int _new = (_wptr); \
836 unsigned int _old = (_owptr); \
838 if ((_new) >= (_old)) \
839 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
840 (_old) * sizeof (efx_desc_t), \
841 ((_new) - (_old)) * sizeof (efx_desc_t)); \
844 * It is cheaper to sync entire map than sync \
845 * two parts especially when offset/size are \
846 * ignored and entire map is synced in any case.\
848 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
850 (_entries) * sizeof (efx_desc_t)); \
851 _NOTE(CONSTANTCONDITION) \
854 extern __checkReturn efx_rc_t
856 __in efx_nic_t *enp);
858 extern __checkReturn efx_rc_t
860 __in efx_nic_t *enp);
863 efx_mac_multicast_hash_compute(
864 __in_ecount(6*count) uint8_t const *addrs,
866 __out efx_oword_t *hash_low,
867 __out efx_oword_t *hash_high);
869 extern __checkReturn efx_rc_t
871 __in efx_nic_t *enp);
875 __in efx_nic_t *enp);
879 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
881 typedef struct efx_register_set_s {
882 unsigned int address;
886 } efx_register_set_t;
888 extern __checkReturn efx_rc_t
889 efx_nic_test_registers(
891 __in efx_register_set_t *rsp,
894 extern __checkReturn efx_rc_t
897 __in efx_register_set_t *rsp,
898 __in efx_pattern_type_t pattern,
901 #endif /* EFSYS_OPT_DIAG */
905 extern __checkReturn efx_rc_t
906 efx_mcdi_set_workaround(
909 __in boolean_t enabled,
910 __out_opt uint32_t *flagsp);
912 extern __checkReturn efx_rc_t
913 efx_mcdi_get_workarounds(
915 __out_opt uint32_t *implementedp,
916 __out_opt uint32_t *enabledp);
918 #endif /* EFSYS_OPT_MCDI */
920 #if EFSYS_OPT_MAC_STATS
923 * Closed range of stats (i.e. the first and the last are included).
924 * The last must be greater or equal (if the range is one item only) to
927 struct efx_mac_stats_range {
928 efx_mac_stat_t first;
933 efx_mac_stats_mask_add_ranges(
934 __inout_bcount(mask_size) uint32_t *maskp,
935 __in size_t mask_size,
936 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
937 __in unsigned int rng_count);
939 #endif /* EFSYS_OPT_MAC_STATS */
945 #endif /* _SYS_EFX_IMPL_H */