drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154 #if EFSYS_OPT_RX_SCALE
 155         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 156                                                efx_rx_hash_type_t, boolean_t);
 157         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 158         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 159                                               size_t);
 160         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 161                                             uint8_t *);
 162 #endif /* EFSYS_OPT_RX_SCALE */
 163         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 164                                               uint16_t *);
 165         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 166                                       unsigned int, unsigned int,
 167                                       unsigned int);
 168         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 169 #if EFSYS_OPT_RX_PACKED_STREAM
 170         void            (*erxo_qps_update_credits)(efx_rxq_t *);
 171         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 172                                                 uint32_t, uint32_t,
 173                                                 uint16_t *, uint32_t *, uint32_t *);
 174 #endif
 175         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 176         void            (*erxo_qenable)(efx_rxq_t *);
 177         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 178                                         unsigned int, efx_rxq_type_t,
 179                                         efsys_mem_t *, size_t, uint32_t,
 180                                         efx_evq_t *, efx_rxq_t *);
 181         void            (*erxo_qdestroy)(efx_rxq_t *);
 182 } efx_rx_ops_t;
 183
 184 typedef struct efx_mac_ops_s {
 185         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 186         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 187         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 188         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 189         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 190         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 191         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 192         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 193                                                       efx_rxq_t *, boolean_t);
 194         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 195 #if EFSYS_OPT_LOOPBACK
 196         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 197                                             efx_loopback_type_t);
 198 #endif  /* EFSYS_OPT_LOOPBACK */
 199 #if EFSYS_OPT_MAC_STATS
 200         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 201         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 202         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 203                                               uint16_t, boolean_t);
 204         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 205                                             efsys_stat_t *, uint32_t *);
 206 #endif  /* EFSYS_OPT_MAC_STATS */
 207 } efx_mac_ops_t;
 208
 209 typedef struct efx_phy_ops_s {
 210         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 211         efx_rc_t        (*epo_reset)(efx_nic_t *);
 212         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 213         efx_rc_t        (*epo_verify)(efx_nic_t *);
 214         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 215 #if EFSYS_OPT_PHY_STATS
 216         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 217                                             uint32_t *);
 218 #endif  /* EFSYS_OPT_PHY_STATS */
 219 #if EFSYS_OPT_BIST
 220         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 221         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 222         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 223                                          efx_bist_result_t *, uint32_t *,
 224                                          unsigned long *, size_t);
 225         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 226 #endif  /* EFSYS_OPT_BIST */
 227 } efx_phy_ops_t;
 228
 229 #if EFSYS_OPT_FILTER
 230 typedef struct efx_filter_ops_s {
 231         efx_rc_t        (*efo_init)(efx_nic_t *);
 232         void            (*efo_fini)(efx_nic_t *);
 233         efx_rc_t        (*efo_restore)(efx_nic_t *);
 234         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 235                                    boolean_t may_replace);
 236         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 237         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 238         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 239                                    boolean_t, boolean_t, boolean_t,
 240                                    uint8_t const *, uint32_t);
 241 } efx_filter_ops_t;
 242
 243 extern  __checkReturn   efx_rc_t
 244 efx_filter_reconfigure(
 245         __in                            efx_nic_t *enp,
 246         __in_ecount(6)                  uint8_t const *mac_addr,
 247         __in                            boolean_t all_unicst,
 248         __in                            boolean_t mulcst,
 249         __in                            boolean_t all_mulcst,
 250         __in                            boolean_t brdcst,
 251         __in_ecount(6*count)            uint8_t const *addrs,
 252         __in                            uint32_t count);
 253
 254 #endif /* EFSYS_OPT_FILTER */
 255
 256
 257 typedef struct efx_port_s {
 258         efx_mac_type_t          ep_mac_type;
 259         uint32_t                ep_phy_type;
 260         uint8_t                 ep_port;
 261         uint32_t                ep_mac_pdu;
 262         uint8_t                 ep_mac_addr[6];
 263         efx_link_mode_t         ep_link_mode;
 264         boolean_t               ep_all_unicst;
 265         boolean_t               ep_mulcst;
 266         boolean_t               ep_all_mulcst;
 267         boolean_t               ep_brdcst;
 268         unsigned int            ep_fcntl;
 269         boolean_t               ep_fcntl_autoneg;
 270         efx_oword_t             ep_multicst_hash[2];
 271         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 272                                                     EFX_MAC_MULTICAST_LIST_MAX];
 273         uint32_t                ep_mulcst_addr_count;
 274 #if EFSYS_OPT_LOOPBACK
 275         efx_loopback_type_t     ep_loopback_type;
 276         efx_link_mode_t         ep_loopback_link_mode;
 277 #endif  /* EFSYS_OPT_LOOPBACK */
 278 #if EFSYS_OPT_PHY_FLAGS
 279         uint32_t                ep_phy_flags;
 280 #endif  /* EFSYS_OPT_PHY_FLAGS */
 281 #if EFSYS_OPT_PHY_LED_CONTROL
 282         efx_phy_led_mode_t      ep_phy_led_mode;
 283 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 284         efx_phy_media_type_t    ep_fixed_port_type;
 285         efx_phy_media_type_t    ep_module_type;
 286         uint32_t                ep_adv_cap_mask;
 287         uint32_t                ep_lp_cap_mask;
 288         uint32_t                ep_default_adv_cap_mask;
 289         uint32_t                ep_phy_cap_mask;
 290         boolean_t               ep_mac_drain;
 291         boolean_t               ep_mac_stats_pending;
 292 #if EFSYS_OPT_BIST
 293         efx_bist_type_t         ep_current_bist;
 294 #endif
 295         const efx_mac_ops_t     *ep_emop;
 296         const efx_phy_ops_t     *ep_epop;
 297 } efx_port_t;
 298
 299 typedef struct efx_mon_ops_s {
 300 #if EFSYS_OPT_MON_STATS
 301         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 302                                             efx_mon_stat_value_t *);
 303 #endif  /* EFSYS_OPT_MON_STATS */
 304 } efx_mon_ops_t;
 305
 306 typedef struct efx_mon_s {
 307         efx_mon_type_t          em_type;
 308         const efx_mon_ops_t     *em_emop;
 309 } efx_mon_t;
 310
 311 typedef struct efx_intr_ops_s {
 312         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 313         void            (*eio_enable)(efx_nic_t *);
 314         void            (*eio_disable)(efx_nic_t *);
 315         void            (*eio_disable_unlocked)(efx_nic_t *);
 316         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 317         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 318         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 319                                  boolean_t *);
 320         void            (*eio_fatal)(efx_nic_t *);
 321         void            (*eio_fini)(efx_nic_t *);
 322 } efx_intr_ops_t;
 323
 324 typedef struct efx_intr_s {
 325         const efx_intr_ops_t    *ei_eiop;
 326         efsys_mem_t             *ei_esmp;
 327         efx_intr_type_t         ei_type;
 328         unsigned int            ei_level;
 329 } efx_intr_t;
 330
 331 typedef struct efx_nic_ops_s {
 332         efx_rc_t        (*eno_probe)(efx_nic_t *);
 333         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 334         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 335         efx_rc_t        (*eno_reset)(efx_nic_t *);
 336         efx_rc_t        (*eno_init)(efx_nic_t *);
 337         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 338         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 339                                         uint32_t *, size_t *);
 340 #if EFSYS_OPT_DIAG
 341         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 342 #endif  /* EFSYS_OPT_DIAG */
 343         void            (*eno_fini)(efx_nic_t *);
 344         void            (*eno_unprobe)(efx_nic_t *);
 345 } efx_nic_ops_t;
 346
 347 #ifndef EFX_TXQ_LIMIT_TARGET
 348 #define EFX_TXQ_LIMIT_TARGET 259
 349 #endif
 350 #ifndef EFX_RXQ_LIMIT_TARGET
 351 #define EFX_RXQ_LIMIT_TARGET 512
 352 #endif
 353 #ifndef EFX_TXQ_DC_SIZE
 354 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 355 #endif
 356 #ifndef EFX_RXQ_DC_SIZE
 357 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 358 #endif
 359
 360 #if EFSYS_OPT_FILTER
 361
 362 #if EFSYS_OPT_SIENA
 363
 364 typedef struct siena_filter_spec_s {
 365         uint8_t         sfs_type;
 366         uint32_t        sfs_flags;
 367         uint32_t        sfs_dmaq_id;
 368         uint32_t        sfs_dword[3];
 369 } siena_filter_spec_t;
 370
 371 typedef enum siena_filter_type_e {
 372         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 373         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 374         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 375         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 376         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 377         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 378
 379         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 380         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 381         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 382         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 383         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 384         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 385
 386         EFX_SIENA_FILTER_NTYPES
 387 } siena_filter_type_t;
 388
 389 typedef enum siena_filter_tbl_id_e {
 390         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 391         EFX_SIENA_FILTER_TBL_RX_MAC,
 392         EFX_SIENA_FILTER_TBL_TX_IP,
 393         EFX_SIENA_FILTER_TBL_TX_MAC,
 394         EFX_SIENA_FILTER_NTBLS
 395 } siena_filter_tbl_id_t;
 396
 397 typedef struct siena_filter_tbl_s {
 398         int                     sft_size;       /* number of entries */
 399         int                     sft_used;       /* active count */
 400         uint32_t                *sft_bitmap;    /* active bitmap */
 401         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 402 } siena_filter_tbl_t;
 403
 404 typedef struct siena_filter_s {
 405         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 406         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 407 } siena_filter_t;
 408
 409 #endif  /* EFSYS_OPT_SIENA */
 410
 411 typedef struct efx_filter_s {
 412 #if EFSYS_OPT_SIENA
 413         siena_filter_t          *ef_siena_filter;
 414 #endif /* EFSYS_OPT_SIENA */
 415 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 416         ef10_filter_table_t     *ef_ef10_filter_table;
 417 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 418 } efx_filter_t;
 419
 420 #if EFSYS_OPT_SIENA
 421
 422 extern                  void
 423 siena_filter_tbl_clear(
 424         __in            efx_nic_t *enp,
 425         __in            siena_filter_tbl_id_t tbl);
 426
 427 #endif  /* EFSYS_OPT_SIENA */
 428
 429 #endif  /* EFSYS_OPT_FILTER */
 430
 431 #if EFSYS_OPT_MCDI
 432
 433 typedef struct efx_mcdi_ops_s {
 434         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 435         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 436                                         void *, size_t);
 437         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 438         boolean_t       (*emco_poll_response)(efx_nic_t *);
 439         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 440         void            (*emco_fini)(efx_nic_t *);
 441         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 442                                             efx_mcdi_feature_id_t, boolean_t *);
 443         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 444                                             uint32_t *);
 445 } efx_mcdi_ops_t;
 446
 447 typedef struct efx_mcdi_s {
 448         const efx_mcdi_ops_t            *em_emcop;
 449         const efx_mcdi_transport_t      *em_emtp;
 450         efx_mcdi_iface_t                em_emip;
 451 } efx_mcdi_t;
 452
 453 #endif /* EFSYS_OPT_MCDI */
 454
 455 #if EFSYS_OPT_NVRAM
 456 typedef struct efx_nvram_ops_s {
 457 #if EFSYS_OPT_DIAG
 458         efx_rc_t        (*envo_test)(efx_nic_t *);
 459 #endif  /* EFSYS_OPT_DIAG */
 460         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 461                                             uint32_t *);
 462         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 463         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 464         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 465                                             unsigned int, caddr_t, size_t);
 466         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 467                                             unsigned int, size_t);
 468         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 469                                             unsigned int, caddr_t, size_t);
 470         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 471         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 472                                             uint32_t *, uint16_t *);
 473         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 474                                             uint16_t *);
 475         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 476                                             caddr_t, size_t);
 477 } efx_nvram_ops_t;
 478 #endif /* EFSYS_OPT_NVRAM */
 479
 480 #if EFSYS_OPT_VPD
 481 typedef struct efx_vpd_ops_s {
 482         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 483         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 484         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 485         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 486         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 487         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 488                                         efx_vpd_value_t *);
 489         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 490                                         efx_vpd_value_t *);
 491         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 492                                         efx_vpd_value_t *, unsigned int *);
 493         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 494         void            (*evpdo_fini)(efx_nic_t *);
 495 } efx_vpd_ops_t;
 496 #endif  /* EFSYS_OPT_VPD */
 497
 498 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 499
 500         __checkReturn           efx_rc_t
 501 efx_mcdi_nvram_partitions(
 502         __in                    efx_nic_t *enp,
 503         __out_bcount(size)      caddr_t data,
 504         __in                    size_t size,
 505         __out                   unsigned int *npartnp);
 506
 507         __checkReturn           efx_rc_t
 508 efx_mcdi_nvram_metadata(
 509         __in                    efx_nic_t *enp,
 510         __in                    uint32_t partn,
 511         __out                   uint32_t *subtypep,
 512         __out_ecount(4)         uint16_t version[4],
 513         __out_bcount_opt(size)  char *descp,
 514         __in                    size_t size);
 515
 516         __checkReturn           efx_rc_t
 517 efx_mcdi_nvram_info(
 518         __in                    efx_nic_t *enp,
 519         __in                    uint32_t partn,
 520         __out_opt               size_t *sizep,
 521         __out_opt               uint32_t *addressp,
 522         __out_opt               uint32_t *erase_sizep,
 523         __out_opt               uint32_t *write_sizep);
 524
 525         __checkReturn           efx_rc_t
 526 efx_mcdi_nvram_update_start(
 527         __in                    efx_nic_t *enp,
 528         __in                    uint32_t partn);
 529
 530         __checkReturn           efx_rc_t
 531 efx_mcdi_nvram_read(
 532         __in                    efx_nic_t *enp,
 533         __in                    uint32_t partn,
 534         __in                    uint32_t offset,
 535         __out_bcount(size)      caddr_t data,
 536         __in                    size_t size,
 537         __in                    uint32_t mode);
 538
 539         __checkReturn           efx_rc_t
 540 efx_mcdi_nvram_erase(
 541         __in                    efx_nic_t *enp,
 542         __in                    uint32_t partn,
 543         __in                    uint32_t offset,
 544         __in                    size_t size);
 545
 546         __checkReturn           efx_rc_t
 547 efx_mcdi_nvram_write(
 548         __in                    efx_nic_t *enp,
 549         __in                    uint32_t partn,
 550         __in                    uint32_t offset,
 551         __out_bcount(size)      caddr_t data,
 552         __in                    size_t size);
 553
 554         __checkReturn           efx_rc_t
 555 efx_mcdi_nvram_update_finish(
 556         __in                    efx_nic_t *enp,
 557         __in                    uint32_t partn,
 558         __in                    boolean_t reboot,
 559         __out_opt               uint32_t *resultp);
 560
 561 #if EFSYS_OPT_DIAG
 562
 563         __checkReturn           efx_rc_t
 564 efx_mcdi_nvram_test(
 565         __in                    efx_nic_t *enp,
 566         __in                    uint32_t partn);
 567
 568 #endif  /* EFSYS_OPT_DIAG */
 569
 570 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 571
 572 typedef struct efx_drv_cfg_s {
 573         uint32_t                edc_min_vi_count;
 574         uint32_t                edc_max_vi_count;
 575
 576         uint32_t                edc_max_piobuf_count;
 577         uint32_t                edc_pio_alloc_size;
 578 } efx_drv_cfg_t;
 579
 580 struct efx_nic_s {
 581         uint32_t                en_magic;
 582         efx_family_t            en_family;
 583         uint32_t                en_features;
 584         efsys_identifier_t      *en_esip;
 585         efsys_lock_t            *en_eslp;
 586         efsys_bar_t             *en_esbp;
 587         unsigned int            en_mod_flags;
 588         unsigned int            en_reset_flags;
 589         efx_nic_cfg_t           en_nic_cfg;
 590         efx_drv_cfg_t           en_drv_cfg;
 591         efx_port_t              en_port;
 592         efx_mon_t               en_mon;
 593         efx_intr_t              en_intr;
 594         uint32_t                en_ev_qcount;
 595         uint32_t                en_rx_qcount;
 596         uint32_t                en_tx_qcount;
 597         const efx_nic_ops_t     *en_enop;
 598         const efx_ev_ops_t      *en_eevop;
 599         const efx_tx_ops_t      *en_etxop;
 600         const efx_rx_ops_t      *en_erxop;
 601 #if EFSYS_OPT_FILTER
 602         efx_filter_t            en_filter;
 603         const efx_filter_ops_t  *en_efop;
 604 #endif  /* EFSYS_OPT_FILTER */
 605 #if EFSYS_OPT_MCDI
 606         efx_mcdi_t              en_mcdi;
 607 #endif  /* EFSYS_OPT_MCDI */
 608 #if EFSYS_OPT_NVRAM
 609         efx_nvram_type_t        en_nvram_locked;
 610         const efx_nvram_ops_t   *en_envop;
 611 #endif  /* EFSYS_OPT_NVRAM */
 612 #if EFSYS_OPT_VPD
 613         const efx_vpd_ops_t     *en_evpdop;
 614 #endif  /* EFSYS_OPT_VPD */
 615 #if EFSYS_OPT_RX_SCALE
 616         efx_rx_hash_support_t   en_hash_support;
 617         efx_rx_scale_support_t  en_rss_support;
 618         uint32_t                en_rss_context;
 619 #endif  /* EFSYS_OPT_RX_SCALE */
 620         uint32_t                en_vport_id;
 621         union {
 622 #if EFSYS_OPT_SIENA
 623                 struct {
 624 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 625                         unsigned int            enu_partn_mask;
 626 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 627 #if EFSYS_OPT_VPD
 628                         caddr_t                 enu_svpd;
 629                         size_t                  enu_svpd_length;
 630 #endif  /* EFSYS_OPT_VPD */
 631                         int                     enu_unused;
 632                 } siena;
 633 #endif  /* EFSYS_OPT_SIENA */
 634                 int     enu_unused;
 635         } en_u;
 636 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 637         union en_arch {
 638                 struct {
 639                         int                     ena_vi_base;
 640                         int                     ena_vi_count;
 641                         int                     ena_vi_shift;
 642 #if EFSYS_OPT_VPD
 643                         caddr_t                 ena_svpd;
 644                         size_t                  ena_svpd_length;
 645 #endif  /* EFSYS_OPT_VPD */
 646                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 647                         uint32_t                ena_piobuf_count;
 648                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 649                         uint32_t                ena_pio_write_vi_base;
 650                         /* Memory BAR mapping regions */
 651                         uint32_t                ena_uc_mem_map_offset;
 652                         size_t                  ena_uc_mem_map_size;
 653                         uint32_t                ena_wc_mem_map_offset;
 654                         size_t                  ena_wc_mem_map_size;
 655                 } ef10;
 656         } en_arch;
 657 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 658 };
 659
 660
 661 #define EFX_NIC_MAGIC   0x02121996
 662
 663 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 664     const efx_ev_callbacks_t *, void *);
 665
 666 typedef struct efx_evq_rxq_state_s {
 667         unsigned int                    eers_rx_read_ptr;
 668         unsigned int                    eers_rx_mask;
 669 #if EFSYS_OPT_RX_PACKED_STREAM
 670         unsigned int                    eers_rx_stream_npackets;
 671         boolean_t                       eers_rx_packed_stream;
 672         unsigned int                    eers_rx_packed_stream_credits;
 673 #endif
 674 } efx_evq_rxq_state_t;
 675
 676 struct efx_evq_s {
 677         uint32_t                        ee_magic;
 678         efx_nic_t                       *ee_enp;
 679         unsigned int                    ee_index;
 680         unsigned int                    ee_mask;
 681         efsys_mem_t                     *ee_esmp;
 682 #if EFSYS_OPT_QSTATS
 683         uint32_t                        ee_stat[EV_NQSTATS];
 684 #endif  /* EFSYS_OPT_QSTATS */
 685
 686         efx_ev_handler_t                ee_rx;
 687         efx_ev_handler_t                ee_tx;
 688         efx_ev_handler_t                ee_driver;
 689         efx_ev_handler_t                ee_global;
 690         efx_ev_handler_t                ee_drv_gen;
 691 #if EFSYS_OPT_MCDI
 692         efx_ev_handler_t                ee_mcdi;
 693 #endif  /* EFSYS_OPT_MCDI */
 694
 695         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 696
 697         uint32_t                        ee_flags;
 698 };
 699
 700 #define EFX_EVQ_MAGIC   0x08081997
 701
 702 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 703
 704 struct efx_rxq_s {
 705         uint32_t                        er_magic;
 706         efx_nic_t                       *er_enp;
 707         efx_evq_t                       *er_eep;
 708         unsigned int                    er_index;
 709         unsigned int                    er_label;
 710         unsigned int                    er_mask;
 711         efsys_mem_t                     *er_esmp;
 712 };
 713
 714 #define EFX_RXQ_MAGIC   0x15022005
 715
 716 struct efx_txq_s {
 717         uint32_t                        et_magic;
 718         efx_nic_t                       *et_enp;
 719         unsigned int                    et_index;
 720         unsigned int                    et_mask;
 721         efsys_mem_t                     *et_esmp;
 722 #if EFSYS_OPT_HUNTINGTON
 723         uint32_t                        et_pio_bufnum;
 724         uint32_t                        et_pio_blknum;
 725         uint32_t                        et_pio_write_offset;
 726         uint32_t                        et_pio_offset;
 727         size_t                          et_pio_size;
 728 #endif
 729 #if EFSYS_OPT_QSTATS
 730         uint32_t                        et_stat[TX_NQSTATS];
 731 #endif  /* EFSYS_OPT_QSTATS */
 732 };
 733
 734 #define EFX_TXQ_MAGIC   0x05092005
 735
 736 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 737         do {                                                            \
 738                 (_dst)[0] = (_src)[0];                                  \
 739                 (_dst)[1] = (_src)[1];                                  \
 740                 (_dst)[2] = (_src)[2];                                  \
 741                 (_dst)[3] = (_src)[3];                                  \
 742                 (_dst)[4] = (_src)[4];                                  \
 743                 (_dst)[5] = (_src)[5];                                  \
 744         _NOTE(CONSTANTCONDITION)                                        \
 745         } while (B_FALSE)
 746
 747 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 748         do {                                                            \
 749                 uint16_t *_d = (uint16_t *)(_dst);                      \
 750                 _d[0] = 0xffff;                                         \
 751                 _d[1] = 0xffff;                                         \
 752                 _d[2] = 0xffff;                                         \
 753         _NOTE(CONSTANTCONDITION)                                        \
 754         } while (B_FALSE)
 755
 756 #if EFSYS_OPT_CHECK_REG
 757 #define EFX_CHECK_REG(_enp, _reg)                                       \
 758         do {                                                            \
 759                 const char *name = #_reg;                               \
 760                 char min = name[4];                                     \
 761                 char max = name[5];                                     \
 762                 char rev;                                               \
 763                                                                         \
 764                 switch ((_enp)->en_family) {                            \
 765                 case EFX_FAMILY_SIENA:                                  \
 766                         rev = 'C';                                      \
 767                         break;                                          \
 768                                                                         \
 769                 case EFX_FAMILY_HUNTINGTON:                             \
 770                         rev = 'D';                                      \
 771                         break;                                          \
 772                                                                         \
 773                 case EFX_FAMILY_MEDFORD:                                \
 774                         rev = 'E';                                      \
 775                         break;                                          \
 776                                                                         \
 777                 default:                                                \
 778                         rev = '?';                                      \
 779                         break;                                          \
 780                 }                                                       \
 781                                                                         \
 782                 EFSYS_ASSERT3S(rev, >=, min);                           \
 783                 EFSYS_ASSERT3S(rev, <=, max);                           \
 784                                                                         \
 785         _NOTE(CONSTANTCONDITION)                                        \
 786         } while (B_FALSE)
 787 #else
 788 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 789         _NOTE(CONSTANTCONDITION)                                        \
 790         } while (B_FALSE)
 791 #endif
 792
 793 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 794         do {                                                            \
 795                 EFX_CHECK_REG((_enp), (_reg));                          \
 796                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 797                     (_edp), (_lock));                                   \
 798                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 799                     uint32_t, _reg ## _OFST,                            \
 800                     uint32_t, (_edp)->ed_u32[0]);                       \
 801         _NOTE(CONSTANTCONDITION)                                        \
 802         } while (B_FALSE)
 803
 804 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 805         do {                                                            \
 806                 EFX_CHECK_REG((_enp), (_reg));                          \
 807                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 808                     uint32_t, _reg ## _OFST,                            \
 809                     uint32_t, (_edp)->ed_u32[0]);                       \
 810                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 811                     (_edp), (_lock));                                   \
 812         _NOTE(CONSTANTCONDITION)                                        \
 813         } while (B_FALSE)
 814
 815 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 816         do {                                                            \
 817                 EFX_CHECK_REG((_enp), (_reg));                          \
 818                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 819                     (_eqp));                                            \
 820                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 821                     uint32_t, _reg ## _OFST,                            \
 822                     uint32_t, (_eqp)->eq_u32[1],                        \
 823                     uint32_t, (_eqp)->eq_u32[0]);                       \
 824         _NOTE(CONSTANTCONDITION)                                        \
 825         } while (B_FALSE)
 826
 827 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 828         do {                                                            \
 829                 EFX_CHECK_REG((_enp), (_reg));                          \
 830                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 831                     uint32_t, _reg ## _OFST,                            \
 832                     uint32_t, (_eqp)->eq_u32[1],                        \
 833                     uint32_t, (_eqp)->eq_u32[0]);                       \
 834                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 835                     (_eqp));                                            \
 836         _NOTE(CONSTANTCONDITION)                                        \
 837         } while (B_FALSE)
 838
 839 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 840         do {                                                            \
 841                 EFX_CHECK_REG((_enp), (_reg));                          \
 842                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 843                     (_eop), B_TRUE);                                    \
 844                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 845                     uint32_t, _reg ## _OFST,                            \
 846                     uint32_t, (_eop)->eo_u32[3],                        \
 847                     uint32_t, (_eop)->eo_u32[2],                        \
 848                     uint32_t, (_eop)->eo_u32[1],                        \
 849                     uint32_t, (_eop)->eo_u32[0]);                       \
 850         _NOTE(CONSTANTCONDITION)                                        \
 851         } while (B_FALSE)
 852
 853 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 854         do {                                                            \
 855                 EFX_CHECK_REG((_enp), (_reg));                          \
 856                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 857                     uint32_t, _reg ## _OFST,                            \
 858                     uint32_t, (_eop)->eo_u32[3],                        \
 859                     uint32_t, (_eop)->eo_u32[2],                        \
 860                     uint32_t, (_eop)->eo_u32[1],                        \
 861                     uint32_t, (_eop)->eo_u32[0]);                       \
 862                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 863                     (_eop), B_TRUE);                                    \
 864         _NOTE(CONSTANTCONDITION)                                        \
 865         } while (B_FALSE)
 866
 867 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 868         do {                                                            \
 869                 EFX_CHECK_REG((_enp), (_reg));                          \
 870                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 871                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 872                     (_edp), (_lock));                                   \
 873                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 874                     uint32_t, (_index),                                 \
 875                     uint32_t, _reg ## _OFST,                            \
 876                     uint32_t, (_edp)->ed_u32[0]);                       \
 877         _NOTE(CONSTANTCONDITION)                                        \
 878         } while (B_FALSE)
 879
 880 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 881         do {                                                            \
 882                 EFX_CHECK_REG((_enp), (_reg));                          \
 883                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 884                     uint32_t, (_index),                                 \
 885                     uint32_t, _reg ## _OFST,                            \
 886                     uint32_t, (_edp)->ed_u32[0]);                       \
 887                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 888                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 889                     (_edp), (_lock));                                   \
 890         _NOTE(CONSTANTCONDITION)                                        \
 891         } while (B_FALSE)
 892
 893 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 894         do {                                                            \
 895                 EFX_CHECK_REG((_enp), (_reg));                          \
 896                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 897                     uint32_t, (_index),                                 \
 898                     uint32_t, _reg ## _OFST,                            \
 899                     uint32_t, (_edp)->ed_u32[0]);                       \
 900                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 901                     (_reg ## _OFST +                                    \
 902                     (2 * sizeof (efx_dword_t)) +                        \
 903                     ((_index) * _reg ## _STEP)),                        \
 904                     (_edp), (_lock));                                   \
 905         _NOTE(CONSTANTCONDITION)                                        \
 906         } while (B_FALSE)
 907
 908 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 909         do {                                                            \
 910                 EFX_CHECK_REG((_enp), (_reg));                          \
 911                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 912                     uint32_t, (_index),                                 \
 913                     uint32_t, _reg ## _OFST,                            \
 914                     uint32_t, (_edp)->ed_u32[0]);                       \
 915                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 916                     (_reg ## _OFST +                                    \
 917                     (3 * sizeof (efx_dword_t)) +                        \
 918                     ((_index) * _reg ## _STEP)),                        \
 919                     (_edp), (_lock));                                   \
 920         _NOTE(CONSTANTCONDITION)                                        \
 921         } while (B_FALSE)
 922
 923 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 924         do {                                                            \
 925                 EFX_CHECK_REG((_enp), (_reg));                          \
 926                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 927                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 928                     (_eqp));                                            \
 929                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 930                     uint32_t, (_index),                                 \
 931                     uint32_t, _reg ## _OFST,                            \
 932                     uint32_t, (_eqp)->eq_u32[1],                        \
 933                     uint32_t, (_eqp)->eq_u32[0]);                       \
 934         _NOTE(CONSTANTCONDITION)                                        \
 935         } while (B_FALSE)
 936
 937 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 938         do {                                                            \
 939                 EFX_CHECK_REG((_enp), (_reg));                          \
 940                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 941                     uint32_t, (_index),                                 \
 942                     uint32_t, _reg ## _OFST,                            \
 943                     uint32_t, (_eqp)->eq_u32[1],                        \
 944                     uint32_t, (_eqp)->eq_u32[0]);                       \
 945                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 946                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 947                     (_eqp));                                            \
 948         _NOTE(CONSTANTCONDITION)                                        \
 949         } while (B_FALSE)
 950
 951 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 952         do {                                                            \
 953                 EFX_CHECK_REG((_enp), (_reg));                          \
 954                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 955                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 956                     (_eop), (_lock));                                   \
 957                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 958                     uint32_t, (_index),                                 \
 959                     uint32_t, _reg ## _OFST,                            \
 960                     uint32_t, (_eop)->eo_u32[3],                        \
 961                     uint32_t, (_eop)->eo_u32[2],                        \
 962                     uint32_t, (_eop)->eo_u32[1],                        \
 963                     uint32_t, (_eop)->eo_u32[0]);                       \
 964         _NOTE(CONSTANTCONDITION)                                        \
 965         } while (B_FALSE)
 966
 967 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 968         do {                                                            \
 969                 EFX_CHECK_REG((_enp), (_reg));                          \
 970                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 971                     uint32_t, (_index),                                 \
 972                     uint32_t, _reg ## _OFST,                            \
 973                     uint32_t, (_eop)->eo_u32[3],                        \
 974                     uint32_t, (_eop)->eo_u32[2],                        \
 975                     uint32_t, (_eop)->eo_u32[1],                        \
 976                     uint32_t, (_eop)->eo_u32[0]);                       \
 977                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 978                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 979                     (_eop), (_lock));                                   \
 980         _NOTE(CONSTANTCONDITION)                                        \
 981         } while (B_FALSE)
 982
 983 /*
 984  * Allow drivers to perform optimised 128-bit doorbell writes.
 985  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 986  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 987  * the need for locking in the host, and are the only ones known to be safe to
 988  * use 128-bites write with.
 989  */
 990 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 991         do {                                                            \
 992                 EFX_CHECK_REG((_enp), (_reg));                          \
 993                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 994                     const char *,                                       \
 995                     #_reg,                                              \
 996                     uint32_t, (_index),                                 \
 997                     uint32_t, _reg ## _OFST,                            \
 998                     uint32_t, (_eop)->eo_u32[3],                        \
 999                     uint32_t, (_eop)->eo_u32[2],                        \
1000                     uint32_t, (_eop)->eo_u32[1],                        \
1001                     uint32_t, (_eop)->eo_u32[0]);                       \
1002                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1003                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1004                     (_eop));                                            \
1005         _NOTE(CONSTANTCONDITION)                                        \
1006         } while (B_FALSE)
1007
1008 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1009         do {                                                            \
1010                 unsigned int _new = (_wptr);                            \
1011                 unsigned int _old = (_owptr);                           \
1012                                                                         \
1013                 if ((_new) >= (_old))                                   \
1014                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1015                             (_old) * sizeof (efx_desc_t),               \
1016                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1017                 else                                                    \
1018                         /*                                              \
1019                          * It is cheaper to sync entire map than sync   \
1020                          * two parts especially when offset/size are    \
1021                          * ignored and entire map is synced in any case.\
1022                          */                                             \
1023                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1024                             0,                                          \
1025                             (_entries) * sizeof (efx_desc_t));          \
1026         _NOTE(CONSTANTCONDITION)                                        \
1027         } while (B_FALSE)
1028
1029 extern  __checkReturn   efx_rc_t
1030 efx_nic_biu_test(
1031         __in            efx_nic_t *enp);
1032
1033 extern  __checkReturn   efx_rc_t
1034 efx_mac_select(
1035         __in            efx_nic_t *enp);
1036
1037 extern  void
1038 efx_mac_multicast_hash_compute(
1039         __in_ecount(6*count)            uint8_t const *addrs,
1040         __in                            int count,
1041         __out                           efx_oword_t *hash_low,
1042         __out                           efx_oword_t *hash_high);
1043
1044 extern  __checkReturn   efx_rc_t
1045 efx_phy_probe(
1046         __in            efx_nic_t *enp);
1047
1048 extern                  void
1049 efx_phy_unprobe(
1050         __in            efx_nic_t *enp);
1051
1052 #if EFSYS_OPT_VPD
1053
1054 /* VPD utility functions */
1055
1056 extern  __checkReturn           efx_rc_t
1057 efx_vpd_hunk_length(
1058         __in_bcount(size)       caddr_t data,
1059         __in                    size_t size,
1060         __out                   size_t *lengthp);
1061
1062 extern  __checkReturn           efx_rc_t
1063 efx_vpd_hunk_verify(
1064         __in_bcount(size)       caddr_t data,
1065         __in                    size_t size,
1066         __out_opt               boolean_t *cksummedp);
1067
1068 extern  __checkReturn           efx_rc_t
1069 efx_vpd_hunk_reinit(
1070         __in_bcount(size)       caddr_t data,
1071         __in                    size_t size,
1072         __in                    boolean_t wantpid);
1073
1074 extern  __checkReturn           efx_rc_t
1075 efx_vpd_hunk_get(
1076         __in_bcount(size)       caddr_t data,
1077         __in                    size_t size,
1078         __in                    efx_vpd_tag_t tag,
1079         __in                    efx_vpd_keyword_t keyword,
1080         __out                   unsigned int *payloadp,
1081         __out                   uint8_t *paylenp);
1082
1083 extern  __checkReturn                   efx_rc_t
1084 efx_vpd_hunk_next(
1085         __in_bcount(size)               caddr_t data,
1086         __in                            size_t size,
1087         __out                           efx_vpd_tag_t *tagp,
1088         __out                           efx_vpd_keyword_t *keyword,
1089         __out_opt                       unsigned int *payloadp,
1090         __out_opt                       uint8_t *paylenp,
1091         __inout                         unsigned int *contp);
1092
1093 extern  __checkReturn           efx_rc_t
1094 efx_vpd_hunk_set(
1095         __in_bcount(size)       caddr_t data,
1096         __in                    size_t size,
1097         __in                    efx_vpd_value_t *evvp);
1098
1099 #endif  /* EFSYS_OPT_VPD */
1100
1101 #if EFSYS_OPT_DIAG
1102
1103 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1104
1105 typedef struct efx_register_set_s {
1106         unsigned int            address;
1107         unsigned int            step;
1108         unsigned int            rows;
1109         efx_oword_t             mask;
1110 } efx_register_set_t;
1111
1112 extern  __checkReturn   efx_rc_t
1113 efx_nic_test_registers(
1114         __in            efx_nic_t *enp,
1115         __in            efx_register_set_t *rsp,
1116         __in            size_t count);
1117
1118 extern  __checkReturn   efx_rc_t
1119 efx_nic_test_tables(
1120         __in            efx_nic_t *enp,
1121         __in            efx_register_set_t *rsp,
1122         __in            efx_pattern_type_t pattern,
1123         __in            size_t count);
1124
1125 #endif  /* EFSYS_OPT_DIAG */
1126
1127 #if EFSYS_OPT_MCDI
1128
1129 extern  __checkReturn           efx_rc_t
1130 efx_mcdi_set_workaround(
1131         __in                    efx_nic_t *enp,
1132         __in                    uint32_t type,
1133         __in                    boolean_t enabled,
1134         __out_opt               uint32_t *flagsp);
1135
1136 extern  __checkReturn           efx_rc_t
1137 efx_mcdi_get_workarounds(
1138         __in                    efx_nic_t *enp,
1139         __out_opt               uint32_t *implementedp,
1140         __out_opt               uint32_t *enabledp);
1141
1142 #endif /* EFSYS_OPT_MCDI */
1143
1144 #if EFSYS_OPT_MAC_STATS
1145
1146 /*
1147  * Closed range of stats (i.e. the first and the last are included).
1148  * The last must be greater or equal (if the range is one item only) to
1149  * the first.
1150  */
1151 struct efx_mac_stats_range {
1152         efx_mac_stat_t          first;
1153         efx_mac_stat_t          last;
1154 };
1155
1156 extern                                  efx_rc_t
1157 efx_mac_stats_mask_add_ranges(
1158         __inout_bcount(mask_size)       uint32_t *maskp,
1159         __in                            size_t mask_size,
1160         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1161         __in                            unsigned int rng_count);
1162
1163 #endif  /* EFSYS_OPT_MAC_STATS */
1164
1165 #ifdef  __cplusplus
1166 }
1167 #endif
1168
1169 #endif  /* _SYS_EFX_IMPL_H */