2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_FILTER 0x00001000
76 #define EFX_MOD_LIC 0x00002000
78 #define EFX_RESET_PHY 0x00000001
79 #define EFX_RESET_RXQ_ERR 0x00000002
80 #define EFX_RESET_TXQ_ERR 0x00000004
82 typedef enum efx_mac_type_e {
90 typedef struct efx_ev_ops_s {
91 efx_rc_t (*eevo_init)(efx_nic_t *);
92 void (*eevo_fini)(efx_nic_t *);
93 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
94 efsys_mem_t *, size_t, uint32_t,
95 uint32_t, uint32_t, efx_evq_t *);
96 void (*eevo_qdestroy)(efx_evq_t *);
97 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
98 void (*eevo_qpost)(efx_evq_t *, uint16_t);
99 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
101 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
105 typedef struct efx_tx_ops_s {
106 efx_rc_t (*etxo_init)(efx_nic_t *);
107 void (*etxo_fini)(efx_nic_t *);
108 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
109 unsigned int, unsigned int,
110 efsys_mem_t *, size_t,
112 efx_evq_t *, efx_txq_t *,
114 void (*etxo_qdestroy)(efx_txq_t *);
115 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
116 unsigned int, unsigned int,
118 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
119 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
120 efx_rc_t (*etxo_qflush)(efx_txq_t *);
121 void (*etxo_qenable)(efx_txq_t *);
122 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
123 void (*etxo_qpio_disable)(efx_txq_t *);
124 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
126 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
128 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
129 unsigned int, unsigned int,
131 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143 void (*etxo_qstats_update)(efx_txq_t *,
148 typedef struct efx_rx_ops_s {
149 efx_rc_t (*erxo_init)(efx_nic_t *);
150 void (*erxo_fini)(efx_nic_t *);
151 #if EFSYS_OPT_RX_SCATTER
152 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
154 #if EFSYS_OPT_RX_SCALE
155 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
156 efx_rx_hash_type_t, boolean_t);
157 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
158 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
160 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
162 #endif /* EFSYS_OPT_RX_SCALE */
163 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
165 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
166 unsigned int, unsigned int,
168 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
169 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
170 void (*erxo_qenable)(efx_rxq_t *);
171 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
172 unsigned int, efx_rxq_type_t,
173 efsys_mem_t *, size_t, uint32_t,
174 efx_evq_t *, efx_rxq_t *);
175 void (*erxo_qdestroy)(efx_rxq_t *);
178 typedef struct efx_mac_ops_s {
179 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
180 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
181 efx_rc_t (*emo_addr_set)(efx_nic_t *);
182 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
183 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
184 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
185 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
186 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
187 efx_rxq_t *, boolean_t);
188 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
189 #if EFSYS_OPT_LOOPBACK
190 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
191 efx_loopback_type_t);
192 #endif /* EFSYS_OPT_LOOPBACK */
193 #if EFSYS_OPT_MAC_STATS
194 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
195 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
196 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
197 uint16_t, boolean_t);
198 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
199 efsys_stat_t *, uint32_t *);
200 #endif /* EFSYS_OPT_MAC_STATS */
203 typedef struct efx_phy_ops_s {
204 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
205 efx_rc_t (*epo_reset)(efx_nic_t *);
206 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
207 efx_rc_t (*epo_verify)(efx_nic_t *);
208 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
209 #if EFSYS_OPT_PHY_STATS
210 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
212 #endif /* EFSYS_OPT_PHY_STATS */
214 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
215 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
216 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
217 efx_bist_result_t *, uint32_t *,
218 unsigned long *, size_t);
219 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
220 #endif /* EFSYS_OPT_BIST */
224 typedef struct efx_filter_ops_s {
225 efx_rc_t (*efo_init)(efx_nic_t *);
226 void (*efo_fini)(efx_nic_t *);
227 efx_rc_t (*efo_restore)(efx_nic_t *);
228 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
229 boolean_t may_replace);
230 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
231 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
232 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
233 boolean_t, boolean_t, boolean_t,
234 uint8_t const *, uint32_t);
237 extern __checkReturn efx_rc_t
238 efx_filter_reconfigure(
240 __in_ecount(6) uint8_t const *mac_addr,
241 __in boolean_t all_unicst,
242 __in boolean_t mulcst,
243 __in boolean_t all_mulcst,
244 __in boolean_t brdcst,
245 __in_ecount(6*count) uint8_t const *addrs,
246 __in uint32_t count);
248 #endif /* EFSYS_OPT_FILTER */
251 typedef struct efx_port_s {
252 efx_mac_type_t ep_mac_type;
253 uint32_t ep_phy_type;
256 uint8_t ep_mac_addr[6];
257 efx_link_mode_t ep_link_mode;
258 boolean_t ep_all_unicst;
260 boolean_t ep_all_mulcst;
262 unsigned int ep_fcntl;
263 boolean_t ep_fcntl_autoneg;
264 efx_oword_t ep_multicst_hash[2];
265 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
266 EFX_MAC_MULTICAST_LIST_MAX];
267 uint32_t ep_mulcst_addr_count;
268 #if EFSYS_OPT_LOOPBACK
269 efx_loopback_type_t ep_loopback_type;
270 efx_link_mode_t ep_loopback_link_mode;
271 #endif /* EFSYS_OPT_LOOPBACK */
272 #if EFSYS_OPT_PHY_FLAGS
273 uint32_t ep_phy_flags;
274 #endif /* EFSYS_OPT_PHY_FLAGS */
275 #if EFSYS_OPT_PHY_LED_CONTROL
276 efx_phy_led_mode_t ep_phy_led_mode;
277 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
278 efx_phy_media_type_t ep_fixed_port_type;
279 efx_phy_media_type_t ep_module_type;
280 uint32_t ep_adv_cap_mask;
281 uint32_t ep_lp_cap_mask;
282 uint32_t ep_default_adv_cap_mask;
283 uint32_t ep_phy_cap_mask;
284 boolean_t ep_mac_drain;
285 boolean_t ep_mac_stats_pending;
287 efx_bist_type_t ep_current_bist;
289 const efx_mac_ops_t *ep_emop;
290 const efx_phy_ops_t *ep_epop;
293 typedef struct efx_mon_ops_s {
294 #if EFSYS_OPT_MON_STATS
295 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
296 efx_mon_stat_value_t *);
297 #endif /* EFSYS_OPT_MON_STATS */
300 typedef struct efx_mon_s {
301 efx_mon_type_t em_type;
302 const efx_mon_ops_t *em_emop;
305 typedef struct efx_intr_ops_s {
306 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
307 void (*eio_enable)(efx_nic_t *);
308 void (*eio_disable)(efx_nic_t *);
309 void (*eio_disable_unlocked)(efx_nic_t *);
310 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
311 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
312 void (*eio_status_message)(efx_nic_t *, unsigned int,
314 void (*eio_fatal)(efx_nic_t *);
315 void (*eio_fini)(efx_nic_t *);
318 typedef struct efx_intr_s {
319 const efx_intr_ops_t *ei_eiop;
320 efsys_mem_t *ei_esmp;
321 efx_intr_type_t ei_type;
322 unsigned int ei_level;
325 typedef struct efx_nic_ops_s {
326 efx_rc_t (*eno_probe)(efx_nic_t *);
327 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
328 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
329 efx_rc_t (*eno_reset)(efx_nic_t *);
330 efx_rc_t (*eno_init)(efx_nic_t *);
331 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
332 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
333 uint32_t *, size_t *);
335 efx_rc_t (*eno_register_test)(efx_nic_t *);
336 #endif /* EFSYS_OPT_DIAG */
337 void (*eno_fini)(efx_nic_t *);
338 void (*eno_unprobe)(efx_nic_t *);
341 #ifndef EFX_TXQ_LIMIT_TARGET
342 #define EFX_TXQ_LIMIT_TARGET 259
344 #ifndef EFX_RXQ_LIMIT_TARGET
345 #define EFX_RXQ_LIMIT_TARGET 512
347 #ifndef EFX_TXQ_DC_SIZE
348 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
350 #ifndef EFX_RXQ_DC_SIZE
351 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
358 typedef struct siena_filter_spec_s {
361 uint32_t sfs_dmaq_id;
362 uint32_t sfs_dword[3];
363 } siena_filter_spec_t;
365 typedef enum siena_filter_type_e {
366 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
367 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
368 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
369 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
370 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
371 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
373 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
374 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
375 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
376 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
377 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
378 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
380 EFX_SIENA_FILTER_NTYPES
381 } siena_filter_type_t;
383 typedef enum siena_filter_tbl_id_e {
384 EFX_SIENA_FILTER_TBL_RX_IP = 0,
385 EFX_SIENA_FILTER_TBL_RX_MAC,
386 EFX_SIENA_FILTER_TBL_TX_IP,
387 EFX_SIENA_FILTER_TBL_TX_MAC,
388 EFX_SIENA_FILTER_NTBLS
389 } siena_filter_tbl_id_t;
391 typedef struct siena_filter_tbl_s {
392 int sft_size; /* number of entries */
393 int sft_used; /* active count */
394 uint32_t *sft_bitmap; /* active bitmap */
395 siena_filter_spec_t *sft_spec; /* array of saved specs */
396 } siena_filter_tbl_t;
398 typedef struct siena_filter_s {
399 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
400 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
403 #endif /* EFSYS_OPT_SIENA */
405 typedef struct efx_filter_s {
407 siena_filter_t *ef_siena_filter;
408 #endif /* EFSYS_OPT_SIENA */
409 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
410 ef10_filter_table_t *ef_ef10_filter_table;
411 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
417 siena_filter_tbl_clear(
419 __in siena_filter_tbl_id_t tbl);
421 #endif /* EFSYS_OPT_SIENA */
423 #endif /* EFSYS_OPT_FILTER */
427 typedef struct efx_mcdi_ops_s {
428 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
429 void (*emco_send_request)(efx_nic_t *, void *, size_t,
431 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
432 boolean_t (*emco_poll_response)(efx_nic_t *);
433 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
434 void (*emco_fini)(efx_nic_t *);
435 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
436 efx_mcdi_feature_id_t, boolean_t *);
437 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
441 typedef struct efx_mcdi_s {
442 const efx_mcdi_ops_t *em_emcop;
443 const efx_mcdi_transport_t *em_emtp;
444 efx_mcdi_iface_t em_emip;
447 #endif /* EFSYS_OPT_MCDI */
449 typedef struct efx_drv_cfg_s {
450 uint32_t edc_min_vi_count;
451 uint32_t edc_max_vi_count;
453 uint32_t edc_max_piobuf_count;
454 uint32_t edc_pio_alloc_size;
459 efx_family_t en_family;
460 uint32_t en_features;
461 efsys_identifier_t *en_esip;
462 efsys_lock_t *en_eslp;
463 efsys_bar_t *en_esbp;
464 unsigned int en_mod_flags;
465 unsigned int en_reset_flags;
466 efx_nic_cfg_t en_nic_cfg;
467 efx_drv_cfg_t en_drv_cfg;
471 uint32_t en_ev_qcount;
472 uint32_t en_rx_qcount;
473 uint32_t en_tx_qcount;
474 const efx_nic_ops_t *en_enop;
475 const efx_ev_ops_t *en_eevop;
476 const efx_tx_ops_t *en_etxop;
477 const efx_rx_ops_t *en_erxop;
479 efx_filter_t en_filter;
480 const efx_filter_ops_t *en_efop;
481 #endif /* EFSYS_OPT_FILTER */
484 #endif /* EFSYS_OPT_MCDI */
485 #if EFSYS_OPT_RX_SCALE
486 efx_rx_hash_support_t en_hash_support;
487 efx_rx_scale_support_t en_rss_support;
488 uint32_t en_rss_context;
489 #endif /* EFSYS_OPT_RX_SCALE */
490 uint32_t en_vport_id;
496 #endif /* EFSYS_OPT_SIENA */
499 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
505 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
506 uint32_t ena_piobuf_count;
507 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
508 uint32_t ena_pio_write_vi_base;
509 /* Memory BAR mapping regions */
510 uint32_t ena_uc_mem_map_offset;
511 size_t ena_uc_mem_map_size;
512 uint32_t ena_wc_mem_map_offset;
513 size_t ena_wc_mem_map_size;
516 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
520 #define EFX_NIC_MAGIC 0x02121996
522 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
523 const efx_ev_callbacks_t *, void *);
525 typedef struct efx_evq_rxq_state_s {
526 unsigned int eers_rx_read_ptr;
527 unsigned int eers_rx_mask;
528 } efx_evq_rxq_state_t;
533 unsigned int ee_index;
534 unsigned int ee_mask;
535 efsys_mem_t *ee_esmp;
537 uint32_t ee_stat[EV_NQSTATS];
538 #endif /* EFSYS_OPT_QSTATS */
540 efx_ev_handler_t ee_rx;
541 efx_ev_handler_t ee_tx;
542 efx_ev_handler_t ee_driver;
543 efx_ev_handler_t ee_global;
544 efx_ev_handler_t ee_drv_gen;
546 efx_ev_handler_t ee_mcdi;
547 #endif /* EFSYS_OPT_MCDI */
549 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
554 #define EFX_EVQ_MAGIC 0x08081997
556 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
562 unsigned int er_index;
563 unsigned int er_label;
564 unsigned int er_mask;
565 efsys_mem_t *er_esmp;
568 #define EFX_RXQ_MAGIC 0x15022005
573 unsigned int et_index;
574 unsigned int et_mask;
575 efsys_mem_t *et_esmp;
576 #if EFSYS_OPT_HUNTINGTON
577 uint32_t et_pio_bufnum;
578 uint32_t et_pio_blknum;
579 uint32_t et_pio_write_offset;
580 uint32_t et_pio_offset;
584 uint32_t et_stat[TX_NQSTATS];
585 #endif /* EFSYS_OPT_QSTATS */
588 #define EFX_TXQ_MAGIC 0x05092005
590 #define EFX_MAC_ADDR_COPY(_dst, _src) \
592 (_dst)[0] = (_src)[0]; \
593 (_dst)[1] = (_src)[1]; \
594 (_dst)[2] = (_src)[2]; \
595 (_dst)[3] = (_src)[3]; \
596 (_dst)[4] = (_src)[4]; \
597 (_dst)[5] = (_src)[5]; \
598 _NOTE(CONSTANTCONDITION) \
601 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
603 uint16_t *_d = (uint16_t *)(_dst); \
607 _NOTE(CONSTANTCONDITION) \
610 #if EFSYS_OPT_CHECK_REG
611 #define EFX_CHECK_REG(_enp, _reg) \
613 const char *name = #_reg; \
614 char min = name[4]; \
615 char max = name[5]; \
618 switch ((_enp)->en_family) { \
619 case EFX_FAMILY_SIENA: \
623 case EFX_FAMILY_HUNTINGTON: \
627 case EFX_FAMILY_MEDFORD: \
636 EFSYS_ASSERT3S(rev, >=, min); \
637 EFSYS_ASSERT3S(rev, <=, max); \
639 _NOTE(CONSTANTCONDITION) \
642 #define EFX_CHECK_REG(_enp, _reg) do { \
643 _NOTE(CONSTANTCONDITION) \
647 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
649 EFX_CHECK_REG((_enp), (_reg)); \
650 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
652 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
653 uint32_t, _reg ## _OFST, \
654 uint32_t, (_edp)->ed_u32[0]); \
655 _NOTE(CONSTANTCONDITION) \
658 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
660 EFX_CHECK_REG((_enp), (_reg)); \
661 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
662 uint32_t, _reg ## _OFST, \
663 uint32_t, (_edp)->ed_u32[0]); \
664 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
666 _NOTE(CONSTANTCONDITION) \
669 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
671 EFX_CHECK_REG((_enp), (_reg)); \
672 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
674 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
675 uint32_t, _reg ## _OFST, \
676 uint32_t, (_eqp)->eq_u32[1], \
677 uint32_t, (_eqp)->eq_u32[0]); \
678 _NOTE(CONSTANTCONDITION) \
681 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
683 EFX_CHECK_REG((_enp), (_reg)); \
684 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
685 uint32_t, _reg ## _OFST, \
686 uint32_t, (_eqp)->eq_u32[1], \
687 uint32_t, (_eqp)->eq_u32[0]); \
688 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
690 _NOTE(CONSTANTCONDITION) \
693 #define EFX_BAR_READO(_enp, _reg, _eop) \
695 EFX_CHECK_REG((_enp), (_reg)); \
696 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
698 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
699 uint32_t, _reg ## _OFST, \
700 uint32_t, (_eop)->eo_u32[3], \
701 uint32_t, (_eop)->eo_u32[2], \
702 uint32_t, (_eop)->eo_u32[1], \
703 uint32_t, (_eop)->eo_u32[0]); \
704 _NOTE(CONSTANTCONDITION) \
707 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
709 EFX_CHECK_REG((_enp), (_reg)); \
710 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
711 uint32_t, _reg ## _OFST, \
712 uint32_t, (_eop)->eo_u32[3], \
713 uint32_t, (_eop)->eo_u32[2], \
714 uint32_t, (_eop)->eo_u32[1], \
715 uint32_t, (_eop)->eo_u32[0]); \
716 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
718 _NOTE(CONSTANTCONDITION) \
721 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
723 EFX_CHECK_REG((_enp), (_reg)); \
724 EFSYS_BAR_READD((_enp)->en_esbp, \
725 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
727 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
728 uint32_t, (_index), \
729 uint32_t, _reg ## _OFST, \
730 uint32_t, (_edp)->ed_u32[0]); \
731 _NOTE(CONSTANTCONDITION) \
734 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
736 EFX_CHECK_REG((_enp), (_reg)); \
737 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
738 uint32_t, (_index), \
739 uint32_t, _reg ## _OFST, \
740 uint32_t, (_edp)->ed_u32[0]); \
741 EFSYS_BAR_WRITED((_enp)->en_esbp, \
742 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
744 _NOTE(CONSTANTCONDITION) \
747 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
749 EFX_CHECK_REG((_enp), (_reg)); \
750 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
751 uint32_t, (_index), \
752 uint32_t, _reg ## _OFST, \
753 uint32_t, (_edp)->ed_u32[0]); \
754 EFSYS_BAR_WRITED((_enp)->en_esbp, \
756 (2 * sizeof (efx_dword_t)) + \
757 ((_index) * _reg ## _STEP)), \
759 _NOTE(CONSTANTCONDITION) \
762 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
764 EFX_CHECK_REG((_enp), (_reg)); \
765 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
766 uint32_t, (_index), \
767 uint32_t, _reg ## _OFST, \
768 uint32_t, (_edp)->ed_u32[0]); \
769 EFSYS_BAR_WRITED((_enp)->en_esbp, \
771 (3 * sizeof (efx_dword_t)) + \
772 ((_index) * _reg ## _STEP)), \
774 _NOTE(CONSTANTCONDITION) \
777 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
779 EFX_CHECK_REG((_enp), (_reg)); \
780 EFSYS_BAR_READQ((_enp)->en_esbp, \
781 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
783 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
784 uint32_t, (_index), \
785 uint32_t, _reg ## _OFST, \
786 uint32_t, (_eqp)->eq_u32[1], \
787 uint32_t, (_eqp)->eq_u32[0]); \
788 _NOTE(CONSTANTCONDITION) \
791 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
793 EFX_CHECK_REG((_enp), (_reg)); \
794 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
795 uint32_t, (_index), \
796 uint32_t, _reg ## _OFST, \
797 uint32_t, (_eqp)->eq_u32[1], \
798 uint32_t, (_eqp)->eq_u32[0]); \
799 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
800 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
802 _NOTE(CONSTANTCONDITION) \
805 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
807 EFX_CHECK_REG((_enp), (_reg)); \
808 EFSYS_BAR_READO((_enp)->en_esbp, \
809 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
811 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
812 uint32_t, (_index), \
813 uint32_t, _reg ## _OFST, \
814 uint32_t, (_eop)->eo_u32[3], \
815 uint32_t, (_eop)->eo_u32[2], \
816 uint32_t, (_eop)->eo_u32[1], \
817 uint32_t, (_eop)->eo_u32[0]); \
818 _NOTE(CONSTANTCONDITION) \
821 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
823 EFX_CHECK_REG((_enp), (_reg)); \
824 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
825 uint32_t, (_index), \
826 uint32_t, _reg ## _OFST, \
827 uint32_t, (_eop)->eo_u32[3], \
828 uint32_t, (_eop)->eo_u32[2], \
829 uint32_t, (_eop)->eo_u32[1], \
830 uint32_t, (_eop)->eo_u32[0]); \
831 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
832 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
834 _NOTE(CONSTANTCONDITION) \
838 * Allow drivers to perform optimised 128-bit doorbell writes.
839 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
840 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
841 * the need for locking in the host, and are the only ones known to be safe to
842 * use 128-bites write with.
844 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
846 EFX_CHECK_REG((_enp), (_reg)); \
847 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
850 uint32_t, (_index), \
851 uint32_t, _reg ## _OFST, \
852 uint32_t, (_eop)->eo_u32[3], \
853 uint32_t, (_eop)->eo_u32[2], \
854 uint32_t, (_eop)->eo_u32[1], \
855 uint32_t, (_eop)->eo_u32[0]); \
856 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
857 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
859 _NOTE(CONSTANTCONDITION) \
862 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
864 unsigned int _new = (_wptr); \
865 unsigned int _old = (_owptr); \
867 if ((_new) >= (_old)) \
868 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
869 (_old) * sizeof (efx_desc_t), \
870 ((_new) - (_old)) * sizeof (efx_desc_t)); \
873 * It is cheaper to sync entire map than sync \
874 * two parts especially when offset/size are \
875 * ignored and entire map is synced in any case.\
877 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
879 (_entries) * sizeof (efx_desc_t)); \
880 _NOTE(CONSTANTCONDITION) \
883 extern __checkReturn efx_rc_t
885 __in efx_nic_t *enp);
887 extern __checkReturn efx_rc_t
889 __in efx_nic_t *enp);
892 efx_mac_multicast_hash_compute(
893 __in_ecount(6*count) uint8_t const *addrs,
895 __out efx_oword_t *hash_low,
896 __out efx_oword_t *hash_high);
898 extern __checkReturn efx_rc_t
900 __in efx_nic_t *enp);
904 __in efx_nic_t *enp);
908 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
910 typedef struct efx_register_set_s {
911 unsigned int address;
915 } efx_register_set_t;
917 extern __checkReturn efx_rc_t
918 efx_nic_test_registers(
920 __in efx_register_set_t *rsp,
923 extern __checkReturn efx_rc_t
926 __in efx_register_set_t *rsp,
927 __in efx_pattern_type_t pattern,
930 #endif /* EFSYS_OPT_DIAG */
934 extern __checkReturn efx_rc_t
935 efx_mcdi_set_workaround(
938 __in boolean_t enabled,
939 __out_opt uint32_t *flagsp);
941 extern __checkReturn efx_rc_t
942 efx_mcdi_get_workarounds(
944 __out_opt uint32_t *implementedp,
945 __out_opt uint32_t *enabledp);
947 #endif /* EFSYS_OPT_MCDI */
949 #if EFSYS_OPT_MAC_STATS
952 * Closed range of stats (i.e. the first and the last are included).
953 * The last must be greater or equal (if the range is one item only) to
956 struct efx_mac_stats_range {
957 efx_mac_stat_t first;
962 efx_mac_stats_mask_add_ranges(
963 __inout_bcount(mask_size) uint32_t *maskp,
964 __in size_t mask_size,
965 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
966 __in unsigned int rng_count);
968 #endif /* EFSYS_OPT_MAC_STATS */
974 #endif /* _SYS_EFX_IMPL_H */