2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
52 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
53 #include "ef10_impl.h"
54 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
60 #define EFX_MOD_MCDI 0x00000001
61 #define EFX_MOD_PROBE 0x00000002
62 #define EFX_MOD_NVRAM 0x00000004
63 #define EFX_MOD_VPD 0x00000008
64 #define EFX_MOD_NIC 0x00000010
65 #define EFX_MOD_INTR 0x00000020
66 #define EFX_MOD_EV 0x00000040
67 #define EFX_MOD_RX 0x00000080
68 #define EFX_MOD_TX 0x00000100
69 #define EFX_MOD_PORT 0x00000200
70 #define EFX_MOD_MON 0x00000400
71 #define EFX_MOD_FILTER 0x00001000
72 #define EFX_MOD_LIC 0x00002000
74 #define EFX_RESET_PHY 0x00000001
75 #define EFX_RESET_RXQ_ERR 0x00000002
76 #define EFX_RESET_TXQ_ERR 0x00000004
78 typedef enum efx_mac_type_e {
86 typedef struct efx_ev_ops_s {
87 efx_rc_t (*eevo_init)(efx_nic_t *);
88 void (*eevo_fini)(efx_nic_t *);
89 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
90 efsys_mem_t *, size_t, uint32_t,
91 uint32_t, uint32_t, efx_evq_t *);
92 void (*eevo_qdestroy)(efx_evq_t *);
93 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
94 void (*eevo_qpost)(efx_evq_t *, uint16_t);
95 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
98 typedef struct efx_tx_ops_s {
99 efx_rc_t (*etxo_init)(efx_nic_t *);
100 void (*etxo_fini)(efx_nic_t *);
101 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
102 unsigned int, unsigned int,
103 efsys_mem_t *, size_t,
105 efx_evq_t *, efx_txq_t *,
107 void (*etxo_qdestroy)(efx_txq_t *);
108 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
109 unsigned int, unsigned int,
111 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
112 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
113 efx_rc_t (*etxo_qflush)(efx_txq_t *);
114 void (*etxo_qenable)(efx_txq_t *);
115 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
116 void (*etxo_qpio_disable)(efx_txq_t *);
117 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
119 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
121 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
122 unsigned int, unsigned int,
124 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
127 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
130 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
133 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
137 typedef struct efx_rx_ops_s {
138 efx_rc_t (*erxo_init)(efx_nic_t *);
139 void (*erxo_fini)(efx_nic_t *);
140 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
142 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
143 unsigned int, unsigned int,
145 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
146 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
147 void (*erxo_qenable)(efx_rxq_t *);
148 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
149 unsigned int, efx_rxq_type_t,
150 efsys_mem_t *, size_t, uint32_t,
151 efx_evq_t *, efx_rxq_t *);
152 void (*erxo_qdestroy)(efx_rxq_t *);
155 typedef struct efx_mac_ops_s {
156 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
157 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
158 efx_rc_t (*emo_addr_set)(efx_nic_t *);
159 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
160 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
161 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
162 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
163 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
164 efx_rxq_t *, boolean_t);
165 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
168 typedef struct efx_phy_ops_s {
169 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
170 efx_rc_t (*epo_reset)(efx_nic_t *);
171 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
172 efx_rc_t (*epo_verify)(efx_nic_t *);
173 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
177 typedef struct efx_filter_ops_s {
178 efx_rc_t (*efo_init)(efx_nic_t *);
179 void (*efo_fini)(efx_nic_t *);
180 efx_rc_t (*efo_restore)(efx_nic_t *);
181 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
182 boolean_t may_replace);
183 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
184 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
185 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
186 boolean_t, boolean_t, boolean_t,
187 uint8_t const *, uint32_t);
190 extern __checkReturn efx_rc_t
191 efx_filter_reconfigure(
193 __in_ecount(6) uint8_t const *mac_addr,
194 __in boolean_t all_unicst,
195 __in boolean_t mulcst,
196 __in boolean_t all_mulcst,
197 __in boolean_t brdcst,
198 __in_ecount(6*count) uint8_t const *addrs,
199 __in uint32_t count);
201 #endif /* EFSYS_OPT_FILTER */
204 typedef struct efx_port_s {
205 efx_mac_type_t ep_mac_type;
206 uint32_t ep_phy_type;
209 uint8_t ep_mac_addr[6];
210 efx_link_mode_t ep_link_mode;
211 boolean_t ep_all_unicst;
213 boolean_t ep_all_mulcst;
215 unsigned int ep_fcntl;
216 boolean_t ep_fcntl_autoneg;
217 efx_oword_t ep_multicst_hash[2];
218 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
219 EFX_MAC_MULTICAST_LIST_MAX];
220 uint32_t ep_mulcst_addr_count;
221 efx_phy_media_type_t ep_fixed_port_type;
222 efx_phy_media_type_t ep_module_type;
223 uint32_t ep_adv_cap_mask;
224 uint32_t ep_lp_cap_mask;
225 uint32_t ep_default_adv_cap_mask;
226 uint32_t ep_phy_cap_mask;
227 boolean_t ep_mac_drain;
228 boolean_t ep_mac_stats_pending;
229 const efx_mac_ops_t *ep_emop;
230 const efx_phy_ops_t *ep_epop;
233 typedef struct efx_mon_ops_s {
236 typedef struct efx_mon_s {
237 efx_mon_type_t em_type;
238 const efx_mon_ops_t *em_emop;
241 typedef struct efx_intr_ops_s {
242 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
243 void (*eio_enable)(efx_nic_t *);
244 void (*eio_disable)(efx_nic_t *);
245 void (*eio_disable_unlocked)(efx_nic_t *);
246 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
247 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
248 void (*eio_status_message)(efx_nic_t *, unsigned int,
250 void (*eio_fatal)(efx_nic_t *);
251 void (*eio_fini)(efx_nic_t *);
254 typedef struct efx_intr_s {
255 const efx_intr_ops_t *ei_eiop;
256 efsys_mem_t *ei_esmp;
257 efx_intr_type_t ei_type;
258 unsigned int ei_level;
261 typedef struct efx_nic_ops_s {
262 efx_rc_t (*eno_probe)(efx_nic_t *);
263 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
264 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
265 efx_rc_t (*eno_reset)(efx_nic_t *);
266 efx_rc_t (*eno_init)(efx_nic_t *);
267 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
268 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
269 uint32_t *, size_t *);
270 void (*eno_fini)(efx_nic_t *);
271 void (*eno_unprobe)(efx_nic_t *);
274 #ifndef EFX_TXQ_LIMIT_TARGET
275 #define EFX_TXQ_LIMIT_TARGET 259
277 #ifndef EFX_RXQ_LIMIT_TARGET
278 #define EFX_RXQ_LIMIT_TARGET 512
280 #ifndef EFX_TXQ_DC_SIZE
281 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
283 #ifndef EFX_RXQ_DC_SIZE
284 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
291 typedef struct siena_filter_spec_s {
294 uint32_t sfs_dmaq_id;
295 uint32_t sfs_dword[3];
296 } siena_filter_spec_t;
298 typedef enum siena_filter_type_e {
299 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
300 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
301 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
302 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
303 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
304 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
306 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
307 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
308 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
309 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
310 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
311 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
313 EFX_SIENA_FILTER_NTYPES
314 } siena_filter_type_t;
316 typedef enum siena_filter_tbl_id_e {
317 EFX_SIENA_FILTER_TBL_RX_IP = 0,
318 EFX_SIENA_FILTER_TBL_RX_MAC,
319 EFX_SIENA_FILTER_TBL_TX_IP,
320 EFX_SIENA_FILTER_TBL_TX_MAC,
321 EFX_SIENA_FILTER_NTBLS
322 } siena_filter_tbl_id_t;
324 typedef struct siena_filter_tbl_s {
325 int sft_size; /* number of entries */
326 int sft_used; /* active count */
327 uint32_t *sft_bitmap; /* active bitmap */
328 siena_filter_spec_t *sft_spec; /* array of saved specs */
329 } siena_filter_tbl_t;
331 typedef struct siena_filter_s {
332 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
333 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
336 #endif /* EFSYS_OPT_SIENA */
338 typedef struct efx_filter_s {
340 siena_filter_t *ef_siena_filter;
341 #endif /* EFSYS_OPT_SIENA */
342 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
343 ef10_filter_table_t *ef_ef10_filter_table;
344 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
350 siena_filter_tbl_clear(
352 __in siena_filter_tbl_id_t tbl);
354 #endif /* EFSYS_OPT_SIENA */
356 #endif /* EFSYS_OPT_FILTER */
360 typedef struct efx_mcdi_ops_s {
361 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
362 void (*emco_send_request)(efx_nic_t *, void *, size_t,
364 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
365 boolean_t (*emco_poll_response)(efx_nic_t *);
366 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
367 void (*emco_fini)(efx_nic_t *);
368 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
369 efx_mcdi_feature_id_t, boolean_t *);
370 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
374 typedef struct efx_mcdi_s {
375 const efx_mcdi_ops_t *em_emcop;
376 const efx_mcdi_transport_t *em_emtp;
377 efx_mcdi_iface_t em_emip;
380 #endif /* EFSYS_OPT_MCDI */
382 typedef struct efx_drv_cfg_s {
383 uint32_t edc_min_vi_count;
384 uint32_t edc_max_vi_count;
386 uint32_t edc_max_piobuf_count;
387 uint32_t edc_pio_alloc_size;
392 efx_family_t en_family;
393 uint32_t en_features;
394 efsys_identifier_t *en_esip;
395 efsys_lock_t *en_eslp;
396 efsys_bar_t *en_esbp;
397 unsigned int en_mod_flags;
398 unsigned int en_reset_flags;
399 efx_nic_cfg_t en_nic_cfg;
400 efx_drv_cfg_t en_drv_cfg;
404 uint32_t en_ev_qcount;
405 uint32_t en_rx_qcount;
406 uint32_t en_tx_qcount;
407 const efx_nic_ops_t *en_enop;
408 const efx_ev_ops_t *en_eevop;
409 const efx_tx_ops_t *en_etxop;
410 const efx_rx_ops_t *en_erxop;
412 efx_filter_t en_filter;
413 const efx_filter_ops_t *en_efop;
414 #endif /* EFSYS_OPT_FILTER */
417 #endif /* EFSYS_OPT_MCDI */
418 uint32_t en_vport_id;
424 #endif /* EFSYS_OPT_SIENA */
427 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
433 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
434 uint32_t ena_piobuf_count;
435 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
436 uint32_t ena_pio_write_vi_base;
437 /* Memory BAR mapping regions */
438 uint32_t ena_uc_mem_map_offset;
439 size_t ena_uc_mem_map_size;
440 uint32_t ena_wc_mem_map_offset;
441 size_t ena_wc_mem_map_size;
444 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
448 #define EFX_NIC_MAGIC 0x02121996
450 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
451 const efx_ev_callbacks_t *, void *);
453 typedef struct efx_evq_rxq_state_s {
454 unsigned int eers_rx_read_ptr;
455 unsigned int eers_rx_mask;
456 } efx_evq_rxq_state_t;
461 unsigned int ee_index;
462 unsigned int ee_mask;
463 efsys_mem_t *ee_esmp;
465 efx_ev_handler_t ee_rx;
466 efx_ev_handler_t ee_tx;
467 efx_ev_handler_t ee_driver;
468 efx_ev_handler_t ee_global;
469 efx_ev_handler_t ee_drv_gen;
471 efx_ev_handler_t ee_mcdi;
472 #endif /* EFSYS_OPT_MCDI */
474 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
479 #define EFX_EVQ_MAGIC 0x08081997
481 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
487 unsigned int er_index;
488 unsigned int er_label;
489 unsigned int er_mask;
490 efsys_mem_t *er_esmp;
493 #define EFX_RXQ_MAGIC 0x15022005
498 unsigned int et_index;
499 unsigned int et_mask;
500 efsys_mem_t *et_esmp;
501 #if EFSYS_OPT_HUNTINGTON
502 uint32_t et_pio_bufnum;
503 uint32_t et_pio_blknum;
504 uint32_t et_pio_write_offset;
505 uint32_t et_pio_offset;
510 #define EFX_TXQ_MAGIC 0x05092005
512 #define EFX_MAC_ADDR_COPY(_dst, _src) \
514 (_dst)[0] = (_src)[0]; \
515 (_dst)[1] = (_src)[1]; \
516 (_dst)[2] = (_src)[2]; \
517 (_dst)[3] = (_src)[3]; \
518 (_dst)[4] = (_src)[4]; \
519 (_dst)[5] = (_src)[5]; \
520 _NOTE(CONSTANTCONDITION) \
523 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
525 uint16_t *_d = (uint16_t *)(_dst); \
529 _NOTE(CONSTANTCONDITION) \
532 #if EFSYS_OPT_CHECK_REG
533 #define EFX_CHECK_REG(_enp, _reg) \
535 const char *name = #_reg; \
536 char min = name[4]; \
537 char max = name[5]; \
540 switch ((_enp)->en_family) { \
541 case EFX_FAMILY_SIENA: \
545 case EFX_FAMILY_HUNTINGTON: \
549 case EFX_FAMILY_MEDFORD: \
558 EFSYS_ASSERT3S(rev, >=, min); \
559 EFSYS_ASSERT3S(rev, <=, max); \
561 _NOTE(CONSTANTCONDITION) \
564 #define EFX_CHECK_REG(_enp, _reg) do { \
565 _NOTE(CONSTANTCONDITION) \
569 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
571 EFX_CHECK_REG((_enp), (_reg)); \
572 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
574 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
575 uint32_t, _reg ## _OFST, \
576 uint32_t, (_edp)->ed_u32[0]); \
577 _NOTE(CONSTANTCONDITION) \
580 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
582 EFX_CHECK_REG((_enp), (_reg)); \
583 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
584 uint32_t, _reg ## _OFST, \
585 uint32_t, (_edp)->ed_u32[0]); \
586 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
588 _NOTE(CONSTANTCONDITION) \
591 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
593 EFX_CHECK_REG((_enp), (_reg)); \
594 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
596 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
597 uint32_t, _reg ## _OFST, \
598 uint32_t, (_eqp)->eq_u32[1], \
599 uint32_t, (_eqp)->eq_u32[0]); \
600 _NOTE(CONSTANTCONDITION) \
603 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
605 EFX_CHECK_REG((_enp), (_reg)); \
606 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
607 uint32_t, _reg ## _OFST, \
608 uint32_t, (_eqp)->eq_u32[1], \
609 uint32_t, (_eqp)->eq_u32[0]); \
610 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
612 _NOTE(CONSTANTCONDITION) \
615 #define EFX_BAR_READO(_enp, _reg, _eop) \
617 EFX_CHECK_REG((_enp), (_reg)); \
618 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
620 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
621 uint32_t, _reg ## _OFST, \
622 uint32_t, (_eop)->eo_u32[3], \
623 uint32_t, (_eop)->eo_u32[2], \
624 uint32_t, (_eop)->eo_u32[1], \
625 uint32_t, (_eop)->eo_u32[0]); \
626 _NOTE(CONSTANTCONDITION) \
629 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
631 EFX_CHECK_REG((_enp), (_reg)); \
632 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
633 uint32_t, _reg ## _OFST, \
634 uint32_t, (_eop)->eo_u32[3], \
635 uint32_t, (_eop)->eo_u32[2], \
636 uint32_t, (_eop)->eo_u32[1], \
637 uint32_t, (_eop)->eo_u32[0]); \
638 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
640 _NOTE(CONSTANTCONDITION) \
643 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
645 EFX_CHECK_REG((_enp), (_reg)); \
646 EFSYS_BAR_READD((_enp)->en_esbp, \
647 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
649 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
650 uint32_t, (_index), \
651 uint32_t, _reg ## _OFST, \
652 uint32_t, (_edp)->ed_u32[0]); \
653 _NOTE(CONSTANTCONDITION) \
656 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
658 EFX_CHECK_REG((_enp), (_reg)); \
659 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
660 uint32_t, (_index), \
661 uint32_t, _reg ## _OFST, \
662 uint32_t, (_edp)->ed_u32[0]); \
663 EFSYS_BAR_WRITED((_enp)->en_esbp, \
664 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
666 _NOTE(CONSTANTCONDITION) \
669 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
671 EFX_CHECK_REG((_enp), (_reg)); \
672 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
673 uint32_t, (_index), \
674 uint32_t, _reg ## _OFST, \
675 uint32_t, (_edp)->ed_u32[0]); \
676 EFSYS_BAR_WRITED((_enp)->en_esbp, \
678 (2 * sizeof (efx_dword_t)) + \
679 ((_index) * _reg ## _STEP)), \
681 _NOTE(CONSTANTCONDITION) \
684 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
686 EFX_CHECK_REG((_enp), (_reg)); \
687 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
688 uint32_t, (_index), \
689 uint32_t, _reg ## _OFST, \
690 uint32_t, (_edp)->ed_u32[0]); \
691 EFSYS_BAR_WRITED((_enp)->en_esbp, \
693 (3 * sizeof (efx_dword_t)) + \
694 ((_index) * _reg ## _STEP)), \
696 _NOTE(CONSTANTCONDITION) \
699 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
701 EFX_CHECK_REG((_enp), (_reg)); \
702 EFSYS_BAR_READQ((_enp)->en_esbp, \
703 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
705 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
706 uint32_t, (_index), \
707 uint32_t, _reg ## _OFST, \
708 uint32_t, (_eqp)->eq_u32[1], \
709 uint32_t, (_eqp)->eq_u32[0]); \
710 _NOTE(CONSTANTCONDITION) \
713 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
715 EFX_CHECK_REG((_enp), (_reg)); \
716 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
717 uint32_t, (_index), \
718 uint32_t, _reg ## _OFST, \
719 uint32_t, (_eqp)->eq_u32[1], \
720 uint32_t, (_eqp)->eq_u32[0]); \
721 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
722 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
724 _NOTE(CONSTANTCONDITION) \
727 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
729 EFX_CHECK_REG((_enp), (_reg)); \
730 EFSYS_BAR_READO((_enp)->en_esbp, \
731 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
733 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
734 uint32_t, (_index), \
735 uint32_t, _reg ## _OFST, \
736 uint32_t, (_eop)->eo_u32[3], \
737 uint32_t, (_eop)->eo_u32[2], \
738 uint32_t, (_eop)->eo_u32[1], \
739 uint32_t, (_eop)->eo_u32[0]); \
740 _NOTE(CONSTANTCONDITION) \
743 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
745 EFX_CHECK_REG((_enp), (_reg)); \
746 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
747 uint32_t, (_index), \
748 uint32_t, _reg ## _OFST, \
749 uint32_t, (_eop)->eo_u32[3], \
750 uint32_t, (_eop)->eo_u32[2], \
751 uint32_t, (_eop)->eo_u32[1], \
752 uint32_t, (_eop)->eo_u32[0]); \
753 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
754 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
756 _NOTE(CONSTANTCONDITION) \
760 * Allow drivers to perform optimised 128-bit doorbell writes.
761 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
762 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
763 * the need for locking in the host, and are the only ones known to be safe to
764 * use 128-bites write with.
766 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
768 EFX_CHECK_REG((_enp), (_reg)); \
769 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
772 uint32_t, (_index), \
773 uint32_t, _reg ## _OFST, \
774 uint32_t, (_eop)->eo_u32[3], \
775 uint32_t, (_eop)->eo_u32[2], \
776 uint32_t, (_eop)->eo_u32[1], \
777 uint32_t, (_eop)->eo_u32[0]); \
778 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
779 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
781 _NOTE(CONSTANTCONDITION) \
784 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
786 unsigned int _new = (_wptr); \
787 unsigned int _old = (_owptr); \
789 if ((_new) >= (_old)) \
790 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
791 (_old) * sizeof (efx_desc_t), \
792 ((_new) - (_old)) * sizeof (efx_desc_t)); \
795 * It is cheaper to sync entire map than sync \
796 * two parts especially when offset/size are \
797 * ignored and entire map is synced in any case.\
799 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
801 (_entries) * sizeof (efx_desc_t)); \
802 _NOTE(CONSTANTCONDITION) \
805 extern __checkReturn efx_rc_t
807 __in efx_nic_t *enp);
809 extern __checkReturn efx_rc_t
811 __in efx_nic_t *enp);
814 efx_mac_multicast_hash_compute(
815 __in_ecount(6*count) uint8_t const *addrs,
817 __out efx_oword_t *hash_low,
818 __out efx_oword_t *hash_high);
820 extern __checkReturn efx_rc_t
822 __in efx_nic_t *enp);
826 __in efx_nic_t *enp);
830 extern __checkReturn efx_rc_t
831 efx_mcdi_set_workaround(
834 __in boolean_t enabled,
835 __out_opt uint32_t *flagsp);
837 extern __checkReturn efx_rc_t
838 efx_mcdi_get_workarounds(
840 __out_opt uint32_t *implementedp,
841 __out_opt uint32_t *enabledp);
843 #endif /* EFSYS_OPT_MCDI */
849 #endif /* _SYS_EFX_IMPL_H */