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37 static __checkReturn efx_rc_t
40 __in efx_intr_type_t type,
41 __in efsys_mem_t *esmp);
52 siena_intr_disable_unlocked(
55 static __checkReturn efx_rc_t
58 __in unsigned int level);
65 siena_intr_status_line(
67 __out boolean_t *fatalp,
68 __out uint32_t *qmaskp);
71 siena_intr_status_message(
73 __in unsigned int message,
74 __out boolean_t *fatalp);
80 static __checkReturn boolean_t
81 siena_intr_check_fatal(
85 #endif /* EFSYS_OPT_SIENA */
89 static const efx_intr_ops_t __efx_intr_siena_ops = {
90 siena_intr_init, /* eio_init */
91 siena_intr_enable, /* eio_enable */
92 siena_intr_disable, /* eio_disable */
93 siena_intr_disable_unlocked, /* eio_disable_unlocked */
94 siena_intr_trigger, /* eio_trigger */
95 siena_intr_status_line, /* eio_status_line */
96 siena_intr_status_message, /* eio_status_message */
97 siena_intr_fatal, /* eio_fatal */
98 siena_intr_fini, /* eio_fini */
100 #endif /* EFSYS_OPT_SIENA */
102 __checkReturn efx_rc_t
105 __in efx_intr_type_t type,
106 __in efsys_mem_t *esmp)
108 efx_intr_t *eip = &(enp->en_intr);
109 const efx_intr_ops_t *eiop;
112 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
113 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
115 if (enp->en_mod_flags & EFX_MOD_INTR) {
124 enp->en_mod_flags |= EFX_MOD_INTR;
126 switch (enp->en_family) {
128 case EFX_FAMILY_SIENA:
129 eiop = &__efx_intr_siena_ops;
131 #endif /* EFSYS_OPT_SIENA */
134 EFSYS_ASSERT(B_FALSE);
139 if ((rc = eiop->eio_init(enp, type, esmp)) != 0)
151 EFSYS_PROBE1(fail1, efx_rc_t, rc);
160 efx_intr_t *eip = &(enp->en_intr);
161 const efx_intr_ops_t *eiop = eip->ei_eiop;
163 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
164 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
165 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
169 enp->en_mod_flags &= ~EFX_MOD_INTR;
176 efx_intr_t *eip = &(enp->en_intr);
177 const efx_intr_ops_t *eiop = eip->ei_eiop;
179 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
180 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
182 eiop->eio_enable(enp);
189 efx_intr_t *eip = &(enp->en_intr);
190 const efx_intr_ops_t *eiop = eip->ei_eiop;
192 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
193 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
195 eiop->eio_disable(enp);
199 efx_intr_disable_unlocked(
202 efx_intr_t *eip = &(enp->en_intr);
203 const efx_intr_ops_t *eiop = eip->ei_eiop;
205 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
206 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
208 eiop->eio_disable_unlocked(enp);
212 __checkReturn efx_rc_t
215 __in unsigned int level)
217 efx_intr_t *eip = &(enp->en_intr);
218 const efx_intr_ops_t *eiop = eip->ei_eiop;
220 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
221 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
223 return (eiop->eio_trigger(enp, level));
227 efx_intr_status_line(
229 __out boolean_t *fatalp,
230 __out uint32_t *qmaskp)
232 efx_intr_t *eip = &(enp->en_intr);
233 const efx_intr_ops_t *eiop = eip->ei_eiop;
235 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
236 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
238 eiop->eio_status_line(enp, fatalp, qmaskp);
242 efx_intr_status_message(
244 __in unsigned int message,
245 __out boolean_t *fatalp)
247 efx_intr_t *eip = &(enp->en_intr);
248 const efx_intr_ops_t *eiop = eip->ei_eiop;
250 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
251 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
253 eiop->eio_status_message(enp, message, fatalp);
260 efx_intr_t *eip = &(enp->en_intr);
261 const efx_intr_ops_t *eiop = eip->ei_eiop;
263 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
266 eiop->eio_fatal(enp);
270 /* ************************************************************************* */
271 /* ************************************************************************* */
272 /* ************************************************************************* */
276 static __checkReturn efx_rc_t
279 __in efx_intr_type_t type,
280 __in efsys_mem_t *esmp)
282 efx_intr_t *eip = &(enp->en_intr);
286 * bug17213 workaround.
288 * Under legacy interrupts, don't share a level between fatal
289 * interrupts and event queue interrupts. Under MSI-X, they
290 * must share, or we won't get an interrupt.
292 if (enp->en_family == EFX_FAMILY_SIENA &&
293 eip->ei_type == EFX_INTR_LINE)
294 eip->ei_level = 0x1f;
298 /* Enable all the genuinely fatal interrupts */
299 EFX_SET_OWORD(oword);
300 EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0);
301 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0);
302 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0);
303 if (enp->en_family >= EFX_FAMILY_SIENA)
304 EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0);
305 EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword);
307 /* Set up the interrupt address register */
308 EFX_POPULATE_OWORD_3(oword,
309 FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0,
310 FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff,
311 FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32);
312 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
321 efx_intr_t *eip = &(enp->en_intr);
324 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
326 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
327 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1);
328 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
337 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
338 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
339 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
345 siena_intr_disable_unlocked(
350 EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
352 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
353 EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
357 static __checkReturn efx_rc_t
360 __in unsigned int level)
362 efx_intr_t *eip = &(enp->en_intr);
368 /* bug16757: No event queues can be initialized */
369 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
371 if (level >= EFX_NINTR_SIENA) {
376 if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL))
377 return (ENOTSUP); /* avoid EFSYS_PROBE() */
381 /* Trigger a test interrupt */
382 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
383 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel);
384 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1);
385 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
388 * Wait up to 100ms for the interrupt to be raised before restoring
389 * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will
390 * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL
394 EFSYS_SPIN(100); /* 100us */
396 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
397 } while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000);
399 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
400 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
405 EFSYS_PROBE1(fail1, efx_rc_t, rc);
410 static __checkReturn boolean_t
411 siena_intr_check_fatal(
414 efx_intr_t *eip = &(enp->en_intr);
415 efsys_mem_t *esmp = eip->ei_esmp;
418 /* Read the syndrome */
419 EFSYS_MEM_READO(esmp, 0, &oword);
421 if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) {
424 /* Clear the fatal interrupt condition */
425 EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0);
426 EFSYS_MEM_WRITEO(esmp, 0, &oword);
435 siena_intr_status_line(
437 __out boolean_t *fatalp,
438 __out uint32_t *qmaskp)
440 efx_intr_t *eip = &(enp->en_intr);
443 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
444 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
447 * Read the queue mask and implicitly acknowledge the
450 EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
451 *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
453 EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
455 if (*qmaskp & (1U << eip->ei_level))
456 *fatalp = siena_intr_check_fatal(enp);
462 siena_intr_status_message(
464 __in unsigned int message,
465 __out boolean_t *fatalp)
467 efx_intr_t *eip = &(enp->en_intr);
469 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
470 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
472 if (message == eip->ei_level)
473 *fatalp = siena_intr_check_fatal(enp);
483 #if EFSYS_OPT_DECODE_INTR_FATAL
487 EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal);
488 EFX_ZERO_OWORD(mem_per);
490 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 ||
491 EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
492 EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per);
494 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0)
495 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0);
497 if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0)
498 EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0);
500 if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
501 EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR,
502 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
503 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
505 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0)
506 EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0);
508 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0)
509 EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0);
511 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0)
512 EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0);
514 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0)
515 EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0);
517 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0)
518 EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0);
520 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0)
521 EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0);
523 if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0)
524 EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0);
526 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0)
527 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR,
528 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
529 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
541 /* Clear the interrupt address register */
542 EFX_ZERO_OWORD(oword);
543 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
546 #endif /* EFSYS_OPT_SIENA */