2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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37 static __checkReturn efx_rc_t
40 __in efx_intr_type_t type,
41 __in efsys_mem_t *esmp);
52 siena_intr_disable_unlocked(
55 static __checkReturn efx_rc_t
58 __in unsigned int level);
65 siena_intr_status_line(
67 __out boolean_t *fatalp,
68 __out uint32_t *qmaskp);
71 siena_intr_status_message(
73 __in unsigned int message,
74 __out boolean_t *fatalp);
80 static __checkReturn boolean_t
81 siena_intr_check_fatal(
85 #endif /* EFSYS_OPT_SIENA */
89 static const efx_intr_ops_t __efx_intr_siena_ops = {
90 siena_intr_init, /* eio_init */
91 siena_intr_enable, /* eio_enable */
92 siena_intr_disable, /* eio_disable */
93 siena_intr_disable_unlocked, /* eio_disable_unlocked */
94 siena_intr_trigger, /* eio_trigger */
95 siena_intr_status_line, /* eio_status_line */
96 siena_intr_status_message, /* eio_status_message */
97 siena_intr_fatal, /* eio_fatal */
98 siena_intr_fini, /* eio_fini */
100 #endif /* EFSYS_OPT_SIENA */
102 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
103 static const efx_intr_ops_t __efx_intr_ef10_ops = {
104 ef10_intr_init, /* eio_init */
105 ef10_intr_enable, /* eio_enable */
106 ef10_intr_disable, /* eio_disable */
107 ef10_intr_disable_unlocked, /* eio_disable_unlocked */
108 ef10_intr_trigger, /* eio_trigger */
109 ef10_intr_status_line, /* eio_status_line */
110 ef10_intr_status_message, /* eio_status_message */
111 ef10_intr_fatal, /* eio_fatal */
112 ef10_intr_fini, /* eio_fini */
114 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
116 __checkReturn efx_rc_t
119 __in efx_intr_type_t type,
120 __in efsys_mem_t *esmp)
122 efx_intr_t *eip = &(enp->en_intr);
123 const efx_intr_ops_t *eiop;
126 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
127 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
129 if (enp->en_mod_flags & EFX_MOD_INTR) {
138 enp->en_mod_flags |= EFX_MOD_INTR;
140 switch (enp->en_family) {
142 case EFX_FAMILY_SIENA:
143 eiop = &__efx_intr_siena_ops;
145 #endif /* EFSYS_OPT_SIENA */
147 #if EFSYS_OPT_HUNTINGTON
148 case EFX_FAMILY_HUNTINGTON:
149 eiop = &__efx_intr_ef10_ops;
151 #endif /* EFSYS_OPT_HUNTINGTON */
153 #if EFSYS_OPT_MEDFORD
154 case EFX_FAMILY_MEDFORD:
155 eiop = &__efx_intr_ef10_ops;
157 #endif /* EFSYS_OPT_MEDFORD */
160 EFSYS_ASSERT(B_FALSE);
165 if ((rc = eiop->eio_init(enp, type, esmp)) != 0)
177 EFSYS_PROBE1(fail1, efx_rc_t, rc);
186 efx_intr_t *eip = &(enp->en_intr);
187 const efx_intr_ops_t *eiop = eip->ei_eiop;
189 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
190 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
191 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
195 enp->en_mod_flags &= ~EFX_MOD_INTR;
202 efx_intr_t *eip = &(enp->en_intr);
203 const efx_intr_ops_t *eiop = eip->ei_eiop;
205 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
206 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
208 eiop->eio_enable(enp);
215 efx_intr_t *eip = &(enp->en_intr);
216 const efx_intr_ops_t *eiop = eip->ei_eiop;
218 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
219 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
221 eiop->eio_disable(enp);
225 efx_intr_disable_unlocked(
228 efx_intr_t *eip = &(enp->en_intr);
229 const efx_intr_ops_t *eiop = eip->ei_eiop;
231 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
232 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
234 eiop->eio_disable_unlocked(enp);
238 __checkReturn efx_rc_t
241 __in unsigned int level)
243 efx_intr_t *eip = &(enp->en_intr);
244 const efx_intr_ops_t *eiop = eip->ei_eiop;
246 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
247 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
249 return (eiop->eio_trigger(enp, level));
253 efx_intr_status_line(
255 __out boolean_t *fatalp,
256 __out uint32_t *qmaskp)
258 efx_intr_t *eip = &(enp->en_intr);
259 const efx_intr_ops_t *eiop = eip->ei_eiop;
261 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
262 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
264 eiop->eio_status_line(enp, fatalp, qmaskp);
268 efx_intr_status_message(
270 __in unsigned int message,
271 __out boolean_t *fatalp)
273 efx_intr_t *eip = &(enp->en_intr);
274 const efx_intr_ops_t *eiop = eip->ei_eiop;
276 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
277 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
279 eiop->eio_status_message(enp, message, fatalp);
286 efx_intr_t *eip = &(enp->en_intr);
287 const efx_intr_ops_t *eiop = eip->ei_eiop;
289 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
290 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
292 eiop->eio_fatal(enp);
296 /* ************************************************************************* */
297 /* ************************************************************************* */
298 /* ************************************************************************* */
302 static __checkReturn efx_rc_t
305 __in efx_intr_type_t type,
306 __in efsys_mem_t *esmp)
308 efx_intr_t *eip = &(enp->en_intr);
312 * bug17213 workaround.
314 * Under legacy interrupts, don't share a level between fatal
315 * interrupts and event queue interrupts. Under MSI-X, they
316 * must share, or we won't get an interrupt.
318 if (enp->en_family == EFX_FAMILY_SIENA &&
319 eip->ei_type == EFX_INTR_LINE)
320 eip->ei_level = 0x1f;
324 /* Enable all the genuinely fatal interrupts */
325 EFX_SET_OWORD(oword);
326 EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0);
327 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0);
328 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0);
329 if (enp->en_family >= EFX_FAMILY_SIENA)
330 EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0);
331 EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword);
333 /* Set up the interrupt address register */
334 EFX_POPULATE_OWORD_3(oword,
335 FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0,
336 FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff,
337 FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32);
338 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
347 efx_intr_t *eip = &(enp->en_intr);
350 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
352 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
353 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1);
354 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
363 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
364 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
365 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
371 siena_intr_disable_unlocked(
376 EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
378 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
379 EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
383 static __checkReturn efx_rc_t
386 __in unsigned int level)
388 efx_intr_t *eip = &(enp->en_intr);
394 /* bug16757: No event queues can be initialized */
395 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
397 if (level >= EFX_NINTR_SIENA) {
402 if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL))
403 return (ENOTSUP); /* avoid EFSYS_PROBE() */
407 /* Trigger a test interrupt */
408 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
409 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel);
410 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1);
411 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
414 * Wait up to 100ms for the interrupt to be raised before restoring
415 * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will
416 * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL
420 EFSYS_SPIN(100); /* 100us */
422 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
423 } while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000);
425 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
426 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
431 EFSYS_PROBE1(fail1, efx_rc_t, rc);
436 static __checkReturn boolean_t
437 siena_intr_check_fatal(
440 efx_intr_t *eip = &(enp->en_intr);
441 efsys_mem_t *esmp = eip->ei_esmp;
444 /* Read the syndrome */
445 EFSYS_MEM_READO(esmp, 0, &oword);
447 if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) {
450 /* Clear the fatal interrupt condition */
451 EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0);
452 EFSYS_MEM_WRITEO(esmp, 0, &oword);
461 siena_intr_status_line(
463 __out boolean_t *fatalp,
464 __out uint32_t *qmaskp)
466 efx_intr_t *eip = &(enp->en_intr);
469 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
470 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
473 * Read the queue mask and implicitly acknowledge the
476 EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
477 *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
479 EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
481 if (*qmaskp & (1U << eip->ei_level))
482 *fatalp = siena_intr_check_fatal(enp);
488 siena_intr_status_message(
490 __in unsigned int message,
491 __out boolean_t *fatalp)
493 efx_intr_t *eip = &(enp->en_intr);
495 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
496 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
498 if (message == eip->ei_level)
499 *fatalp = siena_intr_check_fatal(enp);
509 #if EFSYS_OPT_DECODE_INTR_FATAL
513 EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal);
514 EFX_ZERO_OWORD(mem_per);
516 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 ||
517 EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
518 EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per);
520 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0)
521 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0);
523 if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0)
524 EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0);
526 if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
527 EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR,
528 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
529 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
531 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0)
532 EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0);
534 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0)
535 EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0);
537 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0)
538 EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0);
540 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0)
541 EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0);
543 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0)
544 EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0);
546 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0)
547 EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0);
549 if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0)
550 EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0);
552 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0)
553 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR,
554 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
555 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
567 /* Clear the interrupt address register */
568 EFX_ZERO_OWORD(oword);
569 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
572 #endif /* EFSYS_OPT_SIENA */