2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
34 __checkReturn efx_rc_t
38 __out efx_family_t *efp)
40 if (venid == EFX_PCI_VENID_SFC) {
43 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
45 * Hardware default for PF0 of uninitialised Siena.
46 * manftest must be able to cope with this device id.
48 *efp = EFX_FAMILY_SIENA;
51 case EFX_PCI_DEVID_BETHPAGE:
52 case EFX_PCI_DEVID_SIENA:
53 *efp = EFX_FAMILY_SIENA;
55 #endif /* EFSYS_OPT_SIENA */
57 #if EFSYS_OPT_HUNTINGTON
58 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
60 * Hardware default for PF0 of uninitialised Huntington.
61 * manftest must be able to cope with this device id.
63 *efp = EFX_FAMILY_HUNTINGTON;
66 case EFX_PCI_DEVID_FARMINGDALE:
67 case EFX_PCI_DEVID_GREENPORT:
68 *efp = EFX_FAMILY_HUNTINGTON;
71 case EFX_PCI_DEVID_FARMINGDALE_VF:
72 case EFX_PCI_DEVID_GREENPORT_VF:
73 *efp = EFX_FAMILY_HUNTINGTON;
75 #endif /* EFSYS_OPT_HUNTINGTON */
78 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
80 * Hardware default for PF0 of uninitialised Medford.
81 * manftest must be able to cope with this device id.
83 *efp = EFX_FAMILY_MEDFORD;
86 case EFX_PCI_DEVID_MEDFORD:
87 *efp = EFX_FAMILY_MEDFORD;
90 case EFX_PCI_DEVID_MEDFORD_VF:
91 *efp = EFX_FAMILY_MEDFORD;
93 #endif /* EFSYS_OPT_MEDFORD */
95 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
101 *efp = EFX_FAMILY_INVALID;
106 #define EFX_BIU_MAGIC0 0x01234567
107 #define EFX_BIU_MAGIC1 0xfedcba98
109 __checkReturn efx_rc_t
117 * Write magic values to scratch registers 0 and 1, then
118 * verify that the values were written correctly. Interleave
119 * the accesses to ensure that the BIU is not just reading
120 * back the cached value that was last written.
122 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
123 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
125 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
126 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
128 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
129 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
134 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
135 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
141 * Perform the same test, with the values swapped. This
142 * ensures that subsequent tests don't start with the correct
143 * values already written into the scratch registers.
145 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
146 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
148 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
149 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
151 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
152 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
157 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
158 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
172 EFSYS_PROBE1(fail1, efx_rc_t, rc);
179 static const efx_nic_ops_t __efx_nic_siena_ops = {
180 siena_nic_probe, /* eno_probe */
181 NULL, /* eno_board_cfg */
182 NULL, /* eno_set_drv_limits */
183 siena_nic_reset, /* eno_reset */
184 siena_nic_init, /* eno_init */
185 NULL, /* eno_get_vi_pool */
186 NULL, /* eno_get_bar_region */
188 siena_nic_register_test, /* eno_register_test */
189 #endif /* EFSYS_OPT_DIAG */
190 siena_nic_fini, /* eno_fini */
191 siena_nic_unprobe, /* eno_unprobe */
194 #endif /* EFSYS_OPT_SIENA */
196 #if EFSYS_OPT_HUNTINGTON
198 static const efx_nic_ops_t __efx_nic_hunt_ops = {
199 ef10_nic_probe, /* eno_probe */
200 hunt_board_cfg, /* eno_board_cfg */
201 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
202 ef10_nic_reset, /* eno_reset */
203 ef10_nic_init, /* eno_init */
204 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
205 ef10_nic_get_bar_region, /* eno_get_bar_region */
207 ef10_nic_register_test, /* eno_register_test */
208 #endif /* EFSYS_OPT_DIAG */
209 ef10_nic_fini, /* eno_fini */
210 ef10_nic_unprobe, /* eno_unprobe */
213 #endif /* EFSYS_OPT_HUNTINGTON */
215 #if EFSYS_OPT_MEDFORD
217 static const efx_nic_ops_t __efx_nic_medford_ops = {
218 ef10_nic_probe, /* eno_probe */
219 medford_board_cfg, /* eno_board_cfg */
220 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
221 ef10_nic_reset, /* eno_reset */
222 ef10_nic_init, /* eno_init */
223 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
224 ef10_nic_get_bar_region, /* eno_get_bar_region */
226 ef10_nic_register_test, /* eno_register_test */
227 #endif /* EFSYS_OPT_DIAG */
228 ef10_nic_fini, /* eno_fini */
229 ef10_nic_unprobe, /* eno_unprobe */
232 #endif /* EFSYS_OPT_MEDFORD */
235 __checkReturn efx_rc_t
237 __in efx_family_t family,
238 __in efsys_identifier_t *esip,
239 __in efsys_bar_t *esbp,
240 __in efsys_lock_t *eslp,
241 __deref_out efx_nic_t **enpp)
246 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
247 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
249 /* Allocate a NIC object */
250 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
257 enp->en_magic = EFX_NIC_MAGIC;
261 case EFX_FAMILY_SIENA:
262 enp->en_enop = &__efx_nic_siena_ops;
265 EFX_FEATURE_LFSR_HASH_INSERT |
266 EFX_FEATURE_LINK_EVENTS |
267 EFX_FEATURE_PERIODIC_MAC_STATS |
269 EFX_FEATURE_LOOKAHEAD_SPLIT |
270 EFX_FEATURE_MAC_HEADER_FILTERS |
271 EFX_FEATURE_TX_SRC_FILTERS;
273 #endif /* EFSYS_OPT_SIENA */
275 #if EFSYS_OPT_HUNTINGTON
276 case EFX_FAMILY_HUNTINGTON:
277 enp->en_enop = &__efx_nic_hunt_ops;
280 EFX_FEATURE_LINK_EVENTS |
281 EFX_FEATURE_PERIODIC_MAC_STATS |
283 EFX_FEATURE_MAC_HEADER_FILTERS |
284 EFX_FEATURE_MCDI_DMA |
285 EFX_FEATURE_PIO_BUFFERS |
286 EFX_FEATURE_FW_ASSISTED_TSO |
287 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
288 EFX_FEATURE_PACKED_STREAM;
290 #endif /* EFSYS_OPT_HUNTINGTON */
292 #if EFSYS_OPT_MEDFORD
293 case EFX_FAMILY_MEDFORD:
294 enp->en_enop = &__efx_nic_medford_ops;
296 * FW_ASSISTED_TSO omitted as Medford only supports firmware
297 * assisted TSO version 2, not the v1 scheme used on Huntington.
301 EFX_FEATURE_LINK_EVENTS |
302 EFX_FEATURE_PERIODIC_MAC_STATS |
304 EFX_FEATURE_MAC_HEADER_FILTERS |
305 EFX_FEATURE_MCDI_DMA |
306 EFX_FEATURE_PIO_BUFFERS |
307 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
308 EFX_FEATURE_PACKED_STREAM;
310 #endif /* EFSYS_OPT_MEDFORD */
317 enp->en_family = family;
331 /* Free the NIC object */
332 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
335 EFSYS_PROBE1(fail1, efx_rc_t, rc);
340 __checkReturn efx_rc_t
344 const efx_nic_ops_t *enop;
347 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
349 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
350 #endif /* EFSYS_OPT_MCDI */
351 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
354 if ((rc = enop->eno_probe(enp)) != 0)
357 if ((rc = efx_phy_probe(enp)) != 0)
360 enp->en_mod_flags |= EFX_MOD_PROBE;
367 enop->eno_unprobe(enp);
370 EFSYS_PROBE1(fail1, efx_rc_t, rc);
375 __checkReturn efx_rc_t
376 efx_nic_set_drv_limits(
377 __inout efx_nic_t *enp,
378 __in efx_drv_limits_t *edlp)
380 const efx_nic_ops_t *enop = enp->en_enop;
383 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
384 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
386 if (enop->eno_set_drv_limits != NULL) {
387 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
394 EFSYS_PROBE1(fail1, efx_rc_t, rc);
399 __checkReturn efx_rc_t
400 efx_nic_get_bar_region(
402 __in efx_nic_region_t region,
403 __out uint32_t *offsetp,
406 const efx_nic_ops_t *enop = enp->en_enop;
409 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
410 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
411 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
413 if (enop->eno_get_bar_region == NULL) {
417 if ((rc = (enop->eno_get_bar_region)(enp,
418 region, offsetp, sizep)) != 0) {
428 EFSYS_PROBE1(fail1, efx_rc_t, rc);
434 __checkReturn efx_rc_t
437 __out uint32_t *evq_countp,
438 __out uint32_t *rxq_countp,
439 __out uint32_t *txq_countp)
441 const efx_nic_ops_t *enop = enp->en_enop;
442 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
445 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
446 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
447 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
449 if (enop->eno_get_vi_pool != NULL) {
450 uint32_t vi_count = 0;
452 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
455 *evq_countp = vi_count;
456 *rxq_countp = vi_count;
457 *txq_countp = vi_count;
459 /* Use NIC limits as default value */
460 *evq_countp = encp->enc_evq_limit;
461 *rxq_countp = encp->enc_rxq_limit;
462 *txq_countp = encp->enc_txq_limit;
468 EFSYS_PROBE1(fail1, efx_rc_t, rc);
474 __checkReturn efx_rc_t
478 const efx_nic_ops_t *enop = enp->en_enop;
481 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
482 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
484 if (enp->en_mod_flags & EFX_MOD_NIC) {
489 if ((rc = enop->eno_init(enp)) != 0)
492 enp->en_mod_flags |= EFX_MOD_NIC;
499 EFSYS_PROBE1(fail1, efx_rc_t, rc);
508 const efx_nic_ops_t *enop = enp->en_enop;
510 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
511 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
512 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
513 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
514 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
515 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
516 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
520 enp->en_mod_flags &= ~EFX_MOD_NIC;
527 const efx_nic_ops_t *enop = enp->en_enop;
529 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
531 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
532 #endif /* EFSYS_OPT_MCDI */
533 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
534 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
535 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
536 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
537 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
538 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
540 efx_phy_unprobe(enp);
542 enop->eno_unprobe(enp);
544 enp->en_mod_flags &= ~EFX_MOD_PROBE;
551 efsys_identifier_t *esip = enp->en_esip;
553 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
554 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
556 enp->en_family = EFX_FAMILY_INVALID;
565 /* Free the NIC object */
566 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
569 __checkReturn efx_rc_t
573 const efx_nic_ops_t *enop = enp->en_enop;
574 unsigned int mod_flags;
577 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
578 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
580 * All modules except the MCDI, PROBE, NVRAM, VPD, MON
581 * (which we do not reset here) must have been shut down or never
584 * A rule of thumb here is: If the controller or MC reboots, is *any*
585 * state lost. If it's lost and needs reapplying, then the module
586 * *must* not be initialised during the reset.
588 mod_flags = enp->en_mod_flags;
589 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
590 EFX_MOD_VPD | EFX_MOD_MON);
591 EFSYS_ASSERT3U(mod_flags, ==, 0);
592 if (mod_flags != 0) {
597 if ((rc = enop->eno_reset(enp)) != 0)
605 EFSYS_PROBE1(fail1, efx_rc_t, rc);
610 const efx_nic_cfg_t *
614 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
616 return (&(enp->en_nic_cfg));
621 __checkReturn efx_rc_t
622 efx_nic_register_test(
625 const efx_nic_ops_t *enop = enp->en_enop;
628 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
629 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
630 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
632 if ((rc = enop->eno_register_test(enp)) != 0)
638 EFSYS_PROBE1(fail1, efx_rc_t, rc);
643 __checkReturn efx_rc_t
644 efx_nic_test_registers(
646 __in efx_register_set_t *rsp,
650 efx_oword_t original;
656 /* This function is only suitable for registers */
657 EFSYS_ASSERT(rsp->rows == 1);
659 /* bit sweep on and off */
660 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
662 for (bit = 0; bit < 128; bit++) {
663 /* Is this bit in the mask? */
664 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
667 /* Test this bit can be set in isolation */
669 EFX_AND_OWORD(reg, rsp->mask);
670 EFX_SET_OWORD_BIT(reg, bit);
672 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
674 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
677 EFX_AND_OWORD(buf, rsp->mask);
678 if (memcmp(®, &buf, sizeof (reg))) {
683 /* Test this bit can be cleared in isolation */
684 EFX_OR_OWORD(reg, rsp->mask);
685 EFX_CLEAR_OWORD_BIT(reg, bit);
687 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
689 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
692 EFX_AND_OWORD(buf, rsp->mask);
693 if (memcmp(®, &buf, sizeof (reg))) {
699 /* Restore the old value */
700 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
712 EFSYS_PROBE1(fail1, efx_rc_t, rc);
714 /* Restore the old value */
715 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
720 __checkReturn efx_rc_t
723 __in efx_register_set_t *rsp,
724 __in efx_pattern_type_t pattern,
727 efx_sram_pattern_fn_t func;
729 unsigned int address;
734 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
735 func = __efx_sram_pattern_fns[pattern];
739 address = rsp->address;
740 for (index = 0; index < rsp->rows; ++index) {
741 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
742 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
743 EFX_AND_OWORD(reg, rsp->mask);
744 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
746 address += rsp->step;
750 address = rsp->address;
751 for (index = 0; index < rsp->rows; ++index) {
752 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
753 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
754 EFX_AND_OWORD(reg, rsp->mask);
755 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
756 if (memcmp(®, &buf, sizeof (reg))) {
761 address += rsp->step;
771 EFSYS_PROBE1(fail1, efx_rc_t, rc);
776 #endif /* EFSYS_OPT_DIAG */
778 __checkReturn efx_rc_t
779 efx_nic_calculate_pcie_link_bandwidth(
780 __in uint32_t pcie_link_width,
781 __in uint32_t pcie_link_gen,
782 __out uint32_t *bandwidth_mbpsp)
784 uint32_t lane_bandwidth;
785 uint32_t total_bandwidth;
788 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
789 !ISP2(pcie_link_width)) {
794 switch (pcie_link_gen) {
795 case EFX_PCIE_LINK_SPEED_GEN1:
796 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
797 lane_bandwidth = 2000;
799 case EFX_PCIE_LINK_SPEED_GEN2:
800 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
801 lane_bandwidth = 4000;
803 case EFX_PCIE_LINK_SPEED_GEN3:
804 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
805 lane_bandwidth = 7877;
812 total_bandwidth = lane_bandwidth * pcie_link_width;
813 *bandwidth_mbpsp = total_bandwidth;
820 EFSYS_PROBE1(fail1, efx_rc_t, rc);
826 __checkReturn efx_rc_t
827 efx_nic_check_pcie_link_speed(
829 __in uint32_t pcie_link_width,
830 __in uint32_t pcie_link_gen,
831 __out efx_pcie_link_performance_t *resultp)
833 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
835 efx_pcie_link_performance_t result;
838 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
839 (pcie_link_width == 0) || (pcie_link_width == 32) ||
840 (pcie_link_gen == 0)) {
842 * No usable info on what is required and/or in use. In virtual
843 * machines, sometimes the PCIe link width is reported as 0 or
844 * 32, or the speed as 0.
846 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
850 /* Calculate the available bandwidth in megabits per second */
851 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
852 pcie_link_gen, &bandwidth);
856 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
857 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
858 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
859 /* The link provides enough bandwidth but not optimal latency */
860 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
862 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
871 EFSYS_PROBE1(fail1, efx_rc_t, rc);