drivers/net/sfc/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         *efp = EFX_FAMILY_INVALID;
  89         return (ENOTSUP);
  90 }
  91
  92
  93 #if EFSYS_OPT_SIENA
  94
  95 static const efx_nic_ops_t      __efx_nic_siena_ops = {
  96         siena_nic_probe,                /* eno_probe */
  97         NULL,                           /* eno_board_cfg */
  98         NULL,                           /* eno_set_drv_limits */
  99         siena_nic_reset,                /* eno_reset */
 100         siena_nic_init,                 /* eno_init */
 101         NULL,                           /* eno_get_vi_pool */
 102         NULL,                           /* eno_get_bar_region */
 103 #if EFSYS_OPT_DIAG
 104         siena_nic_register_test,        /* eno_register_test */
 105 #endif  /* EFSYS_OPT_DIAG */
 106         siena_nic_fini,                 /* eno_fini */
 107         siena_nic_unprobe,              /* eno_unprobe */
 108 };
 109
 110 #endif  /* EFSYS_OPT_SIENA */
 111
 112 #if EFSYS_OPT_HUNTINGTON
 113
 114 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 115         ef10_nic_probe,                 /* eno_probe */
 116         hunt_board_cfg,                 /* eno_board_cfg */
 117         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 118         ef10_nic_reset,                 /* eno_reset */
 119         ef10_nic_init,                  /* eno_init */
 120         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 121         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 122 #if EFSYS_OPT_DIAG
 123         ef10_nic_register_test,         /* eno_register_test */
 124 #endif  /* EFSYS_OPT_DIAG */
 125         ef10_nic_fini,                  /* eno_fini */
 126         ef10_nic_unprobe,               /* eno_unprobe */
 127 };
 128
 129 #endif  /* EFSYS_OPT_HUNTINGTON */
 130
 131 #if EFSYS_OPT_MEDFORD
 132
 133 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 134         ef10_nic_probe,                 /* eno_probe */
 135         medford_board_cfg,              /* eno_board_cfg */
 136         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 137         ef10_nic_reset,                 /* eno_reset */
 138         ef10_nic_init,                  /* eno_init */
 139         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 140         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 141 #if EFSYS_OPT_DIAG
 142         ef10_nic_register_test,         /* eno_register_test */
 143 #endif  /* EFSYS_OPT_DIAG */
 144         ef10_nic_fini,                  /* eno_fini */
 145         ef10_nic_unprobe,               /* eno_unprobe */
 146 };
 147
 148 #endif  /* EFSYS_OPT_MEDFORD */
 149
 150 #if EFSYS_OPT_MEDFORD2
 151
 152 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 153         ef10_nic_probe,                 /* eno_probe */
 154         medford2_board_cfg,             /* eno_board_cfg */
 155         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 156         ef10_nic_reset,                 /* eno_reset */
 157         ef10_nic_init,                  /* eno_init */
 158         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 159         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 160 #if EFSYS_OPT_DIAG
 161         ef10_nic_register_test,         /* eno_register_test */
 162 #endif  /* EFSYS_OPT_DIAG */
 163         ef10_nic_fini,                  /* eno_fini */
 164         ef10_nic_unprobe,               /* eno_unprobe */
 165 };
 166
 167 #endif  /* EFSYS_OPT_MEDFORD2 */
 168
 169
 170         __checkReturn   efx_rc_t
 171 efx_nic_create(
 172         __in            efx_family_t family,
 173         __in            efsys_identifier_t *esip,
 174         __in            efsys_bar_t *esbp,
 175         __in            efsys_lock_t *eslp,
 176         __deref_out     efx_nic_t **enpp)
 177 {
 178         efx_nic_t *enp;
 179         efx_rc_t rc;
 180
 181         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 182         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 183
 184         /* Allocate a NIC object */
 185         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 186
 187         if (enp == NULL) {
 188                 rc = ENOMEM;
 189                 goto fail1;
 190         }
 191
 192         enp->en_magic = EFX_NIC_MAGIC;
 193
 194         switch (family) {
 195 #if EFSYS_OPT_SIENA
 196         case EFX_FAMILY_SIENA:
 197                 enp->en_enop = &__efx_nic_siena_ops;
 198                 enp->en_features =
 199                     EFX_FEATURE_IPV6 |
 200                     EFX_FEATURE_LFSR_HASH_INSERT |
 201                     EFX_FEATURE_LINK_EVENTS |
 202                     EFX_FEATURE_PERIODIC_MAC_STATS |
 203                     EFX_FEATURE_MCDI |
 204                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 205                     EFX_FEATURE_MAC_HEADER_FILTERS |
 206                     EFX_FEATURE_TX_SRC_FILTERS;
 207                 break;
 208 #endif  /* EFSYS_OPT_SIENA */
 209
 210 #if EFSYS_OPT_HUNTINGTON
 211         case EFX_FAMILY_HUNTINGTON:
 212                 enp->en_enop = &__efx_nic_hunt_ops;
 213                 enp->en_features =
 214                     EFX_FEATURE_IPV6 |
 215                     EFX_FEATURE_LINK_EVENTS |
 216                     EFX_FEATURE_PERIODIC_MAC_STATS |
 217                     EFX_FEATURE_MCDI |
 218                     EFX_FEATURE_MAC_HEADER_FILTERS |
 219                     EFX_FEATURE_MCDI_DMA |
 220                     EFX_FEATURE_PIO_BUFFERS |
 221                     EFX_FEATURE_FW_ASSISTED_TSO |
 222                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 223                     EFX_FEATURE_PACKED_STREAM;
 224                 break;
 225 #endif  /* EFSYS_OPT_HUNTINGTON */
 226
 227 #if EFSYS_OPT_MEDFORD
 228         case EFX_FAMILY_MEDFORD:
 229                 enp->en_enop = &__efx_nic_medford_ops;
 230                 /*
 231                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 232                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 233                  */
 234                 enp->en_features =
 235                     EFX_FEATURE_IPV6 |
 236                     EFX_FEATURE_LINK_EVENTS |
 237                     EFX_FEATURE_PERIODIC_MAC_STATS |
 238                     EFX_FEATURE_MCDI |
 239                     EFX_FEATURE_MAC_HEADER_FILTERS |
 240                     EFX_FEATURE_MCDI_DMA |
 241                     EFX_FEATURE_PIO_BUFFERS |
 242                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 243                     EFX_FEATURE_PACKED_STREAM;
 244                 break;
 245 #endif  /* EFSYS_OPT_MEDFORD */
 246
 247 #if EFSYS_OPT_MEDFORD2
 248         case EFX_FAMILY_MEDFORD2:
 249                 enp->en_enop = &__efx_nic_medford2_ops;
 250                 enp->en_features =
 251                     EFX_FEATURE_IPV6 |
 252                     EFX_FEATURE_LINK_EVENTS |
 253                     EFX_FEATURE_PERIODIC_MAC_STATS |
 254                     EFX_FEATURE_MCDI |
 255                     EFX_FEATURE_MAC_HEADER_FILTERS |
 256                     EFX_FEATURE_MCDI_DMA |
 257                     EFX_FEATURE_PIO_BUFFERS |
 258                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 259                     EFX_FEATURE_PACKED_STREAM;
 260                 break;
 261 #endif  /* EFSYS_OPT_MEDFORD2 */
 262
 263         default:
 264                 rc = ENOTSUP;
 265                 goto fail2;
 266         }
 267
 268         enp->en_family = family;
 269         enp->en_esip = esip;
 270         enp->en_esbp = esbp;
 271         enp->en_eslp = eslp;
 272
 273         *enpp = enp;
 274
 275         return (0);
 276
 277 fail2:
 278         EFSYS_PROBE(fail2);
 279
 280         enp->en_magic = 0;
 281
 282         /* Free the NIC object */
 283         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 284
 285 fail1:
 286         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 287
 288         return (rc);
 289 }
 290
 291         __checkReturn   efx_rc_t
 292 efx_nic_probe(
 293         __in            efx_nic_t *enp,
 294         __in            efx_fw_variant_t efv)
 295 {
 296         const efx_nic_ops_t *enop;
 297         efx_rc_t rc;
 298
 299         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 300 #if EFSYS_OPT_MCDI
 301         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 302 #endif  /* EFSYS_OPT_MCDI */
 303         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 304
 305         /* Ensure FW variant codes match with MC_CMD_FW codes */
 306         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 307             MC_CMD_FW_FULL_FEATURED);
 308         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 309             MC_CMD_FW_LOW_LATENCY);
 310         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 311             MC_CMD_FW_PACKED_STREAM);
 312         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 313             MC_CMD_FW_HIGH_TX_RATE);
 314         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 315             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 316         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 317             MC_CMD_FW_RULES_ENGINE);
 318         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 319             MC_CMD_FW_DPDK);
 320         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 321             (int)MC_CMD_FW_DONT_CARE);
 322
 323         enop = enp->en_enop;
 324         enp->efv = efv;
 325
 326         if ((rc = enop->eno_probe(enp)) != 0)
 327                 goto fail1;
 328
 329         if ((rc = efx_phy_probe(enp)) != 0)
 330                 goto fail2;
 331
 332         enp->en_mod_flags |= EFX_MOD_PROBE;
 333
 334         return (0);
 335
 336 fail2:
 337         EFSYS_PROBE(fail2);
 338
 339         enop->eno_unprobe(enp);
 340
 341 fail1:
 342         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 343
 344         return (rc);
 345 }
 346
 347         __checkReturn   efx_rc_t
 348 efx_nic_set_drv_limits(
 349         __inout         efx_nic_t *enp,
 350         __in            efx_drv_limits_t *edlp)
 351 {
 352         const efx_nic_ops_t *enop = enp->en_enop;
 353         efx_rc_t rc;
 354
 355         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 356         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 357
 358         if (enop->eno_set_drv_limits != NULL) {
 359                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 360                         goto fail1;
 361         }
 362
 363         return (0);
 364
 365 fail1:
 366         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 367
 368         return (rc);
 369 }
 370
 371         __checkReturn   efx_rc_t
 372 efx_nic_get_bar_region(
 373         __in            efx_nic_t *enp,
 374         __in            efx_nic_region_t region,
 375         __out           uint32_t *offsetp,
 376         __out           size_t *sizep)
 377 {
 378         const efx_nic_ops_t *enop = enp->en_enop;
 379         efx_rc_t rc;
 380
 381         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 382         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 383         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 384
 385         if (enop->eno_get_bar_region == NULL) {
 386                 rc = ENOTSUP;
 387                 goto fail1;
 388         }
 389         if ((rc = (enop->eno_get_bar_region)(enp,
 390                     region, offsetp, sizep)) != 0) {
 391                 goto fail2;
 392         }
 393
 394         return (0);
 395
 396 fail2:
 397         EFSYS_PROBE(fail2);
 398
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401
 402         return (rc);
 403 }
 404
 405
 406         __checkReturn   efx_rc_t
 407 efx_nic_get_vi_pool(
 408         __in            efx_nic_t *enp,
 409         __out           uint32_t *evq_countp,
 410         __out           uint32_t *rxq_countp,
 411         __out           uint32_t *txq_countp)
 412 {
 413         const efx_nic_ops_t *enop = enp->en_enop;
 414         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 415         efx_rc_t rc;
 416
 417         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 418         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 419         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 420
 421         if (enop->eno_get_vi_pool != NULL) {
 422                 uint32_t vi_count = 0;
 423
 424                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 425                         goto fail1;
 426
 427                 *evq_countp = vi_count;
 428                 *rxq_countp = vi_count;
 429                 *txq_countp = vi_count;
 430         } else {
 431                 /* Use NIC limits as default value */
 432                 *evq_countp = encp->enc_evq_limit;
 433                 *rxq_countp = encp->enc_rxq_limit;
 434                 *txq_countp = encp->enc_txq_limit;
 435         }
 436
 437         return (0);
 438
 439 fail1:
 440         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 441
 442         return (rc);
 443 }
 444
 445
 446         __checkReturn   efx_rc_t
 447 efx_nic_init(
 448         __in            efx_nic_t *enp)
 449 {
 450         const efx_nic_ops_t *enop = enp->en_enop;
 451         efx_rc_t rc;
 452
 453         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 454         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 455
 456         if (enp->en_mod_flags & EFX_MOD_NIC) {
 457                 rc = EINVAL;
 458                 goto fail1;
 459         }
 460
 461         if ((rc = enop->eno_init(enp)) != 0)
 462                 goto fail2;
 463
 464         enp->en_mod_flags |= EFX_MOD_NIC;
 465
 466         return (0);
 467
 468 fail2:
 469         EFSYS_PROBE(fail2);
 470 fail1:
 471         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 472
 473         return (rc);
 474 }
 475
 476                         void
 477 efx_nic_fini(
 478         __in            efx_nic_t *enp)
 479 {
 480         const efx_nic_ops_t *enop = enp->en_enop;
 481
 482         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 483         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 484         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 485         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 486         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 487         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 488         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 489
 490         enop->eno_fini(enp);
 491
 492         enp->en_mod_flags &= ~EFX_MOD_NIC;
 493 }
 494
 495                         void
 496 efx_nic_unprobe(
 497         __in            efx_nic_t *enp)
 498 {
 499         const efx_nic_ops_t *enop = enp->en_enop;
 500
 501         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 502 #if EFSYS_OPT_MCDI
 503         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 504 #endif  /* EFSYS_OPT_MCDI */
 505         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 506         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 507         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 508         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 509         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 510         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 511
 512         efx_phy_unprobe(enp);
 513
 514         enop->eno_unprobe(enp);
 515
 516         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 517 }
 518
 519                         void
 520 efx_nic_destroy(
 521         __in    efx_nic_t *enp)
 522 {
 523         efsys_identifier_t *esip = enp->en_esip;
 524
 525         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 526         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 527
 528         enp->en_family = EFX_FAMILY_INVALID;
 529         enp->en_esip = NULL;
 530         enp->en_esbp = NULL;
 531         enp->en_eslp = NULL;
 532
 533         enp->en_enop = NULL;
 534
 535         enp->en_magic = 0;
 536
 537         /* Free the NIC object */
 538         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 539 }
 540
 541         __checkReturn   efx_rc_t
 542 efx_nic_reset(
 543         __in            efx_nic_t *enp)
 544 {
 545         const efx_nic_ops_t *enop = enp->en_enop;
 546         unsigned int mod_flags;
 547         efx_rc_t rc;
 548
 549         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 550         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 551         /*
 552          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 553          * (which we do not reset here) must have been shut down or never
 554          * initialized.
 555          *
 556          * A rule of thumb here is: If the controller or MC reboots, is *any*
 557          * state lost. If it's lost and needs reapplying, then the module
 558          * *must* not be initialised during the reset.
 559          */
 560         mod_flags = enp->en_mod_flags;
 561         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 562             EFX_MOD_VPD | EFX_MOD_MON);
 563 #if EFSYS_OPT_TUNNEL
 564         mod_flags &= ~EFX_MOD_TUNNEL;
 565 #endif /* EFSYS_OPT_TUNNEL */
 566         EFSYS_ASSERT3U(mod_flags, ==, 0);
 567         if (mod_flags != 0) {
 568                 rc = EINVAL;
 569                 goto fail1;
 570         }
 571
 572         if ((rc = enop->eno_reset(enp)) != 0)
 573                 goto fail2;
 574
 575         return (0);
 576
 577 fail2:
 578         EFSYS_PROBE(fail2);
 579 fail1:
 580         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 581
 582         return (rc);
 583 }
 584
 585                         const efx_nic_cfg_t *
 586 efx_nic_cfg_get(
 587         __in            efx_nic_t *enp)
 588 {
 589         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 590
 591         return (&(enp->en_nic_cfg));
 592 }
 593
 594         __checkReturn           efx_rc_t
 595 efx_nic_get_fw_version(
 596         __in                    efx_nic_t *enp,
 597         __out                   efx_nic_fw_info_t *enfip)
 598 {
 599         uint16_t mc_fw_version[4];
 600         efx_rc_t rc;
 601
 602         if (enfip == NULL) {
 603                 rc = EINVAL;
 604                 goto fail1;
 605         }
 606
 607         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 608         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 609
 610         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 611         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 612             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 613         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 614             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 615         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 616             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 617         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 618             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 619         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 620             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 621
 622         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 623         if (rc != 0)
 624                 goto fail2;
 625
 626         rc = efx_mcdi_get_capabilities(enp, NULL,
 627             &enfip->enfi_rx_dpcpu_fw_id,
 628             &enfip->enfi_tx_dpcpu_fw_id,
 629             NULL, NULL);
 630         if (rc == 0) {
 631                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 632         } else if (rc == ENOTSUP) {
 633                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 634                 enfip->enfi_rx_dpcpu_fw_id = 0;
 635                 enfip->enfi_tx_dpcpu_fw_id = 0;
 636         } else {
 637                 goto fail3;
 638         }
 639
 640         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 641             sizeof (mc_fw_version));
 642
 643         return (0);
 644
 645 fail3:
 646         EFSYS_PROBE(fail3);
 647 fail2:
 648         EFSYS_PROBE(fail2);
 649 fail1:
 650         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 651
 652         return (rc);
 653 }
 654
 655 #if EFSYS_OPT_DIAG
 656
 657         __checkReturn   efx_rc_t
 658 efx_nic_register_test(
 659         __in            efx_nic_t *enp)
 660 {
 661         const efx_nic_ops_t *enop = enp->en_enop;
 662         efx_rc_t rc;
 663
 664         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 665         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 666         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 667
 668         if ((rc = enop->eno_register_test(enp)) != 0)
 669                 goto fail1;
 670
 671         return (0);
 672
 673 fail1:
 674         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 675
 676         return (rc);
 677 }
 678
 679 #endif  /* EFSYS_OPT_DIAG */
 680
 681 #if EFSYS_OPT_LOOPBACK
 682
 683 extern                  void
 684 efx_loopback_mask(
 685         __in    efx_loopback_kind_t loopback_kind,
 686         __out   efx_qword_t *maskp)
 687 {
 688         efx_qword_t mask;
 689
 690         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 691         EFSYS_ASSERT(maskp != NULL);
 692
 693         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 694 #define LOOPBACK_CHECK(_mcdi, _efx) \
 695         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 696
 697         LOOPBACK_CHECK(NONE, OFF);
 698         LOOPBACK_CHECK(DATA, DATA);
 699         LOOPBACK_CHECK(GMAC, GMAC);
 700         LOOPBACK_CHECK(XGMII, XGMII);
 701         LOOPBACK_CHECK(XGXS, XGXS);
 702         LOOPBACK_CHECK(XAUI, XAUI);
 703         LOOPBACK_CHECK(GMII, GMII);
 704         LOOPBACK_CHECK(SGMII, SGMII);
 705         LOOPBACK_CHECK(XGBR, XGBR);
 706         LOOPBACK_CHECK(XFI, XFI);
 707         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 708         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 709         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 710         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 711         LOOPBACK_CHECK(GPHY, GPHY);
 712         LOOPBACK_CHECK(PHYXS, PHY_XS);
 713         LOOPBACK_CHECK(PCS, PCS);
 714         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 715         LOOPBACK_CHECK(XPORT, XPORT);
 716         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 717         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 718         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 719         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 720         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 721         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 722         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 723         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 724         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 725         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 726         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 727         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 728         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 729         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 730         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 731         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 732         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 733         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 734         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 735 #undef LOOPBACK_CHECK
 736
 737         /* Build bitmask of possible loopback types */
 738         EFX_ZERO_QWORD(mask);
 739
 740         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 741             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 742                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 743         }
 744
 745         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 746             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 747                 /*
 748                  * The "MAC" grouping has historically been used by drivers to
 749                  * mean loopbacks supported by on-chip hardware. Keep that
 750                  * meaning here, and include on-chip PHY layer loopbacks.
 751                  */
 752                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 753                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 754                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 755                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 756                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 757                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 758                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 759                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 760                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 761                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 762                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 763                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 764                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 765                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 766                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 767                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 768         }
 769
 770         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 771             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 772                 /*
 773                  * The "PHY" grouping has historically been used by drivers to
 774                  * mean loopbacks supported by off-chip hardware. Keep that
 775                  * meaning here.
 776                  */
 777                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 778                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 779                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 780                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 781         }
 782
 783         *maskp = mask;
 784 }
 785
 786         __checkReturn   efx_rc_t
 787 efx_mcdi_get_loopback_modes(
 788         __in            efx_nic_t *enp)
 789 {
 790         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 791         efx_mcdi_req_t req;
 792         uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 793                             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN)];
 794         efx_qword_t mask;
 795         efx_qword_t modes;
 796         efx_rc_t rc;
 797
 798         (void) memset(payload, 0, sizeof (payload));
 799         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 800         req.emr_in_buf = payload;
 801         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 802         req.emr_out_buf = payload;
 803         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 804
 805         efx_mcdi_execute(enp, &req);
 806
 807         if (req.emr_rc != 0) {
 808                 rc = req.emr_rc;
 809                 goto fail1;
 810         }
 811
 812         if (req.emr_out_length_used <
 813             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 814             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 815                 rc = EMSGSIZE;
 816                 goto fail2;
 817         }
 818
 819         /*
 820          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 821          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 822          */
 823         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 824
 825         EFX_AND_QWORD(mask,
 826             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 827
 828         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 829         EFX_AND_QWORD(modes, mask);
 830         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 831
 832         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 833         EFX_AND_QWORD(modes, mask);
 834         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 835
 836         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 837         EFX_AND_QWORD(modes, mask);
 838         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 839
 840         if (req.emr_out_length_used >=
 841             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 842             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 843                 /* Response includes 40G loopback modes */
 844                 modes = *MCDI_OUT2(req, efx_qword_t,
 845                     GET_LOOPBACK_MODES_OUT_40G);
 846                 EFX_AND_QWORD(modes, mask);
 847                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 848         }
 849
 850         if (req.emr_out_length_used >=
 851             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
 852             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
 853                 /* Response includes 25G loopback modes */
 854                 modes = *MCDI_OUT2(req, efx_qword_t,
 855                     GET_LOOPBACK_MODES_OUT_V2_25G);
 856                 EFX_AND_QWORD(modes, mask);
 857                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
 858         }
 859
 860         if (req.emr_out_length_used >=
 861             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
 862             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
 863                 /* Response includes 50G loopback modes */
 864                 modes = *MCDI_OUT2(req, efx_qword_t,
 865                     GET_LOOPBACK_MODES_OUT_V2_50G);
 866                 EFX_AND_QWORD(modes, mask);
 867                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
 868         }
 869
 870         if (req.emr_out_length_used >=
 871             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
 872             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
 873                 /* Response includes 100G loopback modes */
 874                 modes = *MCDI_OUT2(req, efx_qword_t,
 875                     GET_LOOPBACK_MODES_OUT_V2_100G);
 876                 EFX_AND_QWORD(modes, mask);
 877                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
 878         }
 879
 880         EFX_ZERO_QWORD(modes);
 881         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 882         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 883         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 884         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 885         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 886         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
 887         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
 888         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
 889         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 890
 891         return (0);
 892
 893 fail2:
 894         EFSYS_PROBE(fail2);
 895 fail1:
 896         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 897
 898         return (rc);
 899 }
 900
 901 #endif /* EFSYS_OPT_LOOPBACK */
 902
 903         __checkReturn   efx_rc_t
 904 efx_nic_calculate_pcie_link_bandwidth(
 905         __in            uint32_t pcie_link_width,
 906         __in            uint32_t pcie_link_gen,
 907         __out           uint32_t *bandwidth_mbpsp)
 908 {
 909         uint32_t lane_bandwidth;
 910         uint32_t total_bandwidth;
 911         efx_rc_t rc;
 912
 913         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
 914             !ISP2(pcie_link_width)) {
 915                 rc = EINVAL;
 916                 goto fail1;
 917         }
 918
 919         switch (pcie_link_gen) {
 920         case EFX_PCIE_LINK_SPEED_GEN1:
 921                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
 922                 lane_bandwidth = 2000;
 923                 break;
 924         case EFX_PCIE_LINK_SPEED_GEN2:
 925                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
 926                 lane_bandwidth = 4000;
 927                 break;
 928         case EFX_PCIE_LINK_SPEED_GEN3:
 929                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
 930                 lane_bandwidth = 7877;
 931                 break;
 932         default:
 933                 rc = EINVAL;
 934                 goto fail2;
 935         }
 936
 937         total_bandwidth = lane_bandwidth * pcie_link_width;
 938         *bandwidth_mbpsp = total_bandwidth;
 939
 940         return (0);
 941
 942 fail2:
 943         EFSYS_PROBE(fail2);
 944 fail1:
 945         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 946
 947         return (rc);
 948 }
 949
 950 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
 951
 952         __checkReturn   efx_rc_t
 953 efx_nic_get_fw_subvariant(
 954         __in            efx_nic_t *enp,
 955         __out           efx_nic_fw_subvariant_t *subvariantp)
 956 {
 957         efx_rc_t rc;
 958         uint32_t value;
 959
 960         rc = efx_mcdi_get_nic_global(enp,
 961             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
 962         if (rc != 0)
 963                 goto fail1;
 964
 965         /* Mapping is not required since values match MCDI */
 966         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
 967             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
 968         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
 969             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
 970
 971         switch (value) {
 972         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
 973         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
 974                 *subvariantp = value;
 975                 break;
 976         default:
 977                 rc = EINVAL;
 978                 goto fail2;
 979         }
 980
 981         return (0);
 982
 983 fail2:
 984         EFSYS_PROBE(fail2);
 985
 986 fail1:
 987         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 988
 989         return (rc);
 990 }
 991
 992         __checkReturn   efx_rc_t
 993 efx_nic_set_fw_subvariant(
 994         __in            efx_nic_t *enp,
 995         __in            efx_nic_fw_subvariant_t subvariant)
 996 {
 997         efx_rc_t rc;
 998
 999         switch (subvariant) {
1000         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1001         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1002                 /* Mapping is not required since values match MCDI */
1003                 break;
1004         default:
1005                 rc = EINVAL;
1006                 goto fail1;
1007         }
1008
1009         rc = efx_mcdi_set_nic_global(enp,
1010             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1011         if (rc != 0)
1012                 goto fail2;
1013
1014         return (0);
1015
1016 fail2:
1017         EFSYS_PROBE(fail2);
1018
1019 fail1:
1020         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1021
1022         return (rc);
1023 }
1024
1025 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1026
1027         __checkReturn   efx_rc_t
1028 efx_nic_check_pcie_link_speed(
1029         __in            efx_nic_t *enp,
1030         __in            uint32_t pcie_link_width,
1031         __in            uint32_t pcie_link_gen,
1032         __out           efx_pcie_link_performance_t *resultp)
1033 {
1034         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1035         uint32_t bandwidth;
1036         efx_pcie_link_performance_t result;
1037         efx_rc_t rc;
1038
1039         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1040             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1041             (pcie_link_gen == 0)) {
1042                 /*
1043                  * No usable info on what is required and/or in use. In virtual
1044                  * machines, sometimes the PCIe link width is reported as 0 or
1045                  * 32, or the speed as 0.
1046                  */
1047                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1048                 goto out;
1049         }
1050
1051         /* Calculate the available bandwidth in megabits per second */
1052         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1053                                             pcie_link_gen, &bandwidth);
1054         if (rc != 0)
1055                 goto fail1;
1056
1057         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1058                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1059         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1060                 /* The link provides enough bandwidth but not optimal latency */
1061                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1062         } else {
1063                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1064         }
1065
1066 out:
1067         *resultp = result;
1068
1069         return (0);
1070
1071 fail1:
1072         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1073
1074         return (rc);
1075 }