drivers/net/sfc/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         *efp = EFX_FAMILY_INVALID;
  89         return (ENOTSUP);
  90 }
  91
  92
  93 #if EFSYS_OPT_SIENA
  94
  95 static const efx_nic_ops_t      __efx_nic_siena_ops = {
  96         siena_nic_probe,                /* eno_probe */
  97         NULL,                           /* eno_board_cfg */
  98         NULL,                           /* eno_set_drv_limits */
  99         siena_nic_reset,                /* eno_reset */
 100         siena_nic_init,                 /* eno_init */
 101         NULL,                           /* eno_get_vi_pool */
 102         NULL,                           /* eno_get_bar_region */
 103         NULL,                           /* eno_hw_unavailable */
 104 #if EFSYS_OPT_DIAG
 105         siena_nic_register_test,        /* eno_register_test */
 106 #endif  /* EFSYS_OPT_DIAG */
 107         siena_nic_fini,                 /* eno_fini */
 108         siena_nic_unprobe,              /* eno_unprobe */
 109 };
 110
 111 #endif  /* EFSYS_OPT_SIENA */
 112
 113 #if EFSYS_OPT_HUNTINGTON
 114
 115 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 116         ef10_nic_probe,                 /* eno_probe */
 117         hunt_board_cfg,                 /* eno_board_cfg */
 118         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 119         ef10_nic_reset,                 /* eno_reset */
 120         ef10_nic_init,                  /* eno_init */
 121         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 122         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 123         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 124 #if EFSYS_OPT_DIAG
 125         ef10_nic_register_test,         /* eno_register_test */
 126 #endif  /* EFSYS_OPT_DIAG */
 127         ef10_nic_fini,                  /* eno_fini */
 128         ef10_nic_unprobe,               /* eno_unprobe */
 129 };
 130
 131 #endif  /* EFSYS_OPT_HUNTINGTON */
 132
 133 #if EFSYS_OPT_MEDFORD
 134
 135 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 136         ef10_nic_probe,                 /* eno_probe */
 137         medford_board_cfg,              /* eno_board_cfg */
 138         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 139         ef10_nic_reset,                 /* eno_reset */
 140         ef10_nic_init,                  /* eno_init */
 141         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 142         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 143         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 144 #if EFSYS_OPT_DIAG
 145         ef10_nic_register_test,         /* eno_register_test */
 146 #endif  /* EFSYS_OPT_DIAG */
 147         ef10_nic_fini,                  /* eno_fini */
 148         ef10_nic_unprobe,               /* eno_unprobe */
 149 };
 150
 151 #endif  /* EFSYS_OPT_MEDFORD */
 152
 153 #if EFSYS_OPT_MEDFORD2
 154
 155 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 156         ef10_nic_probe,                 /* eno_probe */
 157         medford2_board_cfg,             /* eno_board_cfg */
 158         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 159         ef10_nic_reset,                 /* eno_reset */
 160         ef10_nic_init,                  /* eno_init */
 161         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 162         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 163         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 164 #if EFSYS_OPT_DIAG
 165         ef10_nic_register_test,         /* eno_register_test */
 166 #endif  /* EFSYS_OPT_DIAG */
 167         ef10_nic_fini,                  /* eno_fini */
 168         ef10_nic_unprobe,               /* eno_unprobe */
 169 };
 170
 171 #endif  /* EFSYS_OPT_MEDFORD2 */
 172
 173
 174         __checkReturn   efx_rc_t
 175 efx_nic_create(
 176         __in            efx_family_t family,
 177         __in            efsys_identifier_t *esip,
 178         __in            efsys_bar_t *esbp,
 179         __in            efsys_lock_t *eslp,
 180         __deref_out     efx_nic_t **enpp)
 181 {
 182         efx_nic_t *enp;
 183         efx_rc_t rc;
 184
 185         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 186         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 187
 188         /* Allocate a NIC object */
 189         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 190
 191         if (enp == NULL) {
 192                 rc = ENOMEM;
 193                 goto fail1;
 194         }
 195
 196         enp->en_magic = EFX_NIC_MAGIC;
 197
 198         switch (family) {
 199 #if EFSYS_OPT_SIENA
 200         case EFX_FAMILY_SIENA:
 201                 enp->en_enop = &__efx_nic_siena_ops;
 202                 enp->en_features =
 203                     EFX_FEATURE_IPV6 |
 204                     EFX_FEATURE_LFSR_HASH_INSERT |
 205                     EFX_FEATURE_LINK_EVENTS |
 206                     EFX_FEATURE_PERIODIC_MAC_STATS |
 207                     EFX_FEATURE_MCDI |
 208                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 209                     EFX_FEATURE_MAC_HEADER_FILTERS |
 210                     EFX_FEATURE_TX_SRC_FILTERS;
 211                 break;
 212 #endif  /* EFSYS_OPT_SIENA */
 213
 214 #if EFSYS_OPT_HUNTINGTON
 215         case EFX_FAMILY_HUNTINGTON:
 216                 enp->en_enop = &__efx_nic_hunt_ops;
 217                 enp->en_features =
 218                     EFX_FEATURE_IPV6 |
 219                     EFX_FEATURE_LINK_EVENTS |
 220                     EFX_FEATURE_PERIODIC_MAC_STATS |
 221                     EFX_FEATURE_MCDI |
 222                     EFX_FEATURE_MAC_HEADER_FILTERS |
 223                     EFX_FEATURE_MCDI_DMA |
 224                     EFX_FEATURE_PIO_BUFFERS |
 225                     EFX_FEATURE_FW_ASSISTED_TSO |
 226                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 227                     EFX_FEATURE_PACKED_STREAM;
 228                 break;
 229 #endif  /* EFSYS_OPT_HUNTINGTON */
 230
 231 #if EFSYS_OPT_MEDFORD
 232         case EFX_FAMILY_MEDFORD:
 233                 enp->en_enop = &__efx_nic_medford_ops;
 234                 /*
 235                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 236                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 237                  */
 238                 enp->en_features =
 239                     EFX_FEATURE_IPV6 |
 240                     EFX_FEATURE_LINK_EVENTS |
 241                     EFX_FEATURE_PERIODIC_MAC_STATS |
 242                     EFX_FEATURE_MCDI |
 243                     EFX_FEATURE_MAC_HEADER_FILTERS |
 244                     EFX_FEATURE_MCDI_DMA |
 245                     EFX_FEATURE_PIO_BUFFERS |
 246                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 247                     EFX_FEATURE_PACKED_STREAM;
 248                 break;
 249 #endif  /* EFSYS_OPT_MEDFORD */
 250
 251 #if EFSYS_OPT_MEDFORD2
 252         case EFX_FAMILY_MEDFORD2:
 253                 enp->en_enop = &__efx_nic_medford2_ops;
 254                 enp->en_features =
 255                     EFX_FEATURE_IPV6 |
 256                     EFX_FEATURE_LINK_EVENTS |
 257                     EFX_FEATURE_PERIODIC_MAC_STATS |
 258                     EFX_FEATURE_MCDI |
 259                     EFX_FEATURE_MAC_HEADER_FILTERS |
 260                     EFX_FEATURE_MCDI_DMA |
 261                     EFX_FEATURE_PIO_BUFFERS |
 262                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 263                     EFX_FEATURE_PACKED_STREAM;
 264                 break;
 265 #endif  /* EFSYS_OPT_MEDFORD2 */
 266
 267         default:
 268                 rc = ENOTSUP;
 269                 goto fail2;
 270         }
 271
 272         enp->en_family = family;
 273         enp->en_esip = esip;
 274         enp->en_esbp = esbp;
 275         enp->en_eslp = eslp;
 276
 277         *enpp = enp;
 278
 279         return (0);
 280
 281 fail2:
 282         EFSYS_PROBE(fail2);
 283
 284         enp->en_magic = 0;
 285
 286         /* Free the NIC object */
 287         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 288
 289 fail1:
 290         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 291
 292         return (rc);
 293 }
 294
 295         __checkReturn   efx_rc_t
 296 efx_nic_probe(
 297         __in            efx_nic_t *enp,
 298         __in            efx_fw_variant_t efv)
 299 {
 300         const efx_nic_ops_t *enop;
 301         efx_rc_t rc;
 302
 303         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 304 #if EFSYS_OPT_MCDI
 305         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 306 #endif  /* EFSYS_OPT_MCDI */
 307         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 308
 309         /* Ensure FW variant codes match with MC_CMD_FW codes */
 310         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 311             MC_CMD_FW_FULL_FEATURED);
 312         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 313             MC_CMD_FW_LOW_LATENCY);
 314         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 315             MC_CMD_FW_PACKED_STREAM);
 316         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 317             MC_CMD_FW_HIGH_TX_RATE);
 318         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 319             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 320         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 321             MC_CMD_FW_RULES_ENGINE);
 322         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 323             MC_CMD_FW_DPDK);
 324         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 325             (int)MC_CMD_FW_DONT_CARE);
 326
 327         enop = enp->en_enop;
 328         enp->efv = efv;
 329
 330         if ((rc = enop->eno_probe(enp)) != 0)
 331                 goto fail1;
 332
 333         if ((rc = efx_phy_probe(enp)) != 0)
 334                 goto fail2;
 335
 336         enp->en_mod_flags |= EFX_MOD_PROBE;
 337
 338         return (0);
 339
 340 fail2:
 341         EFSYS_PROBE(fail2);
 342
 343         enop->eno_unprobe(enp);
 344
 345 fail1:
 346         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 347
 348         return (rc);
 349 }
 350
 351         __checkReturn   efx_rc_t
 352 efx_nic_set_drv_limits(
 353         __inout         efx_nic_t *enp,
 354         __in            efx_drv_limits_t *edlp)
 355 {
 356         const efx_nic_ops_t *enop = enp->en_enop;
 357         efx_rc_t rc;
 358
 359         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 360         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 361
 362         if (enop->eno_set_drv_limits != NULL) {
 363                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 364                         goto fail1;
 365         }
 366
 367         return (0);
 368
 369 fail1:
 370         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 371
 372         return (rc);
 373 }
 374
 375         __checkReturn   efx_rc_t
 376 efx_nic_get_bar_region(
 377         __in            efx_nic_t *enp,
 378         __in            efx_nic_region_t region,
 379         __out           uint32_t *offsetp,
 380         __out           size_t *sizep)
 381 {
 382         const efx_nic_ops_t *enop = enp->en_enop;
 383         efx_rc_t rc;
 384
 385         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 386         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 387         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 388
 389         if (enop->eno_get_bar_region == NULL) {
 390                 rc = ENOTSUP;
 391                 goto fail1;
 392         }
 393         if ((rc = (enop->eno_get_bar_region)(enp,
 394                     region, offsetp, sizep)) != 0) {
 395                 goto fail2;
 396         }
 397
 398         return (0);
 399
 400 fail2:
 401         EFSYS_PROBE(fail2);
 402
 403 fail1:
 404         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 405
 406         return (rc);
 407 }
 408
 409
 410         __checkReturn   efx_rc_t
 411 efx_nic_get_vi_pool(
 412         __in            efx_nic_t *enp,
 413         __out           uint32_t *evq_countp,
 414         __out           uint32_t *rxq_countp,
 415         __out           uint32_t *txq_countp)
 416 {
 417         const efx_nic_ops_t *enop = enp->en_enop;
 418         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 419         efx_rc_t rc;
 420
 421         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 422         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 423         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 424
 425         if (enop->eno_get_vi_pool != NULL) {
 426                 uint32_t vi_count = 0;
 427
 428                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 429                         goto fail1;
 430
 431                 *evq_countp = vi_count;
 432                 *rxq_countp = vi_count;
 433                 *txq_countp = vi_count;
 434         } else {
 435                 /* Use NIC limits as default value */
 436                 *evq_countp = encp->enc_evq_limit;
 437                 *rxq_countp = encp->enc_rxq_limit;
 438                 *txq_countp = encp->enc_txq_limit;
 439         }
 440
 441         return (0);
 442
 443 fail1:
 444         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 445
 446         return (rc);
 447 }
 448
 449
 450         __checkReturn   efx_rc_t
 451 efx_nic_init(
 452         __in            efx_nic_t *enp)
 453 {
 454         const efx_nic_ops_t *enop = enp->en_enop;
 455         efx_rc_t rc;
 456
 457         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 458         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 459
 460         if (enp->en_mod_flags & EFX_MOD_NIC) {
 461                 rc = EINVAL;
 462                 goto fail1;
 463         }
 464
 465         if ((rc = enop->eno_init(enp)) != 0)
 466                 goto fail2;
 467
 468         enp->en_mod_flags |= EFX_MOD_NIC;
 469
 470         return (0);
 471
 472 fail2:
 473         EFSYS_PROBE(fail2);
 474 fail1:
 475         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 476
 477         return (rc);
 478 }
 479
 480                         void
 481 efx_nic_fini(
 482         __in            efx_nic_t *enp)
 483 {
 484         const efx_nic_ops_t *enop = enp->en_enop;
 485
 486         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 487         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 488         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 489         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 490         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 491         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 492         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 493
 494         enop->eno_fini(enp);
 495
 496         enp->en_mod_flags &= ~EFX_MOD_NIC;
 497 }
 498
 499                         void
 500 efx_nic_unprobe(
 501         __in            efx_nic_t *enp)
 502 {
 503         const efx_nic_ops_t *enop = enp->en_enop;
 504
 505         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 506 #if EFSYS_OPT_MCDI
 507         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 508 #endif  /* EFSYS_OPT_MCDI */
 509         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 510         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 511         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 512         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 513         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 514         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 515
 516         efx_phy_unprobe(enp);
 517
 518         enop->eno_unprobe(enp);
 519
 520         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 521 }
 522
 523                         void
 524 efx_nic_destroy(
 525         __in    efx_nic_t *enp)
 526 {
 527         efsys_identifier_t *esip = enp->en_esip;
 528
 529         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 530         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 531
 532         enp->en_family = EFX_FAMILY_INVALID;
 533         enp->en_esip = NULL;
 534         enp->en_esbp = NULL;
 535         enp->en_eslp = NULL;
 536
 537         enp->en_enop = NULL;
 538
 539         enp->en_magic = 0;
 540
 541         /* Free the NIC object */
 542         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 543 }
 544
 545         __checkReturn   efx_rc_t
 546 efx_nic_reset(
 547         __in            efx_nic_t *enp)
 548 {
 549         const efx_nic_ops_t *enop = enp->en_enop;
 550         unsigned int mod_flags;
 551         efx_rc_t rc;
 552
 553         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 554         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 555         /*
 556          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 557          * (which we do not reset here) must have been shut down or never
 558          * initialized.
 559          *
 560          * A rule of thumb here is: If the controller or MC reboots, is *any*
 561          * state lost. If it's lost and needs reapplying, then the module
 562          * *must* not be initialised during the reset.
 563          */
 564         mod_flags = enp->en_mod_flags;
 565         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 566             EFX_MOD_VPD | EFX_MOD_MON);
 567 #if EFSYS_OPT_TUNNEL
 568         mod_flags &= ~EFX_MOD_TUNNEL;
 569 #endif /* EFSYS_OPT_TUNNEL */
 570         EFSYS_ASSERT3U(mod_flags, ==, 0);
 571         if (mod_flags != 0) {
 572                 rc = EINVAL;
 573                 goto fail1;
 574         }
 575
 576         if ((rc = enop->eno_reset(enp)) != 0)
 577                 goto fail2;
 578
 579         return (0);
 580
 581 fail2:
 582         EFSYS_PROBE(fail2);
 583 fail1:
 584         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 585
 586         return (rc);
 587 }
 588
 589                         const efx_nic_cfg_t *
 590 efx_nic_cfg_get(
 591         __in            efx_nic_t *enp)
 592 {
 593         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 594
 595         return (&(enp->en_nic_cfg));
 596 }
 597
 598         __checkReturn           efx_rc_t
 599 efx_nic_get_fw_version(
 600         __in                    efx_nic_t *enp,
 601         __out                   efx_nic_fw_info_t *enfip)
 602 {
 603         uint16_t mc_fw_version[4];
 604         efx_rc_t rc;
 605
 606         if (enfip == NULL) {
 607                 rc = EINVAL;
 608                 goto fail1;
 609         }
 610
 611         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 612         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 613
 614         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 615         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 616             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 617         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 618             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 619         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 620             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 621         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 622             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 623         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 624             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 625
 626         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 627         if (rc != 0)
 628                 goto fail2;
 629
 630         rc = efx_mcdi_get_capabilities(enp, NULL,
 631             &enfip->enfi_rx_dpcpu_fw_id,
 632             &enfip->enfi_tx_dpcpu_fw_id,
 633             NULL, NULL);
 634         if (rc == 0) {
 635                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 636         } else if (rc == ENOTSUP) {
 637                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 638                 enfip->enfi_rx_dpcpu_fw_id = 0;
 639                 enfip->enfi_tx_dpcpu_fw_id = 0;
 640         } else {
 641                 goto fail3;
 642         }
 643
 644         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 645             sizeof (mc_fw_version));
 646
 647         return (0);
 648
 649 fail3:
 650         EFSYS_PROBE(fail3);
 651 fail2:
 652         EFSYS_PROBE(fail2);
 653 fail1:
 654         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 655
 656         return (rc);
 657 }
 658
 659         __checkReturn   boolean_t
 660 efx_nic_hw_unavailable(
 661         __in            efx_nic_t *enp)
 662 {
 663         const efx_nic_ops_t *enop = enp->en_enop;
 664
 665         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 666         /* NOTE: can be used by MCDI before NIC probe */
 667
 668         if (enop->eno_hw_unavailable != NULL) {
 669                 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
 670                         goto unavail;
 671         }
 672
 673         return (B_FALSE);
 674
 675 unavail:
 676         EFSYS_PROBE(hw_unavail);
 677
 678         return (B_TRUE);
 679 }
 680
 681
 682 #if EFSYS_OPT_DIAG
 683
 684         __checkReturn   efx_rc_t
 685 efx_nic_register_test(
 686         __in            efx_nic_t *enp)
 687 {
 688         const efx_nic_ops_t *enop = enp->en_enop;
 689         efx_rc_t rc;
 690
 691         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 692         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 693         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 694
 695         if ((rc = enop->eno_register_test(enp)) != 0)
 696                 goto fail1;
 697
 698         return (0);
 699
 700 fail1:
 701         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 702
 703         return (rc);
 704 }
 705
 706 #endif  /* EFSYS_OPT_DIAG */
 707
 708 #if EFSYS_OPT_LOOPBACK
 709
 710 extern                  void
 711 efx_loopback_mask(
 712         __in    efx_loopback_kind_t loopback_kind,
 713         __out   efx_qword_t *maskp)
 714 {
 715         efx_qword_t mask;
 716
 717         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 718         EFSYS_ASSERT(maskp != NULL);
 719
 720         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 721 #define LOOPBACK_CHECK(_mcdi, _efx) \
 722         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 723
 724         LOOPBACK_CHECK(NONE, OFF);
 725         LOOPBACK_CHECK(DATA, DATA);
 726         LOOPBACK_CHECK(GMAC, GMAC);
 727         LOOPBACK_CHECK(XGMII, XGMII);
 728         LOOPBACK_CHECK(XGXS, XGXS);
 729         LOOPBACK_CHECK(XAUI, XAUI);
 730         LOOPBACK_CHECK(GMII, GMII);
 731         LOOPBACK_CHECK(SGMII, SGMII);
 732         LOOPBACK_CHECK(XGBR, XGBR);
 733         LOOPBACK_CHECK(XFI, XFI);
 734         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 735         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 736         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 737         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 738         LOOPBACK_CHECK(GPHY, GPHY);
 739         LOOPBACK_CHECK(PHYXS, PHY_XS);
 740         LOOPBACK_CHECK(PCS, PCS);
 741         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 742         LOOPBACK_CHECK(XPORT, XPORT);
 743         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 744         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 745         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 746         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 747         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 748         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 749         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 750         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 751         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 752         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 753         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 754         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 755         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 756         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 757         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 758         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 759         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 760         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 761         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 762 #undef LOOPBACK_CHECK
 763
 764         /* Build bitmask of possible loopback types */
 765         EFX_ZERO_QWORD(mask);
 766
 767         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 768             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 769                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 770         }
 771
 772         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 773             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 774                 /*
 775                  * The "MAC" grouping has historically been used by drivers to
 776                  * mean loopbacks supported by on-chip hardware. Keep that
 777                  * meaning here, and include on-chip PHY layer loopbacks.
 778                  */
 779                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 780                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 781                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 782                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 783                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 784                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 785                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 786                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 787                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 788                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 789                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 790                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 791                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 792                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 793                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 794                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 795         }
 796
 797         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 798             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 799                 /*
 800                  * The "PHY" grouping has historically been used by drivers to
 801                  * mean loopbacks supported by off-chip hardware. Keep that
 802                  * meaning here.
 803                  */
 804                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 805                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 806                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 807                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 808         }
 809
 810         *maskp = mask;
 811 }
 812
 813         __checkReturn   efx_rc_t
 814 efx_mcdi_get_loopback_modes(
 815         __in            efx_nic_t *enp)
 816 {
 817         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 818         efx_mcdi_req_t req;
 819         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 820                 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
 821         efx_qword_t mask;
 822         efx_qword_t modes;
 823         efx_rc_t rc;
 824
 825         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 826         req.emr_in_buf = payload;
 827         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 828         req.emr_out_buf = payload;
 829         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 830
 831         efx_mcdi_execute(enp, &req);
 832
 833         if (req.emr_rc != 0) {
 834                 rc = req.emr_rc;
 835                 goto fail1;
 836         }
 837
 838         if (req.emr_out_length_used <
 839             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 840             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 841                 rc = EMSGSIZE;
 842                 goto fail2;
 843         }
 844
 845         /*
 846          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 847          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 848          */
 849         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 850
 851         EFX_AND_QWORD(mask,
 852             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 853
 854         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 855         EFX_AND_QWORD(modes, mask);
 856         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 857
 858         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 859         EFX_AND_QWORD(modes, mask);
 860         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 861
 862         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 863         EFX_AND_QWORD(modes, mask);
 864         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 865
 866         if (req.emr_out_length_used >=
 867             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 868             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 869                 /* Response includes 40G loopback modes */
 870                 modes = *MCDI_OUT2(req, efx_qword_t,
 871                     GET_LOOPBACK_MODES_OUT_40G);
 872                 EFX_AND_QWORD(modes, mask);
 873                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 874         }
 875
 876         if (req.emr_out_length_used >=
 877             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
 878             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
 879                 /* Response includes 25G loopback modes */
 880                 modes = *MCDI_OUT2(req, efx_qword_t,
 881                     GET_LOOPBACK_MODES_OUT_V2_25G);
 882                 EFX_AND_QWORD(modes, mask);
 883                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
 884         }
 885
 886         if (req.emr_out_length_used >=
 887             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
 888             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
 889                 /* Response includes 50G loopback modes */
 890                 modes = *MCDI_OUT2(req, efx_qword_t,
 891                     GET_LOOPBACK_MODES_OUT_V2_50G);
 892                 EFX_AND_QWORD(modes, mask);
 893                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
 894         }
 895
 896         if (req.emr_out_length_used >=
 897             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
 898             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
 899                 /* Response includes 100G loopback modes */
 900                 modes = *MCDI_OUT2(req, efx_qword_t,
 901                     GET_LOOPBACK_MODES_OUT_V2_100G);
 902                 EFX_AND_QWORD(modes, mask);
 903                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
 904         }
 905
 906         EFX_ZERO_QWORD(modes);
 907         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 908         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 909         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 910         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 911         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 912         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
 913         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
 914         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
 915         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 916
 917         return (0);
 918
 919 fail2:
 920         EFSYS_PROBE(fail2);
 921 fail1:
 922         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 923
 924         return (rc);
 925 }
 926
 927 #endif /* EFSYS_OPT_LOOPBACK */
 928
 929         __checkReturn   efx_rc_t
 930 efx_nic_calculate_pcie_link_bandwidth(
 931         __in            uint32_t pcie_link_width,
 932         __in            uint32_t pcie_link_gen,
 933         __out           uint32_t *bandwidth_mbpsp)
 934 {
 935         uint32_t lane_bandwidth;
 936         uint32_t total_bandwidth;
 937         efx_rc_t rc;
 938
 939         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
 940             !ISP2(pcie_link_width)) {
 941                 rc = EINVAL;
 942                 goto fail1;
 943         }
 944
 945         switch (pcie_link_gen) {
 946         case EFX_PCIE_LINK_SPEED_GEN1:
 947                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
 948                 lane_bandwidth = 2000;
 949                 break;
 950         case EFX_PCIE_LINK_SPEED_GEN2:
 951                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
 952                 lane_bandwidth = 4000;
 953                 break;
 954         case EFX_PCIE_LINK_SPEED_GEN3:
 955                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
 956                 lane_bandwidth = 7877;
 957                 break;
 958         default:
 959                 rc = EINVAL;
 960                 goto fail2;
 961         }
 962
 963         total_bandwidth = lane_bandwidth * pcie_link_width;
 964         *bandwidth_mbpsp = total_bandwidth;
 965
 966         return (0);
 967
 968 fail2:
 969         EFSYS_PROBE(fail2);
 970 fail1:
 971         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 972
 973         return (rc);
 974 }
 975
 976 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
 977
 978         __checkReturn   efx_rc_t
 979 efx_nic_get_fw_subvariant(
 980         __in            efx_nic_t *enp,
 981         __out           efx_nic_fw_subvariant_t *subvariantp)
 982 {
 983         efx_rc_t rc;
 984         uint32_t value;
 985
 986         rc = efx_mcdi_get_nic_global(enp,
 987             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
 988         if (rc != 0)
 989                 goto fail1;
 990
 991         /* Mapping is not required since values match MCDI */
 992         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
 993             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
 994         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
 995             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
 996
 997         switch (value) {
 998         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
 999         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1000                 *subvariantp = value;
1001                 break;
1002         default:
1003                 rc = EINVAL;
1004                 goto fail2;
1005         }
1006
1007         return (0);
1008
1009 fail2:
1010         EFSYS_PROBE(fail2);
1011
1012 fail1:
1013         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1014
1015         return (rc);
1016 }
1017
1018         __checkReturn   efx_rc_t
1019 efx_nic_set_fw_subvariant(
1020         __in            efx_nic_t *enp,
1021         __in            efx_nic_fw_subvariant_t subvariant)
1022 {
1023         efx_rc_t rc;
1024
1025         switch (subvariant) {
1026         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1027         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1028                 /* Mapping is not required since values match MCDI */
1029                 break;
1030         default:
1031                 rc = EINVAL;
1032                 goto fail1;
1033         }
1034
1035         rc = efx_mcdi_set_nic_global(enp,
1036             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1037         if (rc != 0)
1038                 goto fail2;
1039
1040         return (0);
1041
1042 fail2:
1043         EFSYS_PROBE(fail2);
1044
1045 fail1:
1046         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1047
1048         return (rc);
1049 }
1050
1051 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1052
1053         __checkReturn   efx_rc_t
1054 efx_nic_check_pcie_link_speed(
1055         __in            efx_nic_t *enp,
1056         __in            uint32_t pcie_link_width,
1057         __in            uint32_t pcie_link_gen,
1058         __out           efx_pcie_link_performance_t *resultp)
1059 {
1060         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1061         uint32_t bandwidth;
1062         efx_pcie_link_performance_t result;
1063         efx_rc_t rc;
1064
1065         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1066             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1067             (pcie_link_gen == 0)) {
1068                 /*
1069                  * No usable info on what is required and/or in use. In virtual
1070                  * machines, sometimes the PCIe link width is reported as 0 or
1071                  * 32, or the speed as 0.
1072                  */
1073                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1074                 goto out;
1075         }
1076
1077         /* Calculate the available bandwidth in megabits per second */
1078         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1079                                             pcie_link_gen, &bandwidth);
1080         if (rc != 0)
1081                 goto fail1;
1082
1083         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1084                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1085         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1086                 /* The link provides enough bandwidth but not optimal latency */
1087                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1088         } else {
1089                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1090         }
1091
1092 out:
1093         *resultp = result;
1094
1095         return (0);
1096
1097 fail1:
1098         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1099
1100         return (rc);
1101 }