1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
11 __checkReturn efx_rc_t
15 __out efx_family_t *efp,
16 __out unsigned int *membarp)
18 if (venid == EFX_PCI_VENID_SFC) {
21 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
23 * Hardware default for PF0 of uninitialised Siena.
24 * manftest must be able to cope with this device id.
26 case EFX_PCI_DEVID_BETHPAGE:
27 case EFX_PCI_DEVID_SIENA:
28 *efp = EFX_FAMILY_SIENA;
29 *membarp = EFX_MEM_BAR_SIENA;
31 #endif /* EFSYS_OPT_SIENA */
33 #if EFSYS_OPT_HUNTINGTON
34 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
36 * Hardware default for PF0 of uninitialised Huntington.
37 * manftest must be able to cope with this device id.
39 case EFX_PCI_DEVID_FARMINGDALE:
40 case EFX_PCI_DEVID_GREENPORT:
41 *efp = EFX_FAMILY_HUNTINGTON;
42 *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
45 case EFX_PCI_DEVID_FARMINGDALE_VF:
46 case EFX_PCI_DEVID_GREENPORT_VF:
47 *efp = EFX_FAMILY_HUNTINGTON;
48 *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
55 * Hardware default for PF0 of uninitialised Medford.
56 * manftest must be able to cope with this device id.
58 case EFX_PCI_DEVID_MEDFORD:
59 *efp = EFX_FAMILY_MEDFORD;
60 *membarp = EFX_MEM_BAR_MEDFORD_PF;
63 case EFX_PCI_DEVID_MEDFORD_VF:
64 *efp = EFX_FAMILY_MEDFORD;
65 *membarp = EFX_MEM_BAR_MEDFORD_VF;
67 #endif /* EFSYS_OPT_MEDFORD */
69 #if EFSYS_OPT_MEDFORD2
70 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
72 * Hardware default for PF0 of uninitialised Medford2.
73 * manftest must be able to cope with this device id.
75 case EFX_PCI_DEVID_MEDFORD2:
76 case EFX_PCI_DEVID_MEDFORD2_VF:
77 *efp = EFX_FAMILY_MEDFORD2;
78 *membarp = EFX_MEM_BAR_MEDFORD2;
80 #endif /* EFSYS_OPT_MEDFORD2 */
82 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
88 *efp = EFX_FAMILY_INVALID;
95 static const efx_nic_ops_t __efx_nic_siena_ops = {
96 siena_nic_probe, /* eno_probe */
97 NULL, /* eno_board_cfg */
98 NULL, /* eno_set_drv_limits */
99 siena_nic_reset, /* eno_reset */
100 siena_nic_init, /* eno_init */
101 NULL, /* eno_get_vi_pool */
102 NULL, /* eno_get_bar_region */
104 siena_nic_register_test, /* eno_register_test */
105 #endif /* EFSYS_OPT_DIAG */
106 siena_nic_fini, /* eno_fini */
107 siena_nic_unprobe, /* eno_unprobe */
110 #endif /* EFSYS_OPT_SIENA */
112 #if EFSYS_OPT_HUNTINGTON
114 static const efx_nic_ops_t __efx_nic_hunt_ops = {
115 ef10_nic_probe, /* eno_probe */
116 hunt_board_cfg, /* eno_board_cfg */
117 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
118 ef10_nic_reset, /* eno_reset */
119 ef10_nic_init, /* eno_init */
120 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
121 ef10_nic_get_bar_region, /* eno_get_bar_region */
123 ef10_nic_register_test, /* eno_register_test */
124 #endif /* EFSYS_OPT_DIAG */
125 ef10_nic_fini, /* eno_fini */
126 ef10_nic_unprobe, /* eno_unprobe */
129 #endif /* EFSYS_OPT_HUNTINGTON */
131 #if EFSYS_OPT_MEDFORD
133 static const efx_nic_ops_t __efx_nic_medford_ops = {
134 ef10_nic_probe, /* eno_probe */
135 medford_board_cfg, /* eno_board_cfg */
136 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
137 ef10_nic_reset, /* eno_reset */
138 ef10_nic_init, /* eno_init */
139 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
140 ef10_nic_get_bar_region, /* eno_get_bar_region */
142 ef10_nic_register_test, /* eno_register_test */
143 #endif /* EFSYS_OPT_DIAG */
144 ef10_nic_fini, /* eno_fini */
145 ef10_nic_unprobe, /* eno_unprobe */
148 #endif /* EFSYS_OPT_MEDFORD */
150 #if EFSYS_OPT_MEDFORD2
152 static const efx_nic_ops_t __efx_nic_medford2_ops = {
153 ef10_nic_probe, /* eno_probe */
154 medford2_board_cfg, /* eno_board_cfg */
155 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
156 ef10_nic_reset, /* eno_reset */
157 ef10_nic_init, /* eno_init */
158 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
159 ef10_nic_get_bar_region, /* eno_get_bar_region */
161 ef10_nic_register_test, /* eno_register_test */
162 #endif /* EFSYS_OPT_DIAG */
163 ef10_nic_fini, /* eno_fini */
164 ef10_nic_unprobe, /* eno_unprobe */
167 #endif /* EFSYS_OPT_MEDFORD2 */
170 __checkReturn efx_rc_t
172 __in efx_family_t family,
173 __in efsys_identifier_t *esip,
174 __in efsys_bar_t *esbp,
175 __in efsys_lock_t *eslp,
176 __deref_out efx_nic_t **enpp)
181 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
182 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
184 /* Allocate a NIC object */
185 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
192 enp->en_magic = EFX_NIC_MAGIC;
196 case EFX_FAMILY_SIENA:
197 enp->en_enop = &__efx_nic_siena_ops;
200 EFX_FEATURE_LFSR_HASH_INSERT |
201 EFX_FEATURE_LINK_EVENTS |
202 EFX_FEATURE_PERIODIC_MAC_STATS |
204 EFX_FEATURE_LOOKAHEAD_SPLIT |
205 EFX_FEATURE_MAC_HEADER_FILTERS |
206 EFX_FEATURE_TX_SRC_FILTERS;
208 #endif /* EFSYS_OPT_SIENA */
210 #if EFSYS_OPT_HUNTINGTON
211 case EFX_FAMILY_HUNTINGTON:
212 enp->en_enop = &__efx_nic_hunt_ops;
215 EFX_FEATURE_LINK_EVENTS |
216 EFX_FEATURE_PERIODIC_MAC_STATS |
218 EFX_FEATURE_MAC_HEADER_FILTERS |
219 EFX_FEATURE_MCDI_DMA |
220 EFX_FEATURE_PIO_BUFFERS |
221 EFX_FEATURE_FW_ASSISTED_TSO |
222 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
223 EFX_FEATURE_PACKED_STREAM;
225 #endif /* EFSYS_OPT_HUNTINGTON */
227 #if EFSYS_OPT_MEDFORD
228 case EFX_FAMILY_MEDFORD:
229 enp->en_enop = &__efx_nic_medford_ops;
231 * FW_ASSISTED_TSO omitted as Medford only supports firmware
232 * assisted TSO version 2, not the v1 scheme used on Huntington.
236 EFX_FEATURE_LINK_EVENTS |
237 EFX_FEATURE_PERIODIC_MAC_STATS |
239 EFX_FEATURE_MAC_HEADER_FILTERS |
240 EFX_FEATURE_MCDI_DMA |
241 EFX_FEATURE_PIO_BUFFERS |
242 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
243 EFX_FEATURE_PACKED_STREAM;
245 #endif /* EFSYS_OPT_MEDFORD */
247 #if EFSYS_OPT_MEDFORD2
248 case EFX_FAMILY_MEDFORD2:
249 enp->en_enop = &__efx_nic_medford2_ops;
252 EFX_FEATURE_LINK_EVENTS |
253 EFX_FEATURE_PERIODIC_MAC_STATS |
255 EFX_FEATURE_MAC_HEADER_FILTERS |
256 EFX_FEATURE_MCDI_DMA |
257 EFX_FEATURE_PIO_BUFFERS |
258 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
259 EFX_FEATURE_PACKED_STREAM;
261 #endif /* EFSYS_OPT_MEDFORD2 */
268 enp->en_family = family;
282 /* Free the NIC object */
283 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
286 EFSYS_PROBE1(fail1, efx_rc_t, rc);
291 __checkReturn efx_rc_t
294 __in efx_fw_variant_t efv)
296 const efx_nic_ops_t *enop;
299 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
301 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
302 #endif /* EFSYS_OPT_MCDI */
303 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
305 /* Ensure FW variant codes match with MC_CMD_FW codes */
306 EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
307 MC_CMD_FW_FULL_FEATURED);
308 EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
309 MC_CMD_FW_LOW_LATENCY);
310 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
311 MC_CMD_FW_PACKED_STREAM);
312 EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
313 MC_CMD_FW_HIGH_TX_RATE);
314 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
315 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
316 EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
317 MC_CMD_FW_RULES_ENGINE);
318 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
320 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
321 (int)MC_CMD_FW_DONT_CARE);
326 if ((rc = enop->eno_probe(enp)) != 0)
329 if ((rc = efx_phy_probe(enp)) != 0)
332 enp->en_mod_flags |= EFX_MOD_PROBE;
339 enop->eno_unprobe(enp);
342 EFSYS_PROBE1(fail1, efx_rc_t, rc);
347 __checkReturn efx_rc_t
348 efx_nic_set_drv_limits(
349 __inout efx_nic_t *enp,
350 __in efx_drv_limits_t *edlp)
352 const efx_nic_ops_t *enop = enp->en_enop;
355 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
356 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
358 if (enop->eno_set_drv_limits != NULL) {
359 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
366 EFSYS_PROBE1(fail1, efx_rc_t, rc);
371 __checkReturn efx_rc_t
372 efx_nic_get_bar_region(
374 __in efx_nic_region_t region,
375 __out uint32_t *offsetp,
378 const efx_nic_ops_t *enop = enp->en_enop;
381 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
382 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
383 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
385 if (enop->eno_get_bar_region == NULL) {
389 if ((rc = (enop->eno_get_bar_region)(enp,
390 region, offsetp, sizep)) != 0) {
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
406 __checkReturn efx_rc_t
409 __out uint32_t *evq_countp,
410 __out uint32_t *rxq_countp,
411 __out uint32_t *txq_countp)
413 const efx_nic_ops_t *enop = enp->en_enop;
414 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
417 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
418 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
419 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
421 if (enop->eno_get_vi_pool != NULL) {
422 uint32_t vi_count = 0;
424 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
427 *evq_countp = vi_count;
428 *rxq_countp = vi_count;
429 *txq_countp = vi_count;
431 /* Use NIC limits as default value */
432 *evq_countp = encp->enc_evq_limit;
433 *rxq_countp = encp->enc_rxq_limit;
434 *txq_countp = encp->enc_txq_limit;
440 EFSYS_PROBE1(fail1, efx_rc_t, rc);
446 __checkReturn efx_rc_t
450 const efx_nic_ops_t *enop = enp->en_enop;
453 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
454 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
456 if (enp->en_mod_flags & EFX_MOD_NIC) {
461 if ((rc = enop->eno_init(enp)) != 0)
464 enp->en_mod_flags |= EFX_MOD_NIC;
471 EFSYS_PROBE1(fail1, efx_rc_t, rc);
480 const efx_nic_ops_t *enop = enp->en_enop;
482 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
483 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
484 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
485 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
486 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
487 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
488 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
492 enp->en_mod_flags &= ~EFX_MOD_NIC;
499 const efx_nic_ops_t *enop = enp->en_enop;
501 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
503 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
504 #endif /* EFSYS_OPT_MCDI */
505 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
506 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
507 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
508 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
509 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
510 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
512 efx_phy_unprobe(enp);
514 enop->eno_unprobe(enp);
516 enp->en_mod_flags &= ~EFX_MOD_PROBE;
523 efsys_identifier_t *esip = enp->en_esip;
525 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
526 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
528 enp->en_family = EFX_FAMILY_INVALID;
537 /* Free the NIC object */
538 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
541 __checkReturn efx_rc_t
545 const efx_nic_ops_t *enop = enp->en_enop;
546 unsigned int mod_flags;
549 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
550 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
552 * All modules except the MCDI, PROBE, NVRAM, VPD, MON
553 * (which we do not reset here) must have been shut down or never
556 * A rule of thumb here is: If the controller or MC reboots, is *any*
557 * state lost. If it's lost and needs reapplying, then the module
558 * *must* not be initialised during the reset.
560 mod_flags = enp->en_mod_flags;
561 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
562 EFX_MOD_VPD | EFX_MOD_MON);
563 EFSYS_ASSERT3U(mod_flags, ==, 0);
564 if (mod_flags != 0) {
569 if ((rc = enop->eno_reset(enp)) != 0)
577 EFSYS_PROBE1(fail1, efx_rc_t, rc);
582 const efx_nic_cfg_t *
586 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
588 return (&(enp->en_nic_cfg));
591 __checkReturn efx_rc_t
592 efx_nic_get_fw_version(
594 __out efx_nic_fw_info_t *enfip)
596 uint16_t mc_fw_version[4];
604 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
605 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
607 rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
611 rc = efx_mcdi_get_capabilities(enp, NULL,
612 &enfip->enfi_rx_dpcpu_fw_id,
613 &enfip->enfi_tx_dpcpu_fw_id,
616 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
617 } else if (rc == ENOTSUP) {
618 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
619 enfip->enfi_rx_dpcpu_fw_id = 0;
620 enfip->enfi_tx_dpcpu_fw_id = 0;
625 memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
626 sizeof (mc_fw_version));
635 EFSYS_PROBE1(fail1, efx_rc_t, rc);
642 __checkReturn efx_rc_t
643 efx_nic_register_test(
646 const efx_nic_ops_t *enop = enp->en_enop;
649 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
650 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
651 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
653 if ((rc = enop->eno_register_test(enp)) != 0)
659 EFSYS_PROBE1(fail1, efx_rc_t, rc);
664 #endif /* EFSYS_OPT_DIAG */
666 #if EFSYS_OPT_LOOPBACK
670 __in efx_loopback_kind_t loopback_kind,
671 __out efx_qword_t *maskp)
675 EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
676 EFSYS_ASSERT(maskp != NULL);
678 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
679 #define LOOPBACK_CHECK(_mcdi, _efx) \
680 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
682 LOOPBACK_CHECK(NONE, OFF);
683 LOOPBACK_CHECK(DATA, DATA);
684 LOOPBACK_CHECK(GMAC, GMAC);
685 LOOPBACK_CHECK(XGMII, XGMII);
686 LOOPBACK_CHECK(XGXS, XGXS);
687 LOOPBACK_CHECK(XAUI, XAUI);
688 LOOPBACK_CHECK(GMII, GMII);
689 LOOPBACK_CHECK(SGMII, SGMII);
690 LOOPBACK_CHECK(XGBR, XGBR);
691 LOOPBACK_CHECK(XFI, XFI);
692 LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
693 LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
694 LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
695 LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
696 LOOPBACK_CHECK(GPHY, GPHY);
697 LOOPBACK_CHECK(PHYXS, PHY_XS);
698 LOOPBACK_CHECK(PCS, PCS);
699 LOOPBACK_CHECK(PMAPMD, PMA_PMD);
700 LOOPBACK_CHECK(XPORT, XPORT);
701 LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
702 LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
703 LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
704 LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
705 LOOPBACK_CHECK(GMII_WS, GMII_WS);
706 LOOPBACK_CHECK(XFI_WS, XFI_WS);
707 LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
708 LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
709 LOOPBACK_CHECK(PMA_INT, PMA_INT);
710 LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
711 LOOPBACK_CHECK(SD_FAR, SD_FAR);
712 LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
713 LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
714 LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
715 LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
716 LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
717 LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
718 LOOPBACK_CHECK(DATA_WS, DATA_WS);
719 LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
720 #undef LOOPBACK_CHECK
722 /* Build bitmask of possible loopback types */
723 EFX_ZERO_QWORD(mask);
725 if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
726 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
727 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
730 if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
731 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
733 * The "MAC" grouping has historically been used by drivers to
734 * mean loopbacks supported by on-chip hardware. Keep that
735 * meaning here, and include on-chip PHY layer loopbacks.
737 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
738 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
739 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
740 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
741 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
742 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
743 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
744 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
745 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
746 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
747 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
748 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
749 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
750 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
751 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
752 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
755 if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
756 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
758 * The "PHY" grouping has historically been used by drivers to
759 * mean loopbacks supported by off-chip hardware. Keep that
762 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
763 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
764 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
765 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
771 __checkReturn efx_rc_t
772 efx_mcdi_get_loopback_modes(
775 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
777 uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
778 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN)];
783 (void) memset(payload, 0, sizeof (payload));
784 req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
785 req.emr_in_buf = payload;
786 req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
787 req.emr_out_buf = payload;
788 req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
790 efx_mcdi_execute(enp, &req);
792 if (req.emr_rc != 0) {
797 if (req.emr_out_length_used <
798 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
799 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
805 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
806 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
808 efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
811 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
813 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
814 EFX_AND_QWORD(modes, mask);
815 encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
817 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
818 EFX_AND_QWORD(modes, mask);
819 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
821 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
822 EFX_AND_QWORD(modes, mask);
823 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
825 if (req.emr_out_length_used >=
826 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
827 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
828 /* Response includes 40G loopback modes */
829 modes = *MCDI_OUT2(req, efx_qword_t,
830 GET_LOOPBACK_MODES_OUT_40G);
831 EFX_AND_QWORD(modes, mask);
832 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
835 if (req.emr_out_length_used >=
836 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
837 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
838 /* Response includes 25G loopback modes */
839 modes = *MCDI_OUT2(req, efx_qword_t,
840 GET_LOOPBACK_MODES_OUT_V2_25G);
841 EFX_AND_QWORD(modes, mask);
842 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
845 if (req.emr_out_length_used >=
846 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
847 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
848 /* Response includes 50G loopback modes */
849 modes = *MCDI_OUT2(req, efx_qword_t,
850 GET_LOOPBACK_MODES_OUT_V2_50G);
851 EFX_AND_QWORD(modes, mask);
852 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
855 if (req.emr_out_length_used >=
856 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
857 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
858 /* Response includes 100G loopback modes */
859 modes = *MCDI_OUT2(req, efx_qword_t,
860 GET_LOOPBACK_MODES_OUT_V2_100G);
861 EFX_AND_QWORD(modes, mask);
862 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
865 EFX_ZERO_QWORD(modes);
866 EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
867 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
868 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
869 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
870 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
871 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
872 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
873 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
874 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
881 EFSYS_PROBE1(fail1, efx_rc_t, rc);
886 #endif /* EFSYS_OPT_LOOPBACK */
888 __checkReturn efx_rc_t
889 efx_nic_calculate_pcie_link_bandwidth(
890 __in uint32_t pcie_link_width,
891 __in uint32_t pcie_link_gen,
892 __out uint32_t *bandwidth_mbpsp)
894 uint32_t lane_bandwidth;
895 uint32_t total_bandwidth;
898 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
899 !ISP2(pcie_link_width)) {
904 switch (pcie_link_gen) {
905 case EFX_PCIE_LINK_SPEED_GEN1:
906 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
907 lane_bandwidth = 2000;
909 case EFX_PCIE_LINK_SPEED_GEN2:
910 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
911 lane_bandwidth = 4000;
913 case EFX_PCIE_LINK_SPEED_GEN3:
914 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
915 lane_bandwidth = 7877;
922 total_bandwidth = lane_bandwidth * pcie_link_width;
923 *bandwidth_mbpsp = total_bandwidth;
930 EFSYS_PROBE1(fail1, efx_rc_t, rc);
936 __checkReturn efx_rc_t
937 efx_nic_check_pcie_link_speed(
939 __in uint32_t pcie_link_width,
940 __in uint32_t pcie_link_gen,
941 __out efx_pcie_link_performance_t *resultp)
943 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
945 efx_pcie_link_performance_t result;
948 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
949 (pcie_link_width == 0) || (pcie_link_width == 32) ||
950 (pcie_link_gen == 0)) {
952 * No usable info on what is required and/or in use. In virtual
953 * machines, sometimes the PCIe link width is reported as 0 or
954 * 32, or the speed as 0.
956 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
960 /* Calculate the available bandwidth in megabits per second */
961 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
962 pcie_link_gen, &bandwidth);
966 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
967 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
968 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
969 /* The link provides enough bandwidth but not optimal latency */
970 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
972 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
981 EFSYS_PROBE1(fail1, efx_rc_t, rc);