2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
34 __checkReturn efx_rc_t
38 __out efx_family_t *efp)
40 if (venid == EFX_PCI_VENID_SFC) {
43 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
45 * Hardware default for PF0 of uninitialised Siena.
46 * manftest must be able to cope with this device id.
48 *efp = EFX_FAMILY_SIENA;
51 case EFX_PCI_DEVID_BETHPAGE:
52 case EFX_PCI_DEVID_SIENA:
53 *efp = EFX_FAMILY_SIENA;
55 #endif /* EFSYS_OPT_SIENA */
57 #if EFSYS_OPT_HUNTINGTON
58 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
60 * Hardware default for PF0 of uninitialised Huntington.
61 * manftest must be able to cope with this device id.
63 *efp = EFX_FAMILY_HUNTINGTON;
66 case EFX_PCI_DEVID_FARMINGDALE:
67 case EFX_PCI_DEVID_GREENPORT:
68 *efp = EFX_FAMILY_HUNTINGTON;
71 case EFX_PCI_DEVID_FARMINGDALE_VF:
72 case EFX_PCI_DEVID_GREENPORT_VF:
73 *efp = EFX_FAMILY_HUNTINGTON;
75 #endif /* EFSYS_OPT_HUNTINGTON */
78 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
80 * Hardware default for PF0 of uninitialised Medford.
81 * manftest must be able to cope with this device id.
83 *efp = EFX_FAMILY_MEDFORD;
86 case EFX_PCI_DEVID_MEDFORD:
87 *efp = EFX_FAMILY_MEDFORD;
90 case EFX_PCI_DEVID_MEDFORD_VF:
91 *efp = EFX_FAMILY_MEDFORD;
93 #endif /* EFSYS_OPT_MEDFORD */
95 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
101 *efp = EFX_FAMILY_INVALID;
106 #define EFX_BIU_MAGIC0 0x01234567
107 #define EFX_BIU_MAGIC1 0xfedcba98
109 __checkReturn efx_rc_t
117 * Write magic values to scratch registers 0 and 1, then
118 * verify that the values were written correctly. Interleave
119 * the accesses to ensure that the BIU is not just reading
120 * back the cached value that was last written.
122 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
123 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
125 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
126 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
128 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
129 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
134 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
135 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
141 * Perform the same test, with the values swapped. This
142 * ensures that subsequent tests don't start with the correct
143 * values already written into the scratch registers.
145 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
146 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
148 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
149 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
151 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
152 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
157 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
158 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
172 EFSYS_PROBE1(fail1, efx_rc_t, rc);
179 static const efx_nic_ops_t __efx_nic_siena_ops = {
180 siena_nic_probe, /* eno_probe */
181 NULL, /* eno_board_cfg */
182 NULL, /* eno_set_drv_limits */
183 siena_nic_reset, /* eno_reset */
184 siena_nic_init, /* eno_init */
185 NULL, /* eno_get_vi_pool */
186 NULL, /* eno_get_bar_region */
187 siena_nic_fini, /* eno_fini */
188 siena_nic_unprobe, /* eno_unprobe */
191 #endif /* EFSYS_OPT_SIENA */
193 #if EFSYS_OPT_HUNTINGTON
195 static const efx_nic_ops_t __efx_nic_hunt_ops = {
196 ef10_nic_probe, /* eno_probe */
197 hunt_board_cfg, /* eno_board_cfg */
198 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
199 ef10_nic_reset, /* eno_reset */
200 ef10_nic_init, /* eno_init */
201 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
202 ef10_nic_get_bar_region, /* eno_get_bar_region */
203 ef10_nic_fini, /* eno_fini */
204 ef10_nic_unprobe, /* eno_unprobe */
207 #endif /* EFSYS_OPT_HUNTINGTON */
209 #if EFSYS_OPT_MEDFORD
211 static const efx_nic_ops_t __efx_nic_medford_ops = {
212 ef10_nic_probe, /* eno_probe */
213 medford_board_cfg, /* eno_board_cfg */
214 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
215 ef10_nic_reset, /* eno_reset */
216 ef10_nic_init, /* eno_init */
217 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
218 ef10_nic_get_bar_region, /* eno_get_bar_region */
219 ef10_nic_fini, /* eno_fini */
220 ef10_nic_unprobe, /* eno_unprobe */
223 #endif /* EFSYS_OPT_MEDFORD */
226 __checkReturn efx_rc_t
228 __in efx_family_t family,
229 __in efsys_identifier_t *esip,
230 __in efsys_bar_t *esbp,
231 __in efsys_lock_t *eslp,
232 __deref_out efx_nic_t **enpp)
237 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
238 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
240 /* Allocate a NIC object */
241 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
248 enp->en_magic = EFX_NIC_MAGIC;
252 case EFX_FAMILY_SIENA:
253 enp->en_enop = &__efx_nic_siena_ops;
256 EFX_FEATURE_LFSR_HASH_INSERT |
257 EFX_FEATURE_LINK_EVENTS |
258 EFX_FEATURE_PERIODIC_MAC_STATS |
260 EFX_FEATURE_LOOKAHEAD_SPLIT |
261 EFX_FEATURE_MAC_HEADER_FILTERS |
262 EFX_FEATURE_TX_SRC_FILTERS;
264 #endif /* EFSYS_OPT_SIENA */
266 #if EFSYS_OPT_HUNTINGTON
267 case EFX_FAMILY_HUNTINGTON:
268 enp->en_enop = &__efx_nic_hunt_ops;
271 EFX_FEATURE_LINK_EVENTS |
272 EFX_FEATURE_PERIODIC_MAC_STATS |
274 EFX_FEATURE_MAC_HEADER_FILTERS |
275 EFX_FEATURE_MCDI_DMA |
276 EFX_FEATURE_PIO_BUFFERS |
277 EFX_FEATURE_FW_ASSISTED_TSO |
278 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
279 EFX_FEATURE_PACKED_STREAM;
281 #endif /* EFSYS_OPT_HUNTINGTON */
283 #if EFSYS_OPT_MEDFORD
284 case EFX_FAMILY_MEDFORD:
285 enp->en_enop = &__efx_nic_medford_ops;
287 * FW_ASSISTED_TSO omitted as Medford only supports firmware
288 * assisted TSO version 2, not the v1 scheme used on Huntington.
292 EFX_FEATURE_LINK_EVENTS |
293 EFX_FEATURE_PERIODIC_MAC_STATS |
295 EFX_FEATURE_MAC_HEADER_FILTERS |
296 EFX_FEATURE_MCDI_DMA |
297 EFX_FEATURE_PIO_BUFFERS |
298 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
299 EFX_FEATURE_PACKED_STREAM;
301 #endif /* EFSYS_OPT_MEDFORD */
308 enp->en_family = family;
322 /* Free the NIC object */
323 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
326 EFSYS_PROBE1(fail1, efx_rc_t, rc);
331 __checkReturn efx_rc_t
335 const efx_nic_ops_t *enop;
338 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
340 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
341 #endif /* EFSYS_OPT_MCDI */
342 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
345 if ((rc = enop->eno_probe(enp)) != 0)
348 if ((rc = efx_phy_probe(enp)) != 0)
351 enp->en_mod_flags |= EFX_MOD_PROBE;
358 enop->eno_unprobe(enp);
361 EFSYS_PROBE1(fail1, efx_rc_t, rc);
366 __checkReturn efx_rc_t
367 efx_nic_set_drv_limits(
368 __inout efx_nic_t *enp,
369 __in efx_drv_limits_t *edlp)
371 const efx_nic_ops_t *enop = enp->en_enop;
374 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
375 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
377 if (enop->eno_set_drv_limits != NULL) {
378 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
385 EFSYS_PROBE1(fail1, efx_rc_t, rc);
390 __checkReturn efx_rc_t
391 efx_nic_get_bar_region(
393 __in efx_nic_region_t region,
394 __out uint32_t *offsetp,
397 const efx_nic_ops_t *enop = enp->en_enop;
400 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
401 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
402 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
404 if (enop->eno_get_bar_region == NULL) {
408 if ((rc = (enop->eno_get_bar_region)(enp,
409 region, offsetp, sizep)) != 0) {
419 EFSYS_PROBE1(fail1, efx_rc_t, rc);
425 __checkReturn efx_rc_t
428 __out uint32_t *evq_countp,
429 __out uint32_t *rxq_countp,
430 __out uint32_t *txq_countp)
432 const efx_nic_ops_t *enop = enp->en_enop;
433 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
436 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
437 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
438 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
440 if (enop->eno_get_vi_pool != NULL) {
441 uint32_t vi_count = 0;
443 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
446 *evq_countp = vi_count;
447 *rxq_countp = vi_count;
448 *txq_countp = vi_count;
450 /* Use NIC limits as default value */
451 *evq_countp = encp->enc_evq_limit;
452 *rxq_countp = encp->enc_rxq_limit;
453 *txq_countp = encp->enc_txq_limit;
459 EFSYS_PROBE1(fail1, efx_rc_t, rc);
465 __checkReturn efx_rc_t
469 const efx_nic_ops_t *enop = enp->en_enop;
472 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
473 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
475 if (enp->en_mod_flags & EFX_MOD_NIC) {
480 if ((rc = enop->eno_init(enp)) != 0)
483 enp->en_mod_flags |= EFX_MOD_NIC;
490 EFSYS_PROBE1(fail1, efx_rc_t, rc);
499 const efx_nic_ops_t *enop = enp->en_enop;
501 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
502 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
503 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
504 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
505 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
506 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
507 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
511 enp->en_mod_flags &= ~EFX_MOD_NIC;
518 const efx_nic_ops_t *enop = enp->en_enop;
520 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
522 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
523 #endif /* EFSYS_OPT_MCDI */
524 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
525 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
526 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
527 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
528 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
529 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
531 efx_phy_unprobe(enp);
533 enop->eno_unprobe(enp);
535 enp->en_mod_flags &= ~EFX_MOD_PROBE;
542 efsys_identifier_t *esip = enp->en_esip;
544 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
545 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
547 enp->en_family = EFX_FAMILY_INVALID;
556 /* Free the NIC object */
557 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
560 __checkReturn efx_rc_t
564 const efx_nic_ops_t *enop = enp->en_enop;
565 unsigned int mod_flags;
568 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
569 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
571 * All modules except the MCDI, PROBE, NVRAM, VPD, MON
572 * (which we do not reset here) must have been shut down or never
575 * A rule of thumb here is: If the controller or MC reboots, is *any*
576 * state lost. If it's lost and needs reapplying, then the module
577 * *must* not be initialised during the reset.
579 mod_flags = enp->en_mod_flags;
580 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
581 EFX_MOD_VPD | EFX_MOD_MON);
582 EFSYS_ASSERT3U(mod_flags, ==, 0);
583 if (mod_flags != 0) {
588 if ((rc = enop->eno_reset(enp)) != 0)
596 EFSYS_PROBE1(fail1, efx_rc_t, rc);
601 const efx_nic_cfg_t *
605 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
607 return (&(enp->en_nic_cfg));
610 __checkReturn efx_rc_t
611 efx_nic_calculate_pcie_link_bandwidth(
612 __in uint32_t pcie_link_width,
613 __in uint32_t pcie_link_gen,
614 __out uint32_t *bandwidth_mbpsp)
616 uint32_t lane_bandwidth;
617 uint32_t total_bandwidth;
620 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
621 !ISP2(pcie_link_width)) {
626 switch (pcie_link_gen) {
627 case EFX_PCIE_LINK_SPEED_GEN1:
628 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
629 lane_bandwidth = 2000;
631 case EFX_PCIE_LINK_SPEED_GEN2:
632 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
633 lane_bandwidth = 4000;
635 case EFX_PCIE_LINK_SPEED_GEN3:
636 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
637 lane_bandwidth = 7877;
644 total_bandwidth = lane_bandwidth * pcie_link_width;
645 *bandwidth_mbpsp = total_bandwidth;
652 EFSYS_PROBE1(fail1, efx_rc_t, rc);
658 __checkReturn efx_rc_t
659 efx_nic_check_pcie_link_speed(
661 __in uint32_t pcie_link_width,
662 __in uint32_t pcie_link_gen,
663 __out efx_pcie_link_performance_t *resultp)
665 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
667 efx_pcie_link_performance_t result;
670 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
671 (pcie_link_width == 0) || (pcie_link_width == 32) ||
672 (pcie_link_gen == 0)) {
674 * No usable info on what is required and/or in use. In virtual
675 * machines, sometimes the PCIe link width is reported as 0 or
676 * 32, or the speed as 0.
678 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
682 /* Calculate the available bandwidth in megabits per second */
683 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
684 pcie_link_gen, &bandwidth);
688 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
689 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
690 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
691 /* The link provides enough bandwidth but not optimal latency */
692 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
694 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
703 EFSYS_PROBE1(fail1, efx_rc_t, rc);