1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
11 __checkReturn efx_rc_t
15 __out efx_family_t *efp,
16 __out unsigned int *membarp)
18 if (venid == EFX_PCI_VENID_SFC) {
21 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
23 * Hardware default for PF0 of uninitialised Siena.
24 * manftest must be able to cope with this device id.
26 case EFX_PCI_DEVID_BETHPAGE:
27 case EFX_PCI_DEVID_SIENA:
28 *efp = EFX_FAMILY_SIENA;
29 *membarp = EFX_MEM_BAR_SIENA;
31 #endif /* EFSYS_OPT_SIENA */
33 #if EFSYS_OPT_HUNTINGTON
34 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
36 * Hardware default for PF0 of uninitialised Huntington.
37 * manftest must be able to cope with this device id.
39 case EFX_PCI_DEVID_FARMINGDALE:
40 case EFX_PCI_DEVID_GREENPORT:
41 *efp = EFX_FAMILY_HUNTINGTON;
42 *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
45 case EFX_PCI_DEVID_FARMINGDALE_VF:
46 case EFX_PCI_DEVID_GREENPORT_VF:
47 *efp = EFX_FAMILY_HUNTINGTON;
48 *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
55 * Hardware default for PF0 of uninitialised Medford.
56 * manftest must be able to cope with this device id.
58 case EFX_PCI_DEVID_MEDFORD:
59 *efp = EFX_FAMILY_MEDFORD;
60 *membarp = EFX_MEM_BAR_MEDFORD_PF;
63 case EFX_PCI_DEVID_MEDFORD_VF:
64 *efp = EFX_FAMILY_MEDFORD;
65 *membarp = EFX_MEM_BAR_MEDFORD_VF;
67 #endif /* EFSYS_OPT_MEDFORD */
69 #if EFSYS_OPT_MEDFORD2
70 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
72 * Hardware default for PF0 of uninitialised Medford2.
73 * manftest must be able to cope with this device id.
75 case EFX_PCI_DEVID_MEDFORD2:
76 case EFX_PCI_DEVID_MEDFORD2_VF:
77 *efp = EFX_FAMILY_MEDFORD2;
78 *membarp = EFX_MEM_BAR_MEDFORD2;
80 #endif /* EFSYS_OPT_MEDFORD2 */
82 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
88 *efp = EFX_FAMILY_INVALID;
95 static const efx_nic_ops_t __efx_nic_siena_ops = {
96 siena_nic_probe, /* eno_probe */
97 NULL, /* eno_board_cfg */
98 NULL, /* eno_set_drv_limits */
99 siena_nic_reset, /* eno_reset */
100 siena_nic_init, /* eno_init */
101 NULL, /* eno_get_vi_pool */
102 NULL, /* eno_get_bar_region */
103 NULL, /* eno_hw_unavailable */
104 NULL, /* eno_set_hw_unavailable */
106 siena_nic_register_test, /* eno_register_test */
107 #endif /* EFSYS_OPT_DIAG */
108 siena_nic_fini, /* eno_fini */
109 siena_nic_unprobe, /* eno_unprobe */
112 #endif /* EFSYS_OPT_SIENA */
114 #if EFSYS_OPT_HUNTINGTON
116 static const efx_nic_ops_t __efx_nic_hunt_ops = {
117 ef10_nic_probe, /* eno_probe */
118 hunt_board_cfg, /* eno_board_cfg */
119 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
120 ef10_nic_reset, /* eno_reset */
121 ef10_nic_init, /* eno_init */
122 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
123 ef10_nic_get_bar_region, /* eno_get_bar_region */
124 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
125 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
127 ef10_nic_register_test, /* eno_register_test */
128 #endif /* EFSYS_OPT_DIAG */
129 ef10_nic_fini, /* eno_fini */
130 ef10_nic_unprobe, /* eno_unprobe */
133 #endif /* EFSYS_OPT_HUNTINGTON */
135 #if EFSYS_OPT_MEDFORD
137 static const efx_nic_ops_t __efx_nic_medford_ops = {
138 ef10_nic_probe, /* eno_probe */
139 medford_board_cfg, /* eno_board_cfg */
140 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
141 ef10_nic_reset, /* eno_reset */
142 ef10_nic_init, /* eno_init */
143 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
144 ef10_nic_get_bar_region, /* eno_get_bar_region */
145 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
146 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
148 ef10_nic_register_test, /* eno_register_test */
149 #endif /* EFSYS_OPT_DIAG */
150 ef10_nic_fini, /* eno_fini */
151 ef10_nic_unprobe, /* eno_unprobe */
154 #endif /* EFSYS_OPT_MEDFORD */
156 #if EFSYS_OPT_MEDFORD2
158 static const efx_nic_ops_t __efx_nic_medford2_ops = {
159 ef10_nic_probe, /* eno_probe */
160 medford2_board_cfg, /* eno_board_cfg */
161 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
162 ef10_nic_reset, /* eno_reset */
163 ef10_nic_init, /* eno_init */
164 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
165 ef10_nic_get_bar_region, /* eno_get_bar_region */
166 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
167 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
169 ef10_nic_register_test, /* eno_register_test */
170 #endif /* EFSYS_OPT_DIAG */
171 ef10_nic_fini, /* eno_fini */
172 ef10_nic_unprobe, /* eno_unprobe */
175 #endif /* EFSYS_OPT_MEDFORD2 */
178 __checkReturn efx_rc_t
180 __in efx_family_t family,
181 __in efsys_identifier_t *esip,
182 __in efsys_bar_t *esbp,
183 __in efsys_lock_t *eslp,
184 __deref_out efx_nic_t **enpp)
189 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
190 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
192 /* Allocate a NIC object */
193 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
200 enp->en_magic = EFX_NIC_MAGIC;
204 case EFX_FAMILY_SIENA:
205 enp->en_enop = &__efx_nic_siena_ops;
208 EFX_FEATURE_LFSR_HASH_INSERT |
209 EFX_FEATURE_LINK_EVENTS |
210 EFX_FEATURE_PERIODIC_MAC_STATS |
212 EFX_FEATURE_LOOKAHEAD_SPLIT |
213 EFX_FEATURE_MAC_HEADER_FILTERS |
214 EFX_FEATURE_TX_SRC_FILTERS;
216 #endif /* EFSYS_OPT_SIENA */
218 #if EFSYS_OPT_HUNTINGTON
219 case EFX_FAMILY_HUNTINGTON:
220 enp->en_enop = &__efx_nic_hunt_ops;
223 EFX_FEATURE_LINK_EVENTS |
224 EFX_FEATURE_PERIODIC_MAC_STATS |
226 EFX_FEATURE_MAC_HEADER_FILTERS |
227 EFX_FEATURE_MCDI_DMA |
228 EFX_FEATURE_PIO_BUFFERS |
229 EFX_FEATURE_FW_ASSISTED_TSO |
230 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
231 EFX_FEATURE_PACKED_STREAM |
232 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
234 #endif /* EFSYS_OPT_HUNTINGTON */
236 #if EFSYS_OPT_MEDFORD
237 case EFX_FAMILY_MEDFORD:
238 enp->en_enop = &__efx_nic_medford_ops;
240 * FW_ASSISTED_TSO omitted as Medford only supports firmware
241 * assisted TSO version 2, not the v1 scheme used on Huntington.
245 EFX_FEATURE_LINK_EVENTS |
246 EFX_FEATURE_PERIODIC_MAC_STATS |
248 EFX_FEATURE_MAC_HEADER_FILTERS |
249 EFX_FEATURE_MCDI_DMA |
250 EFX_FEATURE_PIO_BUFFERS |
251 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
252 EFX_FEATURE_PACKED_STREAM |
253 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
255 #endif /* EFSYS_OPT_MEDFORD */
257 #if EFSYS_OPT_MEDFORD2
258 case EFX_FAMILY_MEDFORD2:
259 enp->en_enop = &__efx_nic_medford2_ops;
262 EFX_FEATURE_LINK_EVENTS |
263 EFX_FEATURE_PERIODIC_MAC_STATS |
265 EFX_FEATURE_MAC_HEADER_FILTERS |
266 EFX_FEATURE_MCDI_DMA |
267 EFX_FEATURE_PIO_BUFFERS |
268 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
269 EFX_FEATURE_PACKED_STREAM |
270 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
272 #endif /* EFSYS_OPT_MEDFORD2 */
279 enp->en_family = family;
293 /* Free the NIC object */
294 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
297 EFSYS_PROBE1(fail1, efx_rc_t, rc);
302 __checkReturn efx_rc_t
305 __in efx_fw_variant_t efv)
307 const efx_nic_ops_t *enop;
310 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
312 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
313 #endif /* EFSYS_OPT_MCDI */
314 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
316 /* Ensure FW variant codes match with MC_CMD_FW codes */
317 EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
318 MC_CMD_FW_FULL_FEATURED);
319 EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
320 MC_CMD_FW_LOW_LATENCY);
321 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
322 MC_CMD_FW_PACKED_STREAM);
323 EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
324 MC_CMD_FW_HIGH_TX_RATE);
325 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
326 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
327 EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
328 MC_CMD_FW_RULES_ENGINE);
329 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
331 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
332 (int)MC_CMD_FW_DONT_CARE);
337 if ((rc = enop->eno_probe(enp)) != 0)
340 if ((rc = efx_phy_probe(enp)) != 0)
343 enp->en_mod_flags |= EFX_MOD_PROBE;
350 enop->eno_unprobe(enp);
353 EFSYS_PROBE1(fail1, efx_rc_t, rc);
358 __checkReturn efx_rc_t
359 efx_nic_set_drv_limits(
360 __inout efx_nic_t *enp,
361 __in efx_drv_limits_t *edlp)
363 const efx_nic_ops_t *enop = enp->en_enop;
366 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
367 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
369 if (enop->eno_set_drv_limits != NULL) {
370 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
377 EFSYS_PROBE1(fail1, efx_rc_t, rc);
382 __checkReturn efx_rc_t
383 efx_nic_get_bar_region(
385 __in efx_nic_region_t region,
386 __out uint32_t *offsetp,
389 const efx_nic_ops_t *enop = enp->en_enop;
392 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
393 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
394 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
396 if (enop->eno_get_bar_region == NULL) {
400 if ((rc = (enop->eno_get_bar_region)(enp,
401 region, offsetp, sizep)) != 0) {
411 EFSYS_PROBE1(fail1, efx_rc_t, rc);
417 __checkReturn efx_rc_t
420 __out uint32_t *evq_countp,
421 __out uint32_t *rxq_countp,
422 __out uint32_t *txq_countp)
424 const efx_nic_ops_t *enop = enp->en_enop;
425 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
428 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
429 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
430 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
432 if (enop->eno_get_vi_pool != NULL) {
433 uint32_t vi_count = 0;
435 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
438 *evq_countp = vi_count;
439 *rxq_countp = vi_count;
440 *txq_countp = vi_count;
442 /* Use NIC limits as default value */
443 *evq_countp = encp->enc_evq_limit;
444 *rxq_countp = encp->enc_rxq_limit;
445 *txq_countp = encp->enc_txq_limit;
451 EFSYS_PROBE1(fail1, efx_rc_t, rc);
457 __checkReturn efx_rc_t
461 const efx_nic_ops_t *enop = enp->en_enop;
464 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
465 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
467 if (enp->en_mod_flags & EFX_MOD_NIC) {
472 if ((rc = enop->eno_init(enp)) != 0)
475 enp->en_mod_flags |= EFX_MOD_NIC;
482 EFSYS_PROBE1(fail1, efx_rc_t, rc);
491 const efx_nic_ops_t *enop = enp->en_enop;
493 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
494 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
495 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
496 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
497 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
498 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
499 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
503 enp->en_mod_flags &= ~EFX_MOD_NIC;
510 const efx_nic_ops_t *enop = enp->en_enop;
512 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
514 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
515 #endif /* EFSYS_OPT_MCDI */
516 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
517 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
518 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
519 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
520 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
521 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
523 efx_phy_unprobe(enp);
525 enop->eno_unprobe(enp);
527 enp->en_mod_flags &= ~EFX_MOD_PROBE;
534 efsys_identifier_t *esip = enp->en_esip;
536 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
537 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
539 enp->en_family = EFX_FAMILY_INVALID;
548 /* Free the NIC object */
549 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
552 __checkReturn efx_rc_t
556 const efx_nic_ops_t *enop = enp->en_enop;
557 unsigned int mod_flags;
560 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
561 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
563 * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
564 * (which we do not reset here) must have been shut down or never
567 * A rule of thumb here is: If the controller or MC reboots, is *any*
568 * state lost. If it's lost and needs reapplying, then the module
569 * *must* not be initialised during the reset.
571 mod_flags = enp->en_mod_flags;
572 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
573 EFX_MOD_VPD | EFX_MOD_MON);
575 mod_flags &= ~EFX_MOD_TUNNEL;
576 #endif /* EFSYS_OPT_TUNNEL */
577 EFSYS_ASSERT3U(mod_flags, ==, 0);
578 if (mod_flags != 0) {
583 if ((rc = enop->eno_reset(enp)) != 0)
591 EFSYS_PROBE1(fail1, efx_rc_t, rc);
596 const efx_nic_cfg_t *
600 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
601 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
603 return (&(enp->en_nic_cfg));
606 __checkReturn efx_rc_t
607 efx_nic_get_fw_version(
609 __out efx_nic_fw_info_t *enfip)
611 uint16_t mc_fw_version[4];
619 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
620 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
622 /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
623 EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
624 MC_CMD_GET_CAPABILITIES_OUT_RXDP);
625 EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
626 MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
627 EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
628 MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
629 EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
630 MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
631 EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
632 MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
634 rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
638 rc = efx_mcdi_get_capabilities(enp, NULL,
639 &enfip->enfi_rx_dpcpu_fw_id,
640 &enfip->enfi_tx_dpcpu_fw_id,
643 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
644 } else if (rc == ENOTSUP) {
645 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
646 enfip->enfi_rx_dpcpu_fw_id = 0;
647 enfip->enfi_tx_dpcpu_fw_id = 0;
652 memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
653 sizeof (mc_fw_version));
662 EFSYS_PROBE1(fail1, efx_rc_t, rc);
667 __checkReturn boolean_t
668 efx_nic_hw_unavailable(
671 const efx_nic_ops_t *enop = enp->en_enop;
673 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
674 /* NOTE: can be used by MCDI before NIC probe */
676 if (enop->eno_hw_unavailable != NULL) {
677 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
688 efx_nic_set_hw_unavailable(
691 const efx_nic_ops_t *enop = enp->en_enop;
693 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
695 if (enop->eno_set_hw_unavailable != NULL)
696 enop->eno_set_hw_unavailable(enp);
702 __checkReturn efx_rc_t
703 efx_nic_register_test(
706 const efx_nic_ops_t *enop = enp->en_enop;
709 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
710 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
711 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
713 if ((rc = enop->eno_register_test(enp)) != 0)
719 EFSYS_PROBE1(fail1, efx_rc_t, rc);
724 #endif /* EFSYS_OPT_DIAG */
726 #if EFSYS_OPT_LOOPBACK
730 __in efx_loopback_kind_t loopback_kind,
731 __out efx_qword_t *maskp)
735 EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
736 EFSYS_ASSERT(maskp != NULL);
738 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
739 #define LOOPBACK_CHECK(_mcdi, _efx) \
740 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
742 LOOPBACK_CHECK(NONE, OFF);
743 LOOPBACK_CHECK(DATA, DATA);
744 LOOPBACK_CHECK(GMAC, GMAC);
745 LOOPBACK_CHECK(XGMII, XGMII);
746 LOOPBACK_CHECK(XGXS, XGXS);
747 LOOPBACK_CHECK(XAUI, XAUI);
748 LOOPBACK_CHECK(GMII, GMII);
749 LOOPBACK_CHECK(SGMII, SGMII);
750 LOOPBACK_CHECK(XGBR, XGBR);
751 LOOPBACK_CHECK(XFI, XFI);
752 LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
753 LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
754 LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
755 LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
756 LOOPBACK_CHECK(GPHY, GPHY);
757 LOOPBACK_CHECK(PHYXS, PHY_XS);
758 LOOPBACK_CHECK(PCS, PCS);
759 LOOPBACK_CHECK(PMAPMD, PMA_PMD);
760 LOOPBACK_CHECK(XPORT, XPORT);
761 LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
762 LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
763 LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
764 LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
765 LOOPBACK_CHECK(GMII_WS, GMII_WS);
766 LOOPBACK_CHECK(XFI_WS, XFI_WS);
767 LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
768 LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
769 LOOPBACK_CHECK(PMA_INT, PMA_INT);
770 LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
771 LOOPBACK_CHECK(SD_FAR, SD_FAR);
772 LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
773 LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
774 LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
775 LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
776 LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
777 LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
778 LOOPBACK_CHECK(DATA_WS, DATA_WS);
779 LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
780 #undef LOOPBACK_CHECK
782 /* Build bitmask of possible loopback types */
783 EFX_ZERO_QWORD(mask);
785 if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
786 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
787 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
790 if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
791 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
793 * The "MAC" grouping has historically been used by drivers to
794 * mean loopbacks supported by on-chip hardware. Keep that
795 * meaning here, and include on-chip PHY layer loopbacks.
797 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
798 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
799 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
800 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
801 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
802 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
803 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
804 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
805 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
806 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
807 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
808 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
809 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
810 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
811 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
812 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
815 if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
816 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
818 * The "PHY" grouping has historically been used by drivers to
819 * mean loopbacks supported by off-chip hardware. Keep that
822 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
823 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
824 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
825 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
831 __checkReturn efx_rc_t
832 efx_mcdi_get_loopback_modes(
835 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
837 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
838 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
843 req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
844 req.emr_in_buf = payload;
845 req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
846 req.emr_out_buf = payload;
847 req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
849 efx_mcdi_execute(enp, &req);
851 if (req.emr_rc != 0) {
856 if (req.emr_out_length_used <
857 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
858 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
864 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
865 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
867 efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
870 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
872 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
873 EFX_AND_QWORD(modes, mask);
874 encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
876 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
877 EFX_AND_QWORD(modes, mask);
878 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
880 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
881 EFX_AND_QWORD(modes, mask);
882 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
884 if (req.emr_out_length_used >=
885 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
886 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
887 /* Response includes 40G loopback modes */
888 modes = *MCDI_OUT2(req, efx_qword_t,
889 GET_LOOPBACK_MODES_OUT_40G);
890 EFX_AND_QWORD(modes, mask);
891 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
894 if (req.emr_out_length_used >=
895 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
896 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
897 /* Response includes 25G loopback modes */
898 modes = *MCDI_OUT2(req, efx_qword_t,
899 GET_LOOPBACK_MODES_OUT_V2_25G);
900 EFX_AND_QWORD(modes, mask);
901 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
904 if (req.emr_out_length_used >=
905 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
906 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
907 /* Response includes 50G loopback modes */
908 modes = *MCDI_OUT2(req, efx_qword_t,
909 GET_LOOPBACK_MODES_OUT_V2_50G);
910 EFX_AND_QWORD(modes, mask);
911 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
914 if (req.emr_out_length_used >=
915 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
916 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
917 /* Response includes 100G loopback modes */
918 modes = *MCDI_OUT2(req, efx_qword_t,
919 GET_LOOPBACK_MODES_OUT_V2_100G);
920 EFX_AND_QWORD(modes, mask);
921 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
924 EFX_ZERO_QWORD(modes);
925 EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
926 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
927 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
928 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
929 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
930 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
931 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
932 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
933 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
940 EFSYS_PROBE1(fail1, efx_rc_t, rc);
945 #endif /* EFSYS_OPT_LOOPBACK */
947 __checkReturn efx_rc_t
948 efx_nic_calculate_pcie_link_bandwidth(
949 __in uint32_t pcie_link_width,
950 __in uint32_t pcie_link_gen,
951 __out uint32_t *bandwidth_mbpsp)
953 uint32_t lane_bandwidth;
954 uint32_t total_bandwidth;
957 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
958 !ISP2(pcie_link_width)) {
963 switch (pcie_link_gen) {
964 case EFX_PCIE_LINK_SPEED_GEN1:
965 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
966 lane_bandwidth = 2000;
968 case EFX_PCIE_LINK_SPEED_GEN2:
969 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
970 lane_bandwidth = 4000;
972 case EFX_PCIE_LINK_SPEED_GEN3:
973 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
974 lane_bandwidth = 7877;
981 total_bandwidth = lane_bandwidth * pcie_link_width;
982 *bandwidth_mbpsp = total_bandwidth;
989 EFSYS_PROBE1(fail1, efx_rc_t, rc);
994 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
996 __checkReturn efx_rc_t
997 efx_nic_get_fw_subvariant(
999 __out efx_nic_fw_subvariant_t *subvariantp)
1004 rc = efx_mcdi_get_nic_global(enp,
1005 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1009 /* Mapping is not required since values match MCDI */
1010 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1011 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1012 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1013 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1016 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1017 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1018 *subvariantp = value;
1031 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1036 __checkReturn efx_rc_t
1037 efx_nic_set_fw_subvariant(
1038 __in efx_nic_t *enp,
1039 __in efx_nic_fw_subvariant_t subvariant)
1043 switch (subvariant) {
1044 case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1045 case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1046 /* Mapping is not required since values match MCDI */
1053 rc = efx_mcdi_set_nic_global(enp,
1054 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1064 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1069 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1071 __checkReturn efx_rc_t
1072 efx_nic_check_pcie_link_speed(
1073 __in efx_nic_t *enp,
1074 __in uint32_t pcie_link_width,
1075 __in uint32_t pcie_link_gen,
1076 __out efx_pcie_link_performance_t *resultp)
1078 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1080 efx_pcie_link_performance_t result;
1083 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1084 (pcie_link_width == 0) || (pcie_link_width == 32) ||
1085 (pcie_link_gen == 0)) {
1087 * No usable info on what is required and/or in use. In virtual
1088 * machines, sometimes the PCIe link width is reported as 0 or
1089 * 32, or the speed as 0.
1091 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1095 /* Calculate the available bandwidth in megabits per second */
1096 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1097 pcie_link_gen, &bandwidth);
1101 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1102 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1103 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1104 /* The link provides enough bandwidth but not optimal latency */
1105 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1107 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1116 EFSYS_PROBE1(fail1, efx_rc_t, rc);