2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
34 __checkReturn efx_rc_t
38 __out efx_family_t *efp)
40 if (venid == EFX_PCI_VENID_SFC) {
43 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
45 * Hardware default for PF0 of uninitialised Siena.
46 * manftest must be able to cope with this device id.
48 *efp = EFX_FAMILY_SIENA;
51 case EFX_PCI_DEVID_BETHPAGE:
52 case EFX_PCI_DEVID_SIENA:
53 *efp = EFX_FAMILY_SIENA;
55 #endif /* EFSYS_OPT_SIENA */
57 #if EFSYS_OPT_HUNTINGTON
58 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
60 * Hardware default for PF0 of uninitialised Huntington.
61 * manftest must be able to cope with this device id.
63 *efp = EFX_FAMILY_HUNTINGTON;
66 case EFX_PCI_DEVID_FARMINGDALE:
67 case EFX_PCI_DEVID_GREENPORT:
68 *efp = EFX_FAMILY_HUNTINGTON;
71 case EFX_PCI_DEVID_FARMINGDALE_VF:
72 case EFX_PCI_DEVID_GREENPORT_VF:
73 *efp = EFX_FAMILY_HUNTINGTON;
75 #endif /* EFSYS_OPT_HUNTINGTON */
77 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
83 *efp = EFX_FAMILY_INVALID;
88 #define EFX_BIU_MAGIC0 0x01234567
89 #define EFX_BIU_MAGIC1 0xfedcba98
91 __checkReturn efx_rc_t
99 * Write magic values to scratch registers 0 and 1, then
100 * verify that the values were written correctly. Interleave
101 * the accesses to ensure that the BIU is not just reading
102 * back the cached value that was last written.
104 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
105 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
107 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
108 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
110 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
111 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
116 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
117 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
123 * Perform the same test, with the values swapped. This
124 * ensures that subsequent tests don't start with the correct
125 * values already written into the scratch registers.
127 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
128 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
130 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
131 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
133 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
134 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
139 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
140 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
154 EFSYS_PROBE1(fail1, efx_rc_t, rc);
161 static const efx_nic_ops_t __efx_nic_siena_ops = {
162 siena_nic_probe, /* eno_probe */
163 NULL, /* eno_board_cfg */
164 NULL, /* eno_set_drv_limits */
165 siena_nic_reset, /* eno_reset */
166 siena_nic_init, /* eno_init */
167 NULL, /* eno_get_vi_pool */
168 NULL, /* eno_get_bar_region */
169 siena_nic_fini, /* eno_fini */
170 siena_nic_unprobe, /* eno_unprobe */
173 #endif /* EFSYS_OPT_SIENA */
175 #if EFSYS_OPT_HUNTINGTON
177 static const efx_nic_ops_t __efx_nic_hunt_ops = {
178 ef10_nic_probe, /* eno_probe */
179 hunt_board_cfg, /* eno_board_cfg */
180 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
181 ef10_nic_reset, /* eno_reset */
182 ef10_nic_init, /* eno_init */
183 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
184 ef10_nic_get_bar_region, /* eno_get_bar_region */
185 ef10_nic_fini, /* eno_fini */
186 ef10_nic_unprobe, /* eno_unprobe */
189 #endif /* EFSYS_OPT_HUNTINGTON */
192 __checkReturn efx_rc_t
194 __in efx_family_t family,
195 __in efsys_identifier_t *esip,
196 __in efsys_bar_t *esbp,
197 __in efsys_lock_t *eslp,
198 __deref_out efx_nic_t **enpp)
203 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
204 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
206 /* Allocate a NIC object */
207 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
214 enp->en_magic = EFX_NIC_MAGIC;
218 case EFX_FAMILY_SIENA:
219 enp->en_enop = &__efx_nic_siena_ops;
222 EFX_FEATURE_LFSR_HASH_INSERT |
223 EFX_FEATURE_LINK_EVENTS |
224 EFX_FEATURE_PERIODIC_MAC_STATS |
226 EFX_FEATURE_LOOKAHEAD_SPLIT |
227 EFX_FEATURE_MAC_HEADER_FILTERS |
228 EFX_FEATURE_TX_SRC_FILTERS;
230 #endif /* EFSYS_OPT_SIENA */
232 #if EFSYS_OPT_HUNTINGTON
233 case EFX_FAMILY_HUNTINGTON:
234 enp->en_enop = &__efx_nic_hunt_ops;
237 EFX_FEATURE_LINK_EVENTS |
238 EFX_FEATURE_PERIODIC_MAC_STATS |
240 EFX_FEATURE_MAC_HEADER_FILTERS |
241 EFX_FEATURE_MCDI_DMA |
242 EFX_FEATURE_PIO_BUFFERS |
243 EFX_FEATURE_FW_ASSISTED_TSO |
244 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
245 EFX_FEATURE_PACKED_STREAM;
247 #endif /* EFSYS_OPT_HUNTINGTON */
254 enp->en_family = family;
268 /* Free the NIC object */
269 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
272 EFSYS_PROBE1(fail1, efx_rc_t, rc);
277 __checkReturn efx_rc_t
281 const efx_nic_ops_t *enop;
284 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
286 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
287 #endif /* EFSYS_OPT_MCDI */
288 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
291 if ((rc = enop->eno_probe(enp)) != 0)
294 if ((rc = efx_phy_probe(enp)) != 0)
297 enp->en_mod_flags |= EFX_MOD_PROBE;
304 enop->eno_unprobe(enp);
307 EFSYS_PROBE1(fail1, efx_rc_t, rc);
312 __checkReturn efx_rc_t
313 efx_nic_set_drv_limits(
314 __inout efx_nic_t *enp,
315 __in efx_drv_limits_t *edlp)
317 const efx_nic_ops_t *enop = enp->en_enop;
320 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
321 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
323 if (enop->eno_set_drv_limits != NULL) {
324 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
331 EFSYS_PROBE1(fail1, efx_rc_t, rc);
336 __checkReturn efx_rc_t
337 efx_nic_get_bar_region(
339 __in efx_nic_region_t region,
340 __out uint32_t *offsetp,
343 const efx_nic_ops_t *enop = enp->en_enop;
346 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
347 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
348 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
350 if (enop->eno_get_bar_region == NULL) {
354 if ((rc = (enop->eno_get_bar_region)(enp,
355 region, offsetp, sizep)) != 0) {
365 EFSYS_PROBE1(fail1, efx_rc_t, rc);
371 __checkReturn efx_rc_t
374 __out uint32_t *evq_countp,
375 __out uint32_t *rxq_countp,
376 __out uint32_t *txq_countp)
378 const efx_nic_ops_t *enop = enp->en_enop;
379 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
382 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
383 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
384 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
386 if (enop->eno_get_vi_pool != NULL) {
387 uint32_t vi_count = 0;
389 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
392 *evq_countp = vi_count;
393 *rxq_countp = vi_count;
394 *txq_countp = vi_count;
396 /* Use NIC limits as default value */
397 *evq_countp = encp->enc_evq_limit;
398 *rxq_countp = encp->enc_rxq_limit;
399 *txq_countp = encp->enc_txq_limit;
405 EFSYS_PROBE1(fail1, efx_rc_t, rc);
411 __checkReturn efx_rc_t
415 const efx_nic_ops_t *enop = enp->en_enop;
418 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
419 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
421 if (enp->en_mod_flags & EFX_MOD_NIC) {
426 if ((rc = enop->eno_init(enp)) != 0)
429 enp->en_mod_flags |= EFX_MOD_NIC;
436 EFSYS_PROBE1(fail1, efx_rc_t, rc);
445 const efx_nic_ops_t *enop = enp->en_enop;
447 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
448 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
449 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
450 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
451 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
452 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
453 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
457 enp->en_mod_flags &= ~EFX_MOD_NIC;
464 const efx_nic_ops_t *enop = enp->en_enop;
466 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
468 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
469 #endif /* EFSYS_OPT_MCDI */
470 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
471 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
472 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
473 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
474 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
475 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
477 efx_phy_unprobe(enp);
479 enop->eno_unprobe(enp);
481 enp->en_mod_flags &= ~EFX_MOD_PROBE;
488 efsys_identifier_t *esip = enp->en_esip;
490 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
491 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
493 enp->en_family = EFX_FAMILY_INVALID;
502 /* Free the NIC object */
503 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
506 __checkReturn efx_rc_t
510 const efx_nic_ops_t *enop = enp->en_enop;
511 unsigned int mod_flags;
514 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
515 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
517 * All modules except the MCDI, PROBE, NVRAM, VPD, MON
518 * (which we do not reset here) must have been shut down or never
521 * A rule of thumb here is: If the controller or MC reboots, is *any*
522 * state lost. If it's lost and needs reapplying, then the module
523 * *must* not be initialised during the reset.
525 mod_flags = enp->en_mod_flags;
526 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
527 EFX_MOD_VPD | EFX_MOD_MON);
528 EFSYS_ASSERT3U(mod_flags, ==, 0);
529 if (mod_flags != 0) {
534 if ((rc = enop->eno_reset(enp)) != 0)
542 EFSYS_PROBE1(fail1, efx_rc_t, rc);
547 const efx_nic_cfg_t *
551 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
553 return (&(enp->en_nic_cfg));
556 __checkReturn efx_rc_t
557 efx_nic_calculate_pcie_link_bandwidth(
558 __in uint32_t pcie_link_width,
559 __in uint32_t pcie_link_gen,
560 __out uint32_t *bandwidth_mbpsp)
562 uint32_t lane_bandwidth;
563 uint32_t total_bandwidth;
566 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
567 !ISP2(pcie_link_width)) {
572 switch (pcie_link_gen) {
573 case EFX_PCIE_LINK_SPEED_GEN1:
574 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
575 lane_bandwidth = 2000;
577 case EFX_PCIE_LINK_SPEED_GEN2:
578 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
579 lane_bandwidth = 4000;
581 case EFX_PCIE_LINK_SPEED_GEN3:
582 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
583 lane_bandwidth = 7877;
590 total_bandwidth = lane_bandwidth * pcie_link_width;
591 *bandwidth_mbpsp = total_bandwidth;
598 EFSYS_PROBE1(fail1, efx_rc_t, rc);
604 __checkReturn efx_rc_t
605 efx_nic_check_pcie_link_speed(
607 __in uint32_t pcie_link_width,
608 __in uint32_t pcie_link_gen,
609 __out efx_pcie_link_performance_t *resultp)
611 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
613 efx_pcie_link_performance_t result;
616 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
617 (pcie_link_width == 0) || (pcie_link_width == 32) ||
618 (pcie_link_gen == 0)) {
620 * No usable info on what is required and/or in use. In virtual
621 * machines, sometimes the PCIe link width is reported as 0 or
622 * 32, or the speed as 0.
624 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
628 /* Calculate the available bandwidth in megabits per second */
629 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
630 pcie_link_gen, &bandwidth);
634 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
635 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
636 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
637 /* The link provides enough bandwidth but not optimal latency */
638 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
640 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
649 EFSYS_PROBE1(fail1, efx_rc_t, rc);