2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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34 __checkReturn efx_rc_t
38 __out efx_family_t *efp)
40 if (venid == EFX_PCI_VENID_SFC) {
43 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
49 *efp = EFX_FAMILY_INVALID;
54 #define EFX_BIU_MAGIC0 0x01234567
55 #define EFX_BIU_MAGIC1 0xfedcba98
57 __checkReturn efx_rc_t
65 * Write magic values to scratch registers 0 and 1, then
66 * verify that the values were written correctly. Interleave
67 * the accesses to ensure that the BIU is not just reading
68 * back the cached value that was last written.
70 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
71 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
73 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
74 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
76 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
77 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
82 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
83 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
89 * Perform the same test, with the values swapped. This
90 * ensures that subsequent tests don't start with the correct
91 * values already written into the scratch registers.
93 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
94 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
96 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
97 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
99 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
100 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
105 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
106 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
126 __checkReturn efx_rc_t
128 __in efx_family_t family,
129 __in efsys_identifier_t *esip,
130 __in efsys_bar_t *esbp,
131 __in efsys_lock_t *eslp,
132 __deref_out efx_nic_t **enpp)
137 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
138 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
140 /* Allocate a NIC object */
141 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
148 enp->en_magic = EFX_NIC_MAGIC;
157 enp->en_family = family;
171 /* Free the NIC object */
172 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
175 EFSYS_PROBE1(fail1, efx_rc_t, rc);
180 __checkReturn efx_rc_t
184 const efx_nic_ops_t *enop;
187 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
188 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
191 if ((rc = enop->eno_probe(enp)) != 0)
194 if ((rc = efx_phy_probe(enp)) != 0)
197 enp->en_mod_flags |= EFX_MOD_PROBE;
204 enop->eno_unprobe(enp);
207 EFSYS_PROBE1(fail1, efx_rc_t, rc);
212 __checkReturn efx_rc_t
213 efx_nic_set_drv_limits(
214 __inout efx_nic_t *enp,
215 __in efx_drv_limits_t *edlp)
217 const efx_nic_ops_t *enop = enp->en_enop;
220 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
221 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
223 if (enop->eno_set_drv_limits != NULL) {
224 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
231 EFSYS_PROBE1(fail1, efx_rc_t, rc);
236 __checkReturn efx_rc_t
237 efx_nic_get_bar_region(
239 __in efx_nic_region_t region,
240 __out uint32_t *offsetp,
243 const efx_nic_ops_t *enop = enp->en_enop;
246 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
247 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
248 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
250 if (enop->eno_get_bar_region == NULL) {
254 if ((rc = (enop->eno_get_bar_region)(enp,
255 region, offsetp, sizep)) != 0) {
265 EFSYS_PROBE1(fail1, efx_rc_t, rc);
271 __checkReturn efx_rc_t
274 __out uint32_t *evq_countp,
275 __out uint32_t *rxq_countp,
276 __out uint32_t *txq_countp)
278 const efx_nic_ops_t *enop = enp->en_enop;
279 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
282 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
283 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
284 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
286 if (enop->eno_get_vi_pool != NULL) {
287 uint32_t vi_count = 0;
289 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
292 *evq_countp = vi_count;
293 *rxq_countp = vi_count;
294 *txq_countp = vi_count;
296 /* Use NIC limits as default value */
297 *evq_countp = encp->enc_evq_limit;
298 *rxq_countp = encp->enc_rxq_limit;
299 *txq_countp = encp->enc_txq_limit;
305 EFSYS_PROBE1(fail1, efx_rc_t, rc);
311 __checkReturn efx_rc_t
315 const efx_nic_ops_t *enop = enp->en_enop;
318 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
319 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
321 if (enp->en_mod_flags & EFX_MOD_NIC) {
326 if ((rc = enop->eno_init(enp)) != 0)
329 enp->en_mod_flags |= EFX_MOD_NIC;
336 EFSYS_PROBE1(fail1, efx_rc_t, rc);
345 const efx_nic_ops_t *enop = enp->en_enop;
347 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
348 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
349 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
350 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
351 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
352 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
353 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
357 enp->en_mod_flags &= ~EFX_MOD_NIC;
364 const efx_nic_ops_t *enop = enp->en_enop;
366 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
367 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
368 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
369 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
370 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
371 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
372 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
374 efx_phy_unprobe(enp);
376 enop->eno_unprobe(enp);
378 enp->en_mod_flags &= ~EFX_MOD_PROBE;
385 efsys_identifier_t *esip = enp->en_esip;
387 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
388 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
390 enp->en_family = EFX_FAMILY_INVALID;
399 /* Free the NIC object */
400 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
403 __checkReturn efx_rc_t
407 const efx_nic_ops_t *enop = enp->en_enop;
408 unsigned int mod_flags;
411 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
412 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
414 * All modules except the MCDI, PROBE, NVRAM, VPD, MON
415 * (which we do not reset here) must have been shut down or never
418 * A rule of thumb here is: If the controller or MC reboots, is *any*
419 * state lost. If it's lost and needs reapplying, then the module
420 * *must* not be initialised during the reset.
422 mod_flags = enp->en_mod_flags;
423 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
424 EFX_MOD_VPD | EFX_MOD_MON);
425 EFSYS_ASSERT3U(mod_flags, ==, 0);
426 if (mod_flags != 0) {
431 if ((rc = enop->eno_reset(enp)) != 0)
439 EFSYS_PROBE1(fail1, efx_rc_t, rc);
444 const efx_nic_cfg_t *
448 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
450 return (&(enp->en_nic_cfg));
453 __checkReturn efx_rc_t
454 efx_nic_calculate_pcie_link_bandwidth(
455 __in uint32_t pcie_link_width,
456 __in uint32_t pcie_link_gen,
457 __out uint32_t *bandwidth_mbpsp)
459 uint32_t lane_bandwidth;
460 uint32_t total_bandwidth;
463 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
464 !ISP2(pcie_link_width)) {
469 switch (pcie_link_gen) {
470 case EFX_PCIE_LINK_SPEED_GEN1:
471 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
472 lane_bandwidth = 2000;
474 case EFX_PCIE_LINK_SPEED_GEN2:
475 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
476 lane_bandwidth = 4000;
478 case EFX_PCIE_LINK_SPEED_GEN3:
479 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
480 lane_bandwidth = 7877;
487 total_bandwidth = lane_bandwidth * pcie_link_width;
488 *bandwidth_mbpsp = total_bandwidth;
495 EFSYS_PROBE1(fail1, efx_rc_t, rc);
501 __checkReturn efx_rc_t
502 efx_nic_check_pcie_link_speed(
504 __in uint32_t pcie_link_width,
505 __in uint32_t pcie_link_gen,
506 __out efx_pcie_link_performance_t *resultp)
508 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
510 efx_pcie_link_performance_t result;
513 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
514 (pcie_link_width == 0) || (pcie_link_width == 32) ||
515 (pcie_link_gen == 0)) {
517 * No usable info on what is required and/or in use. In virtual
518 * machines, sometimes the PCIe link width is reported as 0 or
519 * 32, or the speed as 0.
521 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
525 /* Calculate the available bandwidth in megabits per second */
526 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
527 pcie_link_gen, &bandwidth);
531 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
532 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
533 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
534 /* The link provides enough bandwidth but not optimal latency */
535 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
537 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
546 EFSYS_PROBE1(fail1, efx_rc_t, rc);