2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
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9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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34 __checkReturn efx_rc_t
38 __out efx_family_t *efp)
40 if (venid == EFX_PCI_VENID_SFC) {
43 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
49 *efp = EFX_FAMILY_INVALID;
54 #define EFX_BIU_MAGIC0 0x01234567
55 #define EFX_BIU_MAGIC1 0xfedcba98
57 __checkReturn efx_rc_t
65 * Write magic values to scratch registers 0 and 1, then
66 * verify that the values were written correctly. Interleave
67 * the accesses to ensure that the BIU is not just reading
68 * back the cached value that was last written.
70 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
71 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
73 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
74 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
76 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
77 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
82 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
83 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
89 * Perform the same test, with the values swapped. This
90 * ensures that subsequent tests don't start with the correct
91 * values already written into the scratch registers.
93 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
94 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
96 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
97 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
99 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
100 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
105 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
106 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
126 __checkReturn efx_rc_t
128 __in efx_family_t family,
129 __in efsys_identifier_t *esip,
130 __in efsys_bar_t *esbp,
131 __in efsys_lock_t *eslp,
132 __deref_out efx_nic_t **enpp)
137 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
138 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
140 /* Allocate a NIC object */
141 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
148 enp->en_magic = EFX_NIC_MAGIC;
157 enp->en_family = family;
171 /* Free the NIC object */
172 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
175 EFSYS_PROBE1(fail1, efx_rc_t, rc);
180 __checkReturn efx_rc_t
184 const efx_nic_ops_t *enop;
187 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
189 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
190 #endif /* EFSYS_OPT_MCDI */
191 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
194 if ((rc = enop->eno_probe(enp)) != 0)
197 if ((rc = efx_phy_probe(enp)) != 0)
200 enp->en_mod_flags |= EFX_MOD_PROBE;
207 enop->eno_unprobe(enp);
210 EFSYS_PROBE1(fail1, efx_rc_t, rc);
215 __checkReturn efx_rc_t
216 efx_nic_set_drv_limits(
217 __inout efx_nic_t *enp,
218 __in efx_drv_limits_t *edlp)
220 const efx_nic_ops_t *enop = enp->en_enop;
223 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
224 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
226 if (enop->eno_set_drv_limits != NULL) {
227 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
234 EFSYS_PROBE1(fail1, efx_rc_t, rc);
239 __checkReturn efx_rc_t
240 efx_nic_get_bar_region(
242 __in efx_nic_region_t region,
243 __out uint32_t *offsetp,
246 const efx_nic_ops_t *enop = enp->en_enop;
249 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
250 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
251 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
253 if (enop->eno_get_bar_region == NULL) {
257 if ((rc = (enop->eno_get_bar_region)(enp,
258 region, offsetp, sizep)) != 0) {
268 EFSYS_PROBE1(fail1, efx_rc_t, rc);
274 __checkReturn efx_rc_t
277 __out uint32_t *evq_countp,
278 __out uint32_t *rxq_countp,
279 __out uint32_t *txq_countp)
281 const efx_nic_ops_t *enop = enp->en_enop;
282 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
285 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
286 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
287 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
289 if (enop->eno_get_vi_pool != NULL) {
290 uint32_t vi_count = 0;
292 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
295 *evq_countp = vi_count;
296 *rxq_countp = vi_count;
297 *txq_countp = vi_count;
299 /* Use NIC limits as default value */
300 *evq_countp = encp->enc_evq_limit;
301 *rxq_countp = encp->enc_rxq_limit;
302 *txq_countp = encp->enc_txq_limit;
308 EFSYS_PROBE1(fail1, efx_rc_t, rc);
314 __checkReturn efx_rc_t
318 const efx_nic_ops_t *enop = enp->en_enop;
321 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
322 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
324 if (enp->en_mod_flags & EFX_MOD_NIC) {
329 if ((rc = enop->eno_init(enp)) != 0)
332 enp->en_mod_flags |= EFX_MOD_NIC;
339 EFSYS_PROBE1(fail1, efx_rc_t, rc);
348 const efx_nic_ops_t *enop = enp->en_enop;
350 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
351 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
352 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
353 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
354 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
355 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
356 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
360 enp->en_mod_flags &= ~EFX_MOD_NIC;
367 const efx_nic_ops_t *enop = enp->en_enop;
369 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
371 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
372 #endif /* EFSYS_OPT_MCDI */
373 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
374 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
375 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
376 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
377 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
378 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
380 efx_phy_unprobe(enp);
382 enop->eno_unprobe(enp);
384 enp->en_mod_flags &= ~EFX_MOD_PROBE;
391 efsys_identifier_t *esip = enp->en_esip;
393 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
394 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
396 enp->en_family = EFX_FAMILY_INVALID;
405 /* Free the NIC object */
406 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
409 __checkReturn efx_rc_t
413 const efx_nic_ops_t *enop = enp->en_enop;
414 unsigned int mod_flags;
417 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
418 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
420 * All modules except the MCDI, PROBE, NVRAM, VPD, MON
421 * (which we do not reset here) must have been shut down or never
424 * A rule of thumb here is: If the controller or MC reboots, is *any*
425 * state lost. If it's lost and needs reapplying, then the module
426 * *must* not be initialised during the reset.
428 mod_flags = enp->en_mod_flags;
429 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
430 EFX_MOD_VPD | EFX_MOD_MON);
431 EFSYS_ASSERT3U(mod_flags, ==, 0);
432 if (mod_flags != 0) {
437 if ((rc = enop->eno_reset(enp)) != 0)
445 EFSYS_PROBE1(fail1, efx_rc_t, rc);
450 const efx_nic_cfg_t *
454 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
456 return (&(enp->en_nic_cfg));
459 __checkReturn efx_rc_t
460 efx_nic_calculate_pcie_link_bandwidth(
461 __in uint32_t pcie_link_width,
462 __in uint32_t pcie_link_gen,
463 __out uint32_t *bandwidth_mbpsp)
465 uint32_t lane_bandwidth;
466 uint32_t total_bandwidth;
469 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
470 !ISP2(pcie_link_width)) {
475 switch (pcie_link_gen) {
476 case EFX_PCIE_LINK_SPEED_GEN1:
477 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
478 lane_bandwidth = 2000;
480 case EFX_PCIE_LINK_SPEED_GEN2:
481 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
482 lane_bandwidth = 4000;
484 case EFX_PCIE_LINK_SPEED_GEN3:
485 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
486 lane_bandwidth = 7877;
493 total_bandwidth = lane_bandwidth * pcie_link_width;
494 *bandwidth_mbpsp = total_bandwidth;
501 EFSYS_PROBE1(fail1, efx_rc_t, rc);
507 __checkReturn efx_rc_t
508 efx_nic_check_pcie_link_speed(
510 __in uint32_t pcie_link_width,
511 __in uint32_t pcie_link_gen,
512 __out efx_pcie_link_performance_t *resultp)
514 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
516 efx_pcie_link_performance_t result;
519 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
520 (pcie_link_width == 0) || (pcie_link_width == 32) ||
521 (pcie_link_gen == 0)) {
523 * No usable info on what is required and/or in use. In virtual
524 * machines, sometimes the PCIe link width is reported as 0 or
525 * 32, or the speed as 0.
527 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
531 /* Calculate the available bandwidth in megabits per second */
532 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
533 pcie_link_gen, &bandwidth);
537 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
538 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
539 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
540 /* The link provides enough bandwidth but not optimal latency */
541 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
543 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
552 EFSYS_PROBE1(fail1, efx_rc_t, rc);