drivers/net/sfc/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         *efp = EFX_FAMILY_INVALID;
  89         return (ENOTSUP);
  90 }
  91
  92
  93 #if EFSYS_OPT_SIENA
  94
  95 static const efx_nic_ops_t      __efx_nic_siena_ops = {
  96         siena_nic_probe,                /* eno_probe */
  97         NULL,                           /* eno_board_cfg */
  98         NULL,                           /* eno_set_drv_limits */
  99         siena_nic_reset,                /* eno_reset */
 100         siena_nic_init,                 /* eno_init */
 101         NULL,                           /* eno_get_vi_pool */
 102         NULL,                           /* eno_get_bar_region */
 103 #if EFSYS_OPT_DIAG
 104         siena_nic_register_test,        /* eno_register_test */
 105 #endif  /* EFSYS_OPT_DIAG */
 106         siena_nic_fini,                 /* eno_fini */
 107         siena_nic_unprobe,              /* eno_unprobe */
 108 };
 109
 110 #endif  /* EFSYS_OPT_SIENA */
 111
 112 #if EFSYS_OPT_HUNTINGTON
 113
 114 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 115         ef10_nic_probe,                 /* eno_probe */
 116         hunt_board_cfg,                 /* eno_board_cfg */
 117         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 118         ef10_nic_reset,                 /* eno_reset */
 119         ef10_nic_init,                  /* eno_init */
 120         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 121         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 122 #if EFSYS_OPT_DIAG
 123         ef10_nic_register_test,         /* eno_register_test */
 124 #endif  /* EFSYS_OPT_DIAG */
 125         ef10_nic_fini,                  /* eno_fini */
 126         ef10_nic_unprobe,               /* eno_unprobe */
 127 };
 128
 129 #endif  /* EFSYS_OPT_HUNTINGTON */
 130
 131 #if EFSYS_OPT_MEDFORD
 132
 133 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 134         ef10_nic_probe,                 /* eno_probe */
 135         medford_board_cfg,              /* eno_board_cfg */
 136         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 137         ef10_nic_reset,                 /* eno_reset */
 138         ef10_nic_init,                  /* eno_init */
 139         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 140         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 141 #if EFSYS_OPT_DIAG
 142         ef10_nic_register_test,         /* eno_register_test */
 143 #endif  /* EFSYS_OPT_DIAG */
 144         ef10_nic_fini,                  /* eno_fini */
 145         ef10_nic_unprobe,               /* eno_unprobe */
 146 };
 147
 148 #endif  /* EFSYS_OPT_MEDFORD */
 149
 150 #if EFSYS_OPT_MEDFORD2
 151
 152 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 153         ef10_nic_probe,                 /* eno_probe */
 154         medford2_board_cfg,             /* eno_board_cfg */
 155         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 156         ef10_nic_reset,                 /* eno_reset */
 157         ef10_nic_init,                  /* eno_init */
 158         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 159         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 160 #if EFSYS_OPT_DIAG
 161         ef10_nic_register_test,         /* eno_register_test */
 162 #endif  /* EFSYS_OPT_DIAG */
 163         ef10_nic_fini,                  /* eno_fini */
 164         ef10_nic_unprobe,               /* eno_unprobe */
 165 };
 166
 167 #endif  /* EFSYS_OPT_MEDFORD2 */
 168
 169
 170         __checkReturn   efx_rc_t
 171 efx_nic_create(
 172         __in            efx_family_t family,
 173         __in            efsys_identifier_t *esip,
 174         __in            efsys_bar_t *esbp,
 175         __in            efsys_lock_t *eslp,
 176         __deref_out     efx_nic_t **enpp)
 177 {
 178         efx_nic_t *enp;
 179         efx_rc_t rc;
 180
 181         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 182         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 183
 184         /* Allocate a NIC object */
 185         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 186
 187         if (enp == NULL) {
 188                 rc = ENOMEM;
 189                 goto fail1;
 190         }
 191
 192         enp->en_magic = EFX_NIC_MAGIC;
 193
 194         switch (family) {
 195 #if EFSYS_OPT_SIENA
 196         case EFX_FAMILY_SIENA:
 197                 enp->en_enop = &__efx_nic_siena_ops;
 198                 enp->en_features =
 199                     EFX_FEATURE_IPV6 |
 200                     EFX_FEATURE_LFSR_HASH_INSERT |
 201                     EFX_FEATURE_LINK_EVENTS |
 202                     EFX_FEATURE_PERIODIC_MAC_STATS |
 203                     EFX_FEATURE_MCDI |
 204                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 205                     EFX_FEATURE_MAC_HEADER_FILTERS |
 206                     EFX_FEATURE_TX_SRC_FILTERS;
 207                 break;
 208 #endif  /* EFSYS_OPT_SIENA */
 209
 210 #if EFSYS_OPT_HUNTINGTON
 211         case EFX_FAMILY_HUNTINGTON:
 212                 enp->en_enop = &__efx_nic_hunt_ops;
 213                 enp->en_features =
 214                     EFX_FEATURE_IPV6 |
 215                     EFX_FEATURE_LINK_EVENTS |
 216                     EFX_FEATURE_PERIODIC_MAC_STATS |
 217                     EFX_FEATURE_MCDI |
 218                     EFX_FEATURE_MAC_HEADER_FILTERS |
 219                     EFX_FEATURE_MCDI_DMA |
 220                     EFX_FEATURE_PIO_BUFFERS |
 221                     EFX_FEATURE_FW_ASSISTED_TSO |
 222                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 223                     EFX_FEATURE_PACKED_STREAM;
 224                 break;
 225 #endif  /* EFSYS_OPT_HUNTINGTON */
 226
 227 #if EFSYS_OPT_MEDFORD
 228         case EFX_FAMILY_MEDFORD:
 229                 enp->en_enop = &__efx_nic_medford_ops;
 230                 /*
 231                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 232                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 233                  */
 234                 enp->en_features =
 235                     EFX_FEATURE_IPV6 |
 236                     EFX_FEATURE_LINK_EVENTS |
 237                     EFX_FEATURE_PERIODIC_MAC_STATS |
 238                     EFX_FEATURE_MCDI |
 239                     EFX_FEATURE_MAC_HEADER_FILTERS |
 240                     EFX_FEATURE_MCDI_DMA |
 241                     EFX_FEATURE_PIO_BUFFERS |
 242                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 243                     EFX_FEATURE_PACKED_STREAM;
 244                 break;
 245 #endif  /* EFSYS_OPT_MEDFORD */
 246
 247 #if EFSYS_OPT_MEDFORD2
 248         case EFX_FAMILY_MEDFORD2:
 249                 enp->en_enop = &__efx_nic_medford2_ops;
 250                 enp->en_features =
 251                     EFX_FEATURE_IPV6 |
 252                     EFX_FEATURE_LINK_EVENTS |
 253                     EFX_FEATURE_PERIODIC_MAC_STATS |
 254                     EFX_FEATURE_MCDI |
 255                     EFX_FEATURE_MAC_HEADER_FILTERS |
 256                     EFX_FEATURE_MCDI_DMA |
 257                     EFX_FEATURE_PIO_BUFFERS |
 258                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 259                     EFX_FEATURE_PACKED_STREAM;
 260                 break;
 261 #endif  /* EFSYS_OPT_MEDFORD2 */
 262
 263         default:
 264                 rc = ENOTSUP;
 265                 goto fail2;
 266         }
 267
 268         enp->en_family = family;
 269         enp->en_esip = esip;
 270         enp->en_esbp = esbp;
 271         enp->en_eslp = eslp;
 272
 273         *enpp = enp;
 274
 275         return (0);
 276
 277 fail2:
 278         EFSYS_PROBE(fail2);
 279
 280         enp->en_magic = 0;
 281
 282         /* Free the NIC object */
 283         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 284
 285 fail1:
 286         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 287
 288         return (rc);
 289 }
 290
 291         __checkReturn   efx_rc_t
 292 efx_nic_probe(
 293         __in            efx_nic_t *enp)
 294 {
 295         const efx_nic_ops_t *enop;
 296         efx_rc_t rc;
 297
 298         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 299 #if EFSYS_OPT_MCDI
 300         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 301 #endif  /* EFSYS_OPT_MCDI */
 302         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 303
 304         enop = enp->en_enop;
 305         if ((rc = enop->eno_probe(enp)) != 0)
 306                 goto fail1;
 307
 308         if ((rc = efx_phy_probe(enp)) != 0)
 309                 goto fail2;
 310
 311         enp->en_mod_flags |= EFX_MOD_PROBE;
 312
 313         return (0);
 314
 315 fail2:
 316         EFSYS_PROBE(fail2);
 317
 318         enop->eno_unprobe(enp);
 319
 320 fail1:
 321         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 322
 323         return (rc);
 324 }
 325
 326         __checkReturn   efx_rc_t
 327 efx_nic_set_drv_limits(
 328         __inout         efx_nic_t *enp,
 329         __in            efx_drv_limits_t *edlp)
 330 {
 331         const efx_nic_ops_t *enop = enp->en_enop;
 332         efx_rc_t rc;
 333
 334         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 335         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 336
 337         if (enop->eno_set_drv_limits != NULL) {
 338                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 339                         goto fail1;
 340         }
 341
 342         return (0);
 343
 344 fail1:
 345         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 346
 347         return (rc);
 348 }
 349
 350         __checkReturn   efx_rc_t
 351 efx_nic_get_bar_region(
 352         __in            efx_nic_t *enp,
 353         __in            efx_nic_region_t region,
 354         __out           uint32_t *offsetp,
 355         __out           size_t *sizep)
 356 {
 357         const efx_nic_ops_t *enop = enp->en_enop;
 358         efx_rc_t rc;
 359
 360         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 361         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 362         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 363
 364         if (enop->eno_get_bar_region == NULL) {
 365                 rc = ENOTSUP;
 366                 goto fail1;
 367         }
 368         if ((rc = (enop->eno_get_bar_region)(enp,
 369                     region, offsetp, sizep)) != 0) {
 370                 goto fail2;
 371         }
 372
 373         return (0);
 374
 375 fail2:
 376         EFSYS_PROBE(fail2);
 377
 378 fail1:
 379         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 380
 381         return (rc);
 382 }
 383
 384
 385         __checkReturn   efx_rc_t
 386 efx_nic_get_vi_pool(
 387         __in            efx_nic_t *enp,
 388         __out           uint32_t *evq_countp,
 389         __out           uint32_t *rxq_countp,
 390         __out           uint32_t *txq_countp)
 391 {
 392         const efx_nic_ops_t *enop = enp->en_enop;
 393         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 394         efx_rc_t rc;
 395
 396         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 397         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 398         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 399
 400         if (enop->eno_get_vi_pool != NULL) {
 401                 uint32_t vi_count = 0;
 402
 403                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 404                         goto fail1;
 405
 406                 *evq_countp = vi_count;
 407                 *rxq_countp = vi_count;
 408                 *txq_countp = vi_count;
 409         } else {
 410                 /* Use NIC limits as default value */
 411                 *evq_countp = encp->enc_evq_limit;
 412                 *rxq_countp = encp->enc_rxq_limit;
 413                 *txq_countp = encp->enc_txq_limit;
 414         }
 415
 416         return (0);
 417
 418 fail1:
 419         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 420
 421         return (rc);
 422 }
 423
 424
 425         __checkReturn   efx_rc_t
 426 efx_nic_init(
 427         __in            efx_nic_t *enp)
 428 {
 429         const efx_nic_ops_t *enop = enp->en_enop;
 430         efx_rc_t rc;
 431
 432         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 433         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 434
 435         if (enp->en_mod_flags & EFX_MOD_NIC) {
 436                 rc = EINVAL;
 437                 goto fail1;
 438         }
 439
 440         if ((rc = enop->eno_init(enp)) != 0)
 441                 goto fail2;
 442
 443         enp->en_mod_flags |= EFX_MOD_NIC;
 444
 445         return (0);
 446
 447 fail2:
 448         EFSYS_PROBE(fail2);
 449 fail1:
 450         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 451
 452         return (rc);
 453 }
 454
 455                         void
 456 efx_nic_fini(
 457         __in            efx_nic_t *enp)
 458 {
 459         const efx_nic_ops_t *enop = enp->en_enop;
 460
 461         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 462         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 463         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 464         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 465         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 466         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 467         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 468
 469         enop->eno_fini(enp);
 470
 471         enp->en_mod_flags &= ~EFX_MOD_NIC;
 472 }
 473
 474                         void
 475 efx_nic_unprobe(
 476         __in            efx_nic_t *enp)
 477 {
 478         const efx_nic_ops_t *enop = enp->en_enop;
 479
 480         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 481 #if EFSYS_OPT_MCDI
 482         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 483 #endif  /* EFSYS_OPT_MCDI */
 484         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 485         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 486         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 487         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 488         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 489         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 490
 491         efx_phy_unprobe(enp);
 492
 493         enop->eno_unprobe(enp);
 494
 495         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 496 }
 497
 498                         void
 499 efx_nic_destroy(
 500         __in    efx_nic_t *enp)
 501 {
 502         efsys_identifier_t *esip = enp->en_esip;
 503
 504         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 505         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 506
 507         enp->en_family = EFX_FAMILY_INVALID;
 508         enp->en_esip = NULL;
 509         enp->en_esbp = NULL;
 510         enp->en_eslp = NULL;
 511
 512         enp->en_enop = NULL;
 513
 514         enp->en_magic = 0;
 515
 516         /* Free the NIC object */
 517         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 518 }
 519
 520         __checkReturn   efx_rc_t
 521 efx_nic_reset(
 522         __in            efx_nic_t *enp)
 523 {
 524         const efx_nic_ops_t *enop = enp->en_enop;
 525         unsigned int mod_flags;
 526         efx_rc_t rc;
 527
 528         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 529         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 530         /*
 531          * All modules except the MCDI, PROBE, NVRAM, VPD, MON
 532          * (which we do not reset here) must have been shut down or never
 533          * initialized.
 534          *
 535          * A rule of thumb here is: If the controller or MC reboots, is *any*
 536          * state lost. If it's lost and needs reapplying, then the module
 537          * *must* not be initialised during the reset.
 538          */
 539         mod_flags = enp->en_mod_flags;
 540         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 541                     EFX_MOD_VPD | EFX_MOD_MON);
 542         EFSYS_ASSERT3U(mod_flags, ==, 0);
 543         if (mod_flags != 0) {
 544                 rc = EINVAL;
 545                 goto fail1;
 546         }
 547
 548         if ((rc = enop->eno_reset(enp)) != 0)
 549                 goto fail2;
 550
 551         return (0);
 552
 553 fail2:
 554         EFSYS_PROBE(fail2);
 555 fail1:
 556         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 557
 558         return (rc);
 559 }
 560
 561                         const efx_nic_cfg_t *
 562 efx_nic_cfg_get(
 563         __in            efx_nic_t *enp)
 564 {
 565         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 566
 567         return (&(enp->en_nic_cfg));
 568 }
 569
 570         __checkReturn           efx_rc_t
 571 efx_nic_get_fw_version(
 572         __in                    efx_nic_t *enp,
 573         __out                   efx_nic_fw_info_t *enfip)
 574 {
 575         uint16_t mc_fw_version[4];
 576         efx_rc_t rc;
 577
 578         if (enfip == NULL) {
 579                 rc = EINVAL;
 580                 goto fail1;
 581         }
 582
 583         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 584         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 585
 586         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 587         if (rc != 0)
 588                 goto fail2;
 589
 590         rc = efx_mcdi_get_capabilities(enp, NULL,
 591             &enfip->enfi_rx_dpcpu_fw_id,
 592             &enfip->enfi_tx_dpcpu_fw_id,
 593             NULL, NULL);
 594         if (rc == 0) {
 595                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 596         } else if (rc == ENOTSUP) {
 597                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 598                 enfip->enfi_rx_dpcpu_fw_id = 0;
 599                 enfip->enfi_tx_dpcpu_fw_id = 0;
 600         } else {
 601                 goto fail3;
 602         }
 603
 604         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 605             sizeof (mc_fw_version));
 606
 607         return (0);
 608
 609 fail3:
 610         EFSYS_PROBE(fail3);
 611 fail2:
 612         EFSYS_PROBE(fail2);
 613 fail1:
 614         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 615
 616         return (rc);
 617 }
 618
 619 #if EFSYS_OPT_DIAG
 620
 621         __checkReturn   efx_rc_t
 622 efx_nic_register_test(
 623         __in            efx_nic_t *enp)
 624 {
 625         const efx_nic_ops_t *enop = enp->en_enop;
 626         efx_rc_t rc;
 627
 628         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 629         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 630         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 631
 632         if ((rc = enop->eno_register_test(enp)) != 0)
 633                 goto fail1;
 634
 635         return (0);
 636
 637 fail1:
 638         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 639
 640         return (rc);
 641 }
 642
 643 #endif  /* EFSYS_OPT_DIAG */
 644
 645 #if EFSYS_OPT_LOOPBACK
 646
 647 extern                  void
 648 efx_loopback_mask(
 649         __in    efx_loopback_kind_t loopback_kind,
 650         __out   efx_qword_t *maskp)
 651 {
 652         efx_qword_t mask;
 653
 654         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 655         EFSYS_ASSERT(maskp != NULL);
 656
 657         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
 658         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
 659         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
 660         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
 661         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
 662         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
 663         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
 664         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
 665         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
 666         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
 667         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
 668         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
 669         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
 670         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
 671         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
 672         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
 673         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
 674         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
 675         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
 676         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XPORT == EFX_LOOPBACK_XPORT);
 677         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII_WS == EFX_LOOPBACK_XGMII_WS);
 678         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS == EFX_LOOPBACK_XAUI_WS);
 679         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_FAR ==
 680             EFX_LOOPBACK_XAUI_WS_FAR);
 681         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_NEAR ==
 682             EFX_LOOPBACK_XAUI_WS_NEAR);
 683         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_WS == EFX_LOOPBACK_GMII_WS);
 684         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS == EFX_LOOPBACK_XFI_WS);
 685         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS_FAR ==
 686             EFX_LOOPBACK_XFI_WS_FAR);
 687         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS_WS == EFX_LOOPBACK_PHYXS_WS);
 688         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT == EFX_LOOPBACK_PMA_INT);
 689         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_NEAR == EFX_LOOPBACK_SD_NEAR);
 690         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FAR == EFX_LOOPBACK_SD_FAR);
 691         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT_WS ==
 692             EFX_LOOPBACK_PMA_INT_WS);
 693         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP2_WS ==
 694             EFX_LOOPBACK_SD_FEP2_WS);
 695         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP1_5_WS ==
 696             EFX_LOOPBACK_SD_FEP1_5_WS);
 697         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP_WS == EFX_LOOPBACK_SD_FEP_WS);
 698         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FES_WS == EFX_LOOPBACK_SD_FES_WS);
 699
 700         /* Build bitmask of possible loopback types */
 701         EFX_ZERO_QWORD(mask);
 702
 703         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 704             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 705                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 706         }
 707
 708         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 709             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 710                 /*
 711                  * The "MAC" grouping has historically been used by drivers to
 712                  * mean loopbacks supported by on-chip hardware. Keep that
 713                  * meaning here, and include on-chip PHY layer loopbacks.
 714                  */
 715                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 716                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 717                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 718                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 719                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 720                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 721                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 722                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 723                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 724                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 725                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 726                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 727                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 728                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 729                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 730                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 731         }
 732
 733         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 734             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 735                 /*
 736                  * The "PHY" grouping has historically been used by drivers to
 737                  * mean loopbacks supported by off-chip hardware. Keep that
 738                  * meaning here.
 739                  */
 740                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 741                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 742                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 743                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 744         }
 745
 746         *maskp = mask;
 747 }
 748
 749         __checkReturn   efx_rc_t
 750 efx_mcdi_get_loopback_modes(
 751         __in            efx_nic_t *enp)
 752 {
 753         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 754         efx_mcdi_req_t req;
 755         uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 756                             MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)];
 757         efx_qword_t mask;
 758         efx_qword_t modes;
 759         efx_rc_t rc;
 760
 761         (void) memset(payload, 0, sizeof (payload));
 762         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 763         req.emr_in_buf = payload;
 764         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 765         req.emr_out_buf = payload;
 766         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_LEN;
 767
 768         efx_mcdi_execute(enp, &req);
 769
 770         if (req.emr_rc != 0) {
 771                 rc = req.emr_rc;
 772                 goto fail1;
 773         }
 774
 775         if (req.emr_out_length_used <
 776             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 777             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 778                 rc = EMSGSIZE;
 779                 goto fail2;
 780         }
 781
 782         /*
 783          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 784          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 785          */
 786         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 787
 788         EFX_AND_QWORD(mask,
 789             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 790
 791         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 792         EFX_AND_QWORD(modes, mask);
 793         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 794
 795         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 796         EFX_AND_QWORD(modes, mask);
 797         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 798
 799         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 800         EFX_AND_QWORD(modes, mask);
 801         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 802
 803         if (req.emr_out_length_used >=
 804             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 805             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 806                 /* Response includes 40G loopback modes */
 807                 modes =
 808                     *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G);
 809                 EFX_AND_QWORD(modes, mask);
 810                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 811         }
 812
 813         EFX_ZERO_QWORD(modes);
 814         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 815         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 816         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 817         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 818         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 819         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 820
 821         return (0);
 822
 823 fail2:
 824         EFSYS_PROBE(fail2);
 825 fail1:
 826         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 827
 828         return (rc);
 829 }
 830
 831 #endif /* EFSYS_OPT_LOOPBACK */
 832
 833         __checkReturn   efx_rc_t
 834 efx_nic_calculate_pcie_link_bandwidth(
 835         __in            uint32_t pcie_link_width,
 836         __in            uint32_t pcie_link_gen,
 837         __out           uint32_t *bandwidth_mbpsp)
 838 {
 839         uint32_t lane_bandwidth;
 840         uint32_t total_bandwidth;
 841         efx_rc_t rc;
 842
 843         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
 844             !ISP2(pcie_link_width)) {
 845                 rc = EINVAL;
 846                 goto fail1;
 847         }
 848
 849         switch (pcie_link_gen) {
 850         case EFX_PCIE_LINK_SPEED_GEN1:
 851                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
 852                 lane_bandwidth = 2000;
 853                 break;
 854         case EFX_PCIE_LINK_SPEED_GEN2:
 855                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
 856                 lane_bandwidth = 4000;
 857                 break;
 858         case EFX_PCIE_LINK_SPEED_GEN3:
 859                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
 860                 lane_bandwidth = 7877;
 861                 break;
 862         default:
 863                 rc = EINVAL;
 864                 goto fail2;
 865         }
 866
 867         total_bandwidth = lane_bandwidth * pcie_link_width;
 868         *bandwidth_mbpsp = total_bandwidth;
 869
 870         return (0);
 871
 872 fail2:
 873         EFSYS_PROBE(fail2);
 874 fail1:
 875         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 876
 877         return (rc);
 878 }
 879
 880
 881         __checkReturn   efx_rc_t
 882 efx_nic_check_pcie_link_speed(
 883         __in            efx_nic_t *enp,
 884         __in            uint32_t pcie_link_width,
 885         __in            uint32_t pcie_link_gen,
 886         __out           efx_pcie_link_performance_t *resultp)
 887 {
 888         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 889         uint32_t bandwidth;
 890         efx_pcie_link_performance_t result;
 891         efx_rc_t rc;
 892
 893         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
 894             (pcie_link_width == 0) || (pcie_link_width == 32) ||
 895             (pcie_link_gen == 0)) {
 896                 /*
 897                  * No usable info on what is required and/or in use. In virtual
 898                  * machines, sometimes the PCIe link width is reported as 0 or
 899                  * 32, or the speed as 0.
 900                  */
 901                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
 902                 goto out;
 903         }
 904
 905         /* Calculate the available bandwidth in megabits per second */
 906         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
 907                                             pcie_link_gen, &bandwidth);
 908         if (rc != 0)
 909                 goto fail1;
 910
 911         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
 912                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
 913         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
 914                 /* The link provides enough bandwidth but not optimal latency */
 915                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
 916         } else {
 917                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
 918         }
 919
 920 out:
 921         *resultp = result;
 922
 923         return (0);
 924
 925 fail1:
 926         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 927
 928         return (rc);
 929 }