drivers/net/sfc/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         *efp = EFX_FAMILY_INVALID;
  89         return (ENOTSUP);
  90 }
  91
  92
  93 #if EFSYS_OPT_SIENA
  94
  95 static const efx_nic_ops_t      __efx_nic_siena_ops = {
  96         siena_nic_probe,                /* eno_probe */
  97         NULL,                           /* eno_board_cfg */
  98         NULL,                           /* eno_set_drv_limits */
  99         siena_nic_reset,                /* eno_reset */
 100         siena_nic_init,                 /* eno_init */
 101         NULL,                           /* eno_get_vi_pool */
 102         NULL,                           /* eno_get_bar_region */
 103         NULL,                           /* eno_hw_unavailable */
 104         NULL,                           /* eno_set_hw_unavailable */
 105 #if EFSYS_OPT_DIAG
 106         siena_nic_register_test,        /* eno_register_test */
 107 #endif  /* EFSYS_OPT_DIAG */
 108         siena_nic_fini,                 /* eno_fini */
 109         siena_nic_unprobe,              /* eno_unprobe */
 110 };
 111
 112 #endif  /* EFSYS_OPT_SIENA */
 113
 114 #if EFSYS_OPT_HUNTINGTON
 115
 116 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 117         ef10_nic_probe,                 /* eno_probe */
 118         hunt_board_cfg,                 /* eno_board_cfg */
 119         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 120         ef10_nic_reset,                 /* eno_reset */
 121         ef10_nic_init,                  /* eno_init */
 122         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 123         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 124         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 125         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 126 #if EFSYS_OPT_DIAG
 127         ef10_nic_register_test,         /* eno_register_test */
 128 #endif  /* EFSYS_OPT_DIAG */
 129         ef10_nic_fini,                  /* eno_fini */
 130         ef10_nic_unprobe,               /* eno_unprobe */
 131 };
 132
 133 #endif  /* EFSYS_OPT_HUNTINGTON */
 134
 135 #if EFSYS_OPT_MEDFORD
 136
 137 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 138         ef10_nic_probe,                 /* eno_probe */
 139         medford_board_cfg,              /* eno_board_cfg */
 140         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 141         ef10_nic_reset,                 /* eno_reset */
 142         ef10_nic_init,                  /* eno_init */
 143         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 144         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 145         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 146         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 147 #if EFSYS_OPT_DIAG
 148         ef10_nic_register_test,         /* eno_register_test */
 149 #endif  /* EFSYS_OPT_DIAG */
 150         ef10_nic_fini,                  /* eno_fini */
 151         ef10_nic_unprobe,               /* eno_unprobe */
 152 };
 153
 154 #endif  /* EFSYS_OPT_MEDFORD */
 155
 156 #if EFSYS_OPT_MEDFORD2
 157
 158 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 159         ef10_nic_probe,                 /* eno_probe */
 160         medford2_board_cfg,             /* eno_board_cfg */
 161         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 162         ef10_nic_reset,                 /* eno_reset */
 163         ef10_nic_init,                  /* eno_init */
 164         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 165         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 166         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 167         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 168 #if EFSYS_OPT_DIAG
 169         ef10_nic_register_test,         /* eno_register_test */
 170 #endif  /* EFSYS_OPT_DIAG */
 171         ef10_nic_fini,                  /* eno_fini */
 172         ef10_nic_unprobe,               /* eno_unprobe */
 173 };
 174
 175 #endif  /* EFSYS_OPT_MEDFORD2 */
 176
 177
 178         __checkReturn   efx_rc_t
 179 efx_nic_create(
 180         __in            efx_family_t family,
 181         __in            efsys_identifier_t *esip,
 182         __in            efsys_bar_t *esbp,
 183         __in            efsys_lock_t *eslp,
 184         __deref_out     efx_nic_t **enpp)
 185 {
 186         efx_nic_t *enp;
 187         efx_rc_t rc;
 188
 189         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 190         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 191
 192         /* Allocate a NIC object */
 193         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 194
 195         if (enp == NULL) {
 196                 rc = ENOMEM;
 197                 goto fail1;
 198         }
 199
 200         enp->en_magic = EFX_NIC_MAGIC;
 201
 202         switch (family) {
 203 #if EFSYS_OPT_SIENA
 204         case EFX_FAMILY_SIENA:
 205                 enp->en_enop = &__efx_nic_siena_ops;
 206                 enp->en_features =
 207                     EFX_FEATURE_IPV6 |
 208                     EFX_FEATURE_LFSR_HASH_INSERT |
 209                     EFX_FEATURE_LINK_EVENTS |
 210                     EFX_FEATURE_PERIODIC_MAC_STATS |
 211                     EFX_FEATURE_MCDI |
 212                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 213                     EFX_FEATURE_MAC_HEADER_FILTERS |
 214                     EFX_FEATURE_TX_SRC_FILTERS;
 215                 break;
 216 #endif  /* EFSYS_OPT_SIENA */
 217
 218 #if EFSYS_OPT_HUNTINGTON
 219         case EFX_FAMILY_HUNTINGTON:
 220                 enp->en_enop = &__efx_nic_hunt_ops;
 221                 enp->en_features =
 222                     EFX_FEATURE_IPV6 |
 223                     EFX_FEATURE_LINK_EVENTS |
 224                     EFX_FEATURE_PERIODIC_MAC_STATS |
 225                     EFX_FEATURE_MCDI |
 226                     EFX_FEATURE_MAC_HEADER_FILTERS |
 227                     EFX_FEATURE_MCDI_DMA |
 228                     EFX_FEATURE_PIO_BUFFERS |
 229                     EFX_FEATURE_FW_ASSISTED_TSO |
 230                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 231                     EFX_FEATURE_PACKED_STREAM |
 232                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 233                 break;
 234 #endif  /* EFSYS_OPT_HUNTINGTON */
 235
 236 #if EFSYS_OPT_MEDFORD
 237         case EFX_FAMILY_MEDFORD:
 238                 enp->en_enop = &__efx_nic_medford_ops;
 239                 /*
 240                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 241                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 242                  */
 243                 enp->en_features =
 244                     EFX_FEATURE_IPV6 |
 245                     EFX_FEATURE_LINK_EVENTS |
 246                     EFX_FEATURE_PERIODIC_MAC_STATS |
 247                     EFX_FEATURE_MCDI |
 248                     EFX_FEATURE_MAC_HEADER_FILTERS |
 249                     EFX_FEATURE_MCDI_DMA |
 250                     EFX_FEATURE_PIO_BUFFERS |
 251                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 252                     EFX_FEATURE_PACKED_STREAM |
 253                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 254                 break;
 255 #endif  /* EFSYS_OPT_MEDFORD */
 256
 257 #if EFSYS_OPT_MEDFORD2
 258         case EFX_FAMILY_MEDFORD2:
 259                 enp->en_enop = &__efx_nic_medford2_ops;
 260                 enp->en_features =
 261                     EFX_FEATURE_IPV6 |
 262                     EFX_FEATURE_LINK_EVENTS |
 263                     EFX_FEATURE_PERIODIC_MAC_STATS |
 264                     EFX_FEATURE_MCDI |
 265                     EFX_FEATURE_MAC_HEADER_FILTERS |
 266                     EFX_FEATURE_MCDI_DMA |
 267                     EFX_FEATURE_PIO_BUFFERS |
 268                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 269                     EFX_FEATURE_PACKED_STREAM |
 270                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 271                 break;
 272 #endif  /* EFSYS_OPT_MEDFORD2 */
 273
 274         default:
 275                 rc = ENOTSUP;
 276                 goto fail2;
 277         }
 278
 279         enp->en_family = family;
 280         enp->en_esip = esip;
 281         enp->en_esbp = esbp;
 282         enp->en_eslp = eslp;
 283
 284         *enpp = enp;
 285
 286         return (0);
 287
 288 fail2:
 289         EFSYS_PROBE(fail2);
 290
 291         enp->en_magic = 0;
 292
 293         /* Free the NIC object */
 294         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 295
 296 fail1:
 297         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 298
 299         return (rc);
 300 }
 301
 302         __checkReturn   efx_rc_t
 303 efx_nic_probe(
 304         __in            efx_nic_t *enp,
 305         __in            efx_fw_variant_t efv)
 306 {
 307         const efx_nic_ops_t *enop;
 308         efx_rc_t rc;
 309
 310         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 311 #if EFSYS_OPT_MCDI
 312         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 313 #endif  /* EFSYS_OPT_MCDI */
 314         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 315
 316         /* Ensure FW variant codes match with MC_CMD_FW codes */
 317         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 318             MC_CMD_FW_FULL_FEATURED);
 319         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 320             MC_CMD_FW_LOW_LATENCY);
 321         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 322             MC_CMD_FW_PACKED_STREAM);
 323         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 324             MC_CMD_FW_HIGH_TX_RATE);
 325         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 326             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 327         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 328             MC_CMD_FW_RULES_ENGINE);
 329         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 330             MC_CMD_FW_DPDK);
 331         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 332             (int)MC_CMD_FW_DONT_CARE);
 333
 334         enop = enp->en_enop;
 335         enp->efv = efv;
 336
 337         if ((rc = enop->eno_probe(enp)) != 0)
 338                 goto fail1;
 339
 340         if ((rc = efx_phy_probe(enp)) != 0)
 341                 goto fail2;
 342
 343         enp->en_mod_flags |= EFX_MOD_PROBE;
 344
 345         return (0);
 346
 347 fail2:
 348         EFSYS_PROBE(fail2);
 349
 350         enop->eno_unprobe(enp);
 351
 352 fail1:
 353         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 354
 355         return (rc);
 356 }
 357
 358         __checkReturn   efx_rc_t
 359 efx_nic_set_drv_limits(
 360         __inout         efx_nic_t *enp,
 361         __in            efx_drv_limits_t *edlp)
 362 {
 363         const efx_nic_ops_t *enop = enp->en_enop;
 364         efx_rc_t rc;
 365
 366         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 367         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 368
 369         if (enop->eno_set_drv_limits != NULL) {
 370                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 371                         goto fail1;
 372         }
 373
 374         return (0);
 375
 376 fail1:
 377         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 378
 379         return (rc);
 380 }
 381
 382         __checkReturn   efx_rc_t
 383 efx_nic_set_drv_version(
 384         __inout                 efx_nic_t *enp,
 385         __in_ecount(length)     char const *verp,
 386         __in                    size_t length)
 387 {
 388         efx_rc_t rc;
 389
 390         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 391         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 392
 393         /*
 394          * length is the string content length in bytes.
 395          * Accept any content which fits into the version
 396          * buffer, excluding the last byte. This is reserved
 397          * for an appended NUL terminator.
 398          */
 399         if (length >= sizeof (enp->en_drv_version)) {
 400                 rc = E2BIG;
 401                 goto fail1;
 402         }
 403
 404         (void) memset(enp->en_drv_version, 0,
 405             sizeof (enp->en_drv_version));
 406         memcpy(enp->en_drv_version, verp, length);
 407
 408         return (0);
 409
 410 fail1:
 411         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 412
 413         return (rc);
 414 }
 415
 416
 417         __checkReturn   efx_rc_t
 418 efx_nic_get_bar_region(
 419         __in            efx_nic_t *enp,
 420         __in            efx_nic_region_t region,
 421         __out           uint32_t *offsetp,
 422         __out           size_t *sizep)
 423 {
 424         const efx_nic_ops_t *enop = enp->en_enop;
 425         efx_rc_t rc;
 426
 427         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 428         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 429         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 430
 431         if (enop->eno_get_bar_region == NULL) {
 432                 rc = ENOTSUP;
 433                 goto fail1;
 434         }
 435         if ((rc = (enop->eno_get_bar_region)(enp,
 436                     region, offsetp, sizep)) != 0) {
 437                 goto fail2;
 438         }
 439
 440         return (0);
 441
 442 fail2:
 443         EFSYS_PROBE(fail2);
 444
 445 fail1:
 446         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 447
 448         return (rc);
 449 }
 450
 451
 452         __checkReturn   efx_rc_t
 453 efx_nic_get_vi_pool(
 454         __in            efx_nic_t *enp,
 455         __out           uint32_t *evq_countp,
 456         __out           uint32_t *rxq_countp,
 457         __out           uint32_t *txq_countp)
 458 {
 459         const efx_nic_ops_t *enop = enp->en_enop;
 460         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 461         efx_rc_t rc;
 462
 463         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 464         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 465         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 466
 467         if (enop->eno_get_vi_pool != NULL) {
 468                 uint32_t vi_count = 0;
 469
 470                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 471                         goto fail1;
 472
 473                 *evq_countp = vi_count;
 474                 *rxq_countp = vi_count;
 475                 *txq_countp = vi_count;
 476         } else {
 477                 /* Use NIC limits as default value */
 478                 *evq_countp = encp->enc_evq_limit;
 479                 *rxq_countp = encp->enc_rxq_limit;
 480                 *txq_countp = encp->enc_txq_limit;
 481         }
 482
 483         return (0);
 484
 485 fail1:
 486         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 487
 488         return (rc);
 489 }
 490
 491
 492         __checkReturn   efx_rc_t
 493 efx_nic_init(
 494         __in            efx_nic_t *enp)
 495 {
 496         const efx_nic_ops_t *enop = enp->en_enop;
 497         efx_rc_t rc;
 498
 499         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 500         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 501
 502         if (enp->en_mod_flags & EFX_MOD_NIC) {
 503                 rc = EINVAL;
 504                 goto fail1;
 505         }
 506
 507         if ((rc = enop->eno_init(enp)) != 0)
 508                 goto fail2;
 509
 510         enp->en_mod_flags |= EFX_MOD_NIC;
 511
 512         return (0);
 513
 514 fail2:
 515         EFSYS_PROBE(fail2);
 516 fail1:
 517         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 518
 519         return (rc);
 520 }
 521
 522                         void
 523 efx_nic_fini(
 524         __in            efx_nic_t *enp)
 525 {
 526         const efx_nic_ops_t *enop = enp->en_enop;
 527
 528         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 529         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 530         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 531         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 532         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 533         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 534         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 535
 536         enop->eno_fini(enp);
 537
 538         enp->en_mod_flags &= ~EFX_MOD_NIC;
 539 }
 540
 541                         void
 542 efx_nic_unprobe(
 543         __in            efx_nic_t *enp)
 544 {
 545         const efx_nic_ops_t *enop = enp->en_enop;
 546
 547         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 548 #if EFSYS_OPT_MCDI
 549         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 550 #endif  /* EFSYS_OPT_MCDI */
 551         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 552         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 553         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 554         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 555         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 556         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 557
 558         efx_phy_unprobe(enp);
 559
 560         enop->eno_unprobe(enp);
 561
 562         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 563 }
 564
 565                         void
 566 efx_nic_destroy(
 567         __in    efx_nic_t *enp)
 568 {
 569         efsys_identifier_t *esip = enp->en_esip;
 570
 571         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 572         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 573
 574         enp->en_family = EFX_FAMILY_INVALID;
 575         enp->en_esip = NULL;
 576         enp->en_esbp = NULL;
 577         enp->en_eslp = NULL;
 578
 579         enp->en_enop = NULL;
 580
 581         enp->en_magic = 0;
 582
 583         /* Free the NIC object */
 584         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 585 }
 586
 587         __checkReturn   efx_rc_t
 588 efx_nic_reset(
 589         __in            efx_nic_t *enp)
 590 {
 591         const efx_nic_ops_t *enop = enp->en_enop;
 592         unsigned int mod_flags;
 593         efx_rc_t rc;
 594
 595         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 596         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 597         /*
 598          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 599          * (which we do not reset here) must have been shut down or never
 600          * initialized.
 601          *
 602          * A rule of thumb here is: If the controller or MC reboots, is *any*
 603          * state lost. If it's lost and needs reapplying, then the module
 604          * *must* not be initialised during the reset.
 605          */
 606         mod_flags = enp->en_mod_flags;
 607         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 608             EFX_MOD_VPD | EFX_MOD_MON);
 609 #if EFSYS_OPT_TUNNEL
 610         mod_flags &= ~EFX_MOD_TUNNEL;
 611 #endif /* EFSYS_OPT_TUNNEL */
 612         EFSYS_ASSERT3U(mod_flags, ==, 0);
 613         if (mod_flags != 0) {
 614                 rc = EINVAL;
 615                 goto fail1;
 616         }
 617
 618         if ((rc = enop->eno_reset(enp)) != 0)
 619                 goto fail2;
 620
 621         return (0);
 622
 623 fail2:
 624         EFSYS_PROBE(fail2);
 625 fail1:
 626         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 627
 628         return (rc);
 629 }
 630
 631                         const efx_nic_cfg_t *
 632 efx_nic_cfg_get(
 633         __in            const efx_nic_t *enp)
 634 {
 635         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 636         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 637
 638         return (&(enp->en_nic_cfg));
 639 }
 640
 641         __checkReturn           efx_rc_t
 642 efx_nic_get_fw_version(
 643         __in                    efx_nic_t *enp,
 644         __out                   efx_nic_fw_info_t *enfip)
 645 {
 646         uint16_t mc_fw_version[4];
 647         efx_rc_t rc;
 648
 649         if (enfip == NULL) {
 650                 rc = EINVAL;
 651                 goto fail1;
 652         }
 653
 654         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 655         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 656
 657         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 658         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 659             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 660         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 661             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 662         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 663             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 664         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 665             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 666         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 667             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 668
 669         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 670         if (rc != 0)
 671                 goto fail2;
 672
 673         rc = efx_mcdi_get_capabilities(enp, NULL,
 674             &enfip->enfi_rx_dpcpu_fw_id,
 675             &enfip->enfi_tx_dpcpu_fw_id,
 676             NULL, NULL);
 677         if (rc == 0) {
 678                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 679         } else if (rc == ENOTSUP) {
 680                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 681                 enfip->enfi_rx_dpcpu_fw_id = 0;
 682                 enfip->enfi_tx_dpcpu_fw_id = 0;
 683         } else {
 684                 goto fail3;
 685         }
 686
 687         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 688             sizeof (mc_fw_version));
 689
 690         return (0);
 691
 692 fail3:
 693         EFSYS_PROBE(fail3);
 694 fail2:
 695         EFSYS_PROBE(fail2);
 696 fail1:
 697         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 698
 699         return (rc);
 700 }
 701
 702         __checkReturn   boolean_t
 703 efx_nic_hw_unavailable(
 704         __in            efx_nic_t *enp)
 705 {
 706         const efx_nic_ops_t *enop = enp->en_enop;
 707
 708         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 709         /* NOTE: can be used by MCDI before NIC probe */
 710
 711         if (enop->eno_hw_unavailable != NULL) {
 712                 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
 713                         goto unavail;
 714         }
 715
 716         return (B_FALSE);
 717
 718 unavail:
 719         return (B_TRUE);
 720 }
 721
 722                         void
 723 efx_nic_set_hw_unavailable(
 724         __in            efx_nic_t *enp)
 725 {
 726         const efx_nic_ops_t *enop = enp->en_enop;
 727
 728         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 729
 730         if (enop->eno_set_hw_unavailable != NULL)
 731                 enop->eno_set_hw_unavailable(enp);
 732 }
 733
 734
 735 #if EFSYS_OPT_DIAG
 736
 737         __checkReturn   efx_rc_t
 738 efx_nic_register_test(
 739         __in            efx_nic_t *enp)
 740 {
 741         const efx_nic_ops_t *enop = enp->en_enop;
 742         efx_rc_t rc;
 743
 744         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 745         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 746         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 747
 748         if ((rc = enop->eno_register_test(enp)) != 0)
 749                 goto fail1;
 750
 751         return (0);
 752
 753 fail1:
 754         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 755
 756         return (rc);
 757 }
 758
 759 #endif  /* EFSYS_OPT_DIAG */
 760
 761 #if EFSYS_OPT_LOOPBACK
 762
 763 extern                  void
 764 efx_loopback_mask(
 765         __in    efx_loopback_kind_t loopback_kind,
 766         __out   efx_qword_t *maskp)
 767 {
 768         efx_qword_t mask;
 769
 770         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 771         EFSYS_ASSERT(maskp != NULL);
 772
 773         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 774 #define LOOPBACK_CHECK(_mcdi, _efx) \
 775         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 776
 777         LOOPBACK_CHECK(NONE, OFF);
 778         LOOPBACK_CHECK(DATA, DATA);
 779         LOOPBACK_CHECK(GMAC, GMAC);
 780         LOOPBACK_CHECK(XGMII, XGMII);
 781         LOOPBACK_CHECK(XGXS, XGXS);
 782         LOOPBACK_CHECK(XAUI, XAUI);
 783         LOOPBACK_CHECK(GMII, GMII);
 784         LOOPBACK_CHECK(SGMII, SGMII);
 785         LOOPBACK_CHECK(XGBR, XGBR);
 786         LOOPBACK_CHECK(XFI, XFI);
 787         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 788         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 789         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 790         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 791         LOOPBACK_CHECK(GPHY, GPHY);
 792         LOOPBACK_CHECK(PHYXS, PHY_XS);
 793         LOOPBACK_CHECK(PCS, PCS);
 794         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 795         LOOPBACK_CHECK(XPORT, XPORT);
 796         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 797         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 798         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 799         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 800         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 801         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 802         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 803         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 804         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 805         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 806         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 807         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 808         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 809         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 810         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 811         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 812         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 813         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 814         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 815 #undef LOOPBACK_CHECK
 816
 817         /* Build bitmask of possible loopback types */
 818         EFX_ZERO_QWORD(mask);
 819
 820         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 821             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 822                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 823         }
 824
 825         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 826             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 827                 /*
 828                  * The "MAC" grouping has historically been used by drivers to
 829                  * mean loopbacks supported by on-chip hardware. Keep that
 830                  * meaning here, and include on-chip PHY layer loopbacks.
 831                  */
 832                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 833                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 834                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 835                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 836                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 837                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 838                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 839                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 840                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 841                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 842                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 843                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 844                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 845                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 846                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 847                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 848         }
 849
 850         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 851             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 852                 /*
 853                  * The "PHY" grouping has historically been used by drivers to
 854                  * mean loopbacks supported by off-chip hardware. Keep that
 855                  * meaning here.
 856                  */
 857                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 858                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 859                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 860                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 861         }
 862
 863         *maskp = mask;
 864 }
 865
 866         __checkReturn   efx_rc_t
 867 efx_mcdi_get_loopback_modes(
 868         __in            efx_nic_t *enp)
 869 {
 870         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 871         efx_mcdi_req_t req;
 872         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 873                 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
 874         efx_qword_t mask;
 875         efx_qword_t modes;
 876         efx_rc_t rc;
 877
 878         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 879         req.emr_in_buf = payload;
 880         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 881         req.emr_out_buf = payload;
 882         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 883
 884         efx_mcdi_execute(enp, &req);
 885
 886         if (req.emr_rc != 0) {
 887                 rc = req.emr_rc;
 888                 goto fail1;
 889         }
 890
 891         if (req.emr_out_length_used <
 892             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 893             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 894                 rc = EMSGSIZE;
 895                 goto fail2;
 896         }
 897
 898         /*
 899          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 900          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 901          */
 902         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 903
 904         EFX_AND_QWORD(mask,
 905             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 906
 907         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 908         EFX_AND_QWORD(modes, mask);
 909         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 910
 911         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 912         EFX_AND_QWORD(modes, mask);
 913         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 914
 915         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 916         EFX_AND_QWORD(modes, mask);
 917         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 918
 919         if (req.emr_out_length_used >=
 920             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 921             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 922                 /* Response includes 40G loopback modes */
 923                 modes = *MCDI_OUT2(req, efx_qword_t,
 924                     GET_LOOPBACK_MODES_OUT_40G);
 925                 EFX_AND_QWORD(modes, mask);
 926                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 927         }
 928
 929         if (req.emr_out_length_used >=
 930             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
 931             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
 932                 /* Response includes 25G loopback modes */
 933                 modes = *MCDI_OUT2(req, efx_qword_t,
 934                     GET_LOOPBACK_MODES_OUT_V2_25G);
 935                 EFX_AND_QWORD(modes, mask);
 936                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
 937         }
 938
 939         if (req.emr_out_length_used >=
 940             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
 941             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
 942                 /* Response includes 50G loopback modes */
 943                 modes = *MCDI_OUT2(req, efx_qword_t,
 944                     GET_LOOPBACK_MODES_OUT_V2_50G);
 945                 EFX_AND_QWORD(modes, mask);
 946                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
 947         }
 948
 949         if (req.emr_out_length_used >=
 950             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
 951             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
 952                 /* Response includes 100G loopback modes */
 953                 modes = *MCDI_OUT2(req, efx_qword_t,
 954                     GET_LOOPBACK_MODES_OUT_V2_100G);
 955                 EFX_AND_QWORD(modes, mask);
 956                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
 957         }
 958
 959         EFX_ZERO_QWORD(modes);
 960         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 961         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 962         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 963         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 964         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 965         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
 966         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
 967         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
 968         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 969
 970         return (0);
 971
 972 fail2:
 973         EFSYS_PROBE(fail2);
 974 fail1:
 975         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 976
 977         return (rc);
 978 }
 979
 980 #endif /* EFSYS_OPT_LOOPBACK */
 981
 982         __checkReturn   efx_rc_t
 983 efx_nic_calculate_pcie_link_bandwidth(
 984         __in            uint32_t pcie_link_width,
 985         __in            uint32_t pcie_link_gen,
 986         __out           uint32_t *bandwidth_mbpsp)
 987 {
 988         uint32_t lane_bandwidth;
 989         uint32_t total_bandwidth;
 990         efx_rc_t rc;
 991
 992         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
 993             !ISP2(pcie_link_width)) {
 994                 rc = EINVAL;
 995                 goto fail1;
 996         }
 997
 998         switch (pcie_link_gen) {
 999         case EFX_PCIE_LINK_SPEED_GEN1:
1000                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
1001                 lane_bandwidth = 2000;
1002                 break;
1003         case EFX_PCIE_LINK_SPEED_GEN2:
1004                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
1005                 lane_bandwidth = 4000;
1006                 break;
1007         case EFX_PCIE_LINK_SPEED_GEN3:
1008                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
1009                 lane_bandwidth = 7877;
1010                 break;
1011         default:
1012                 rc = EINVAL;
1013                 goto fail2;
1014         }
1015
1016         total_bandwidth = lane_bandwidth * pcie_link_width;
1017         *bandwidth_mbpsp = total_bandwidth;
1018
1019         return (0);
1020
1021 fail2:
1022         EFSYS_PROBE(fail2);
1023 fail1:
1024         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1025
1026         return (rc);
1027 }
1028
1029 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1030
1031         __checkReturn   efx_rc_t
1032 efx_nic_get_fw_subvariant(
1033         __in            efx_nic_t *enp,
1034         __out           efx_nic_fw_subvariant_t *subvariantp)
1035 {
1036         efx_rc_t rc;
1037         uint32_t value;
1038
1039         rc = efx_mcdi_get_nic_global(enp,
1040             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1041         if (rc != 0)
1042                 goto fail1;
1043
1044         /* Mapping is not required since values match MCDI */
1045         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1046             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1047         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1048             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1049
1050         switch (value) {
1051         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1052         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1053                 *subvariantp = value;
1054                 break;
1055         default:
1056                 rc = EINVAL;
1057                 goto fail2;
1058         }
1059
1060         return (0);
1061
1062 fail2:
1063         EFSYS_PROBE(fail2);
1064
1065 fail1:
1066         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1067
1068         return (rc);
1069 }
1070
1071         __checkReturn   efx_rc_t
1072 efx_nic_set_fw_subvariant(
1073         __in            efx_nic_t *enp,
1074         __in            efx_nic_fw_subvariant_t subvariant)
1075 {
1076         efx_rc_t rc;
1077
1078         switch (subvariant) {
1079         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1080         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1081                 /* Mapping is not required since values match MCDI */
1082                 break;
1083         default:
1084                 rc = EINVAL;
1085                 goto fail1;
1086         }
1087
1088         rc = efx_mcdi_set_nic_global(enp,
1089             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1090         if (rc != 0)
1091                 goto fail2;
1092
1093         return (0);
1094
1095 fail2:
1096         EFSYS_PROBE(fail2);
1097
1098 fail1:
1099         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1100
1101         return (rc);
1102 }
1103
1104 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1105
1106         __checkReturn   efx_rc_t
1107 efx_nic_check_pcie_link_speed(
1108         __in            efx_nic_t *enp,
1109         __in            uint32_t pcie_link_width,
1110         __in            uint32_t pcie_link_gen,
1111         __out           efx_pcie_link_performance_t *resultp)
1112 {
1113         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1114         uint32_t bandwidth;
1115         efx_pcie_link_performance_t result;
1116         efx_rc_t rc;
1117
1118         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1119             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1120             (pcie_link_gen == 0)) {
1121                 /*
1122                  * No usable info on what is required and/or in use. In virtual
1123                  * machines, sometimes the PCIe link width is reported as 0 or
1124                  * 32, or the speed as 0.
1125                  */
1126                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1127                 goto out;
1128         }
1129
1130         /* Calculate the available bandwidth in megabits per second */
1131         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1132                                             pcie_link_gen, &bandwidth);
1133         if (rc != 0)
1134                 goto fail1;
1135
1136         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1137                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1138         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1139                 /* The link provides enough bandwidth but not optimal latency */
1140                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1141         } else {
1142                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1143         }
1144
1145 out:
1146         *resultp = result;
1147
1148         return (0);
1149
1150 fail1:
1151         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1152
1153         return (rc);
1154 }