1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
11 __checkReturn efx_rc_t
15 __out efx_family_t *efp,
16 __out unsigned int *membarp)
18 if (venid == EFX_PCI_VENID_SFC) {
21 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
23 * Hardware default for PF0 of uninitialised Siena.
24 * manftest must be able to cope with this device id.
26 case EFX_PCI_DEVID_BETHPAGE:
27 case EFX_PCI_DEVID_SIENA:
28 *efp = EFX_FAMILY_SIENA;
29 *membarp = EFX_MEM_BAR_SIENA;
31 #endif /* EFSYS_OPT_SIENA */
33 #if EFSYS_OPT_HUNTINGTON
34 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
36 * Hardware default for PF0 of uninitialised Huntington.
37 * manftest must be able to cope with this device id.
39 case EFX_PCI_DEVID_FARMINGDALE:
40 case EFX_PCI_DEVID_GREENPORT:
41 *efp = EFX_FAMILY_HUNTINGTON;
42 *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
45 case EFX_PCI_DEVID_FARMINGDALE_VF:
46 case EFX_PCI_DEVID_GREENPORT_VF:
47 *efp = EFX_FAMILY_HUNTINGTON;
48 *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
55 * Hardware default for PF0 of uninitialised Medford.
56 * manftest must be able to cope with this device id.
58 case EFX_PCI_DEVID_MEDFORD:
59 *efp = EFX_FAMILY_MEDFORD;
60 *membarp = EFX_MEM_BAR_MEDFORD_PF;
63 case EFX_PCI_DEVID_MEDFORD_VF:
64 *efp = EFX_FAMILY_MEDFORD;
65 *membarp = EFX_MEM_BAR_MEDFORD_VF;
67 #endif /* EFSYS_OPT_MEDFORD */
69 #if EFSYS_OPT_MEDFORD2
70 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
72 * Hardware default for PF0 of uninitialised Medford2.
73 * manftest must be able to cope with this device id.
75 case EFX_PCI_DEVID_MEDFORD2:
76 case EFX_PCI_DEVID_MEDFORD2_VF:
77 *efp = EFX_FAMILY_MEDFORD2;
78 *membarp = EFX_MEM_BAR_MEDFORD2;
80 #endif /* EFSYS_OPT_MEDFORD2 */
82 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
88 *efp = EFX_FAMILY_INVALID;
95 static const efx_nic_ops_t __efx_nic_siena_ops = {
96 siena_nic_probe, /* eno_probe */
97 NULL, /* eno_board_cfg */
98 NULL, /* eno_set_drv_limits */
99 siena_nic_reset, /* eno_reset */
100 siena_nic_init, /* eno_init */
101 NULL, /* eno_get_vi_pool */
102 NULL, /* eno_get_bar_region */
103 NULL, /* eno_hw_unavailable */
104 NULL, /* eno_set_hw_unavailable */
106 siena_nic_register_test, /* eno_register_test */
107 #endif /* EFSYS_OPT_DIAG */
108 siena_nic_fini, /* eno_fini */
109 siena_nic_unprobe, /* eno_unprobe */
112 #endif /* EFSYS_OPT_SIENA */
114 #if EFSYS_OPT_HUNTINGTON
116 static const efx_nic_ops_t __efx_nic_hunt_ops = {
117 ef10_nic_probe, /* eno_probe */
118 hunt_board_cfg, /* eno_board_cfg */
119 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
120 ef10_nic_reset, /* eno_reset */
121 ef10_nic_init, /* eno_init */
122 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
123 ef10_nic_get_bar_region, /* eno_get_bar_region */
124 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
125 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
127 ef10_nic_register_test, /* eno_register_test */
128 #endif /* EFSYS_OPT_DIAG */
129 ef10_nic_fini, /* eno_fini */
130 ef10_nic_unprobe, /* eno_unprobe */
133 #endif /* EFSYS_OPT_HUNTINGTON */
135 #if EFSYS_OPT_MEDFORD
137 static const efx_nic_ops_t __efx_nic_medford_ops = {
138 ef10_nic_probe, /* eno_probe */
139 medford_board_cfg, /* eno_board_cfg */
140 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
141 ef10_nic_reset, /* eno_reset */
142 ef10_nic_init, /* eno_init */
143 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
144 ef10_nic_get_bar_region, /* eno_get_bar_region */
145 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
146 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
148 ef10_nic_register_test, /* eno_register_test */
149 #endif /* EFSYS_OPT_DIAG */
150 ef10_nic_fini, /* eno_fini */
151 ef10_nic_unprobe, /* eno_unprobe */
154 #endif /* EFSYS_OPT_MEDFORD */
156 #if EFSYS_OPT_MEDFORD2
158 static const efx_nic_ops_t __efx_nic_medford2_ops = {
159 ef10_nic_probe, /* eno_probe */
160 medford2_board_cfg, /* eno_board_cfg */
161 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
162 ef10_nic_reset, /* eno_reset */
163 ef10_nic_init, /* eno_init */
164 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
165 ef10_nic_get_bar_region, /* eno_get_bar_region */
166 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
167 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
169 ef10_nic_register_test, /* eno_register_test */
170 #endif /* EFSYS_OPT_DIAG */
171 ef10_nic_fini, /* eno_fini */
172 ef10_nic_unprobe, /* eno_unprobe */
175 #endif /* EFSYS_OPT_MEDFORD2 */
178 __checkReturn efx_rc_t
180 __in efx_family_t family,
181 __in efsys_identifier_t *esip,
182 __in efsys_bar_t *esbp,
183 __in efsys_lock_t *eslp,
184 __deref_out efx_nic_t **enpp)
189 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
190 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
192 /* Allocate a NIC object */
193 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
200 enp->en_magic = EFX_NIC_MAGIC;
204 case EFX_FAMILY_SIENA:
205 enp->en_enop = &__efx_nic_siena_ops;
208 EFX_FEATURE_LFSR_HASH_INSERT |
209 EFX_FEATURE_LINK_EVENTS |
210 EFX_FEATURE_PERIODIC_MAC_STATS |
212 EFX_FEATURE_LOOKAHEAD_SPLIT |
213 EFX_FEATURE_MAC_HEADER_FILTERS |
214 EFX_FEATURE_TX_SRC_FILTERS;
216 #endif /* EFSYS_OPT_SIENA */
218 #if EFSYS_OPT_HUNTINGTON
219 case EFX_FAMILY_HUNTINGTON:
220 enp->en_enop = &__efx_nic_hunt_ops;
223 EFX_FEATURE_LINK_EVENTS |
224 EFX_FEATURE_PERIODIC_MAC_STATS |
226 EFX_FEATURE_MAC_HEADER_FILTERS |
227 EFX_FEATURE_MCDI_DMA |
228 EFX_FEATURE_PIO_BUFFERS |
229 EFX_FEATURE_FW_ASSISTED_TSO |
230 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
231 EFX_FEATURE_PACKED_STREAM;
233 #endif /* EFSYS_OPT_HUNTINGTON */
235 #if EFSYS_OPT_MEDFORD
236 case EFX_FAMILY_MEDFORD:
237 enp->en_enop = &__efx_nic_medford_ops;
239 * FW_ASSISTED_TSO omitted as Medford only supports firmware
240 * assisted TSO version 2, not the v1 scheme used on Huntington.
244 EFX_FEATURE_LINK_EVENTS |
245 EFX_FEATURE_PERIODIC_MAC_STATS |
247 EFX_FEATURE_MAC_HEADER_FILTERS |
248 EFX_FEATURE_MCDI_DMA |
249 EFX_FEATURE_PIO_BUFFERS |
250 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
251 EFX_FEATURE_PACKED_STREAM;
253 #endif /* EFSYS_OPT_MEDFORD */
255 #if EFSYS_OPT_MEDFORD2
256 case EFX_FAMILY_MEDFORD2:
257 enp->en_enop = &__efx_nic_medford2_ops;
260 EFX_FEATURE_LINK_EVENTS |
261 EFX_FEATURE_PERIODIC_MAC_STATS |
263 EFX_FEATURE_MAC_HEADER_FILTERS |
264 EFX_FEATURE_MCDI_DMA |
265 EFX_FEATURE_PIO_BUFFERS |
266 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
267 EFX_FEATURE_PACKED_STREAM;
269 #endif /* EFSYS_OPT_MEDFORD2 */
276 enp->en_family = family;
290 /* Free the NIC object */
291 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
294 EFSYS_PROBE1(fail1, efx_rc_t, rc);
299 __checkReturn efx_rc_t
302 __in efx_fw_variant_t efv)
304 const efx_nic_ops_t *enop;
307 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
309 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
310 #endif /* EFSYS_OPT_MCDI */
311 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
313 /* Ensure FW variant codes match with MC_CMD_FW codes */
314 EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
315 MC_CMD_FW_FULL_FEATURED);
316 EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
317 MC_CMD_FW_LOW_LATENCY);
318 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
319 MC_CMD_FW_PACKED_STREAM);
320 EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
321 MC_CMD_FW_HIGH_TX_RATE);
322 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
323 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
324 EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
325 MC_CMD_FW_RULES_ENGINE);
326 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
328 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
329 (int)MC_CMD_FW_DONT_CARE);
334 if ((rc = enop->eno_probe(enp)) != 0)
337 if ((rc = efx_phy_probe(enp)) != 0)
340 enp->en_mod_flags |= EFX_MOD_PROBE;
347 enop->eno_unprobe(enp);
350 EFSYS_PROBE1(fail1, efx_rc_t, rc);
355 __checkReturn efx_rc_t
356 efx_nic_set_drv_limits(
357 __inout efx_nic_t *enp,
358 __in efx_drv_limits_t *edlp)
360 const efx_nic_ops_t *enop = enp->en_enop;
363 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
364 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
366 if (enop->eno_set_drv_limits != NULL) {
367 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
374 EFSYS_PROBE1(fail1, efx_rc_t, rc);
379 __checkReturn efx_rc_t
380 efx_nic_get_bar_region(
382 __in efx_nic_region_t region,
383 __out uint32_t *offsetp,
386 const efx_nic_ops_t *enop = enp->en_enop;
389 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
390 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
391 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
393 if (enop->eno_get_bar_region == NULL) {
397 if ((rc = (enop->eno_get_bar_region)(enp,
398 region, offsetp, sizep)) != 0) {
408 EFSYS_PROBE1(fail1, efx_rc_t, rc);
414 __checkReturn efx_rc_t
417 __out uint32_t *evq_countp,
418 __out uint32_t *rxq_countp,
419 __out uint32_t *txq_countp)
421 const efx_nic_ops_t *enop = enp->en_enop;
422 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
425 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
426 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
427 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
429 if (enop->eno_get_vi_pool != NULL) {
430 uint32_t vi_count = 0;
432 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
435 *evq_countp = vi_count;
436 *rxq_countp = vi_count;
437 *txq_countp = vi_count;
439 /* Use NIC limits as default value */
440 *evq_countp = encp->enc_evq_limit;
441 *rxq_countp = encp->enc_rxq_limit;
442 *txq_countp = encp->enc_txq_limit;
448 EFSYS_PROBE1(fail1, efx_rc_t, rc);
454 __checkReturn efx_rc_t
458 const efx_nic_ops_t *enop = enp->en_enop;
461 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
462 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
464 if (enp->en_mod_flags & EFX_MOD_NIC) {
469 if ((rc = enop->eno_init(enp)) != 0)
472 enp->en_mod_flags |= EFX_MOD_NIC;
479 EFSYS_PROBE1(fail1, efx_rc_t, rc);
488 const efx_nic_ops_t *enop = enp->en_enop;
490 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
491 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
492 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
493 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
494 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
495 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
496 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
500 enp->en_mod_flags &= ~EFX_MOD_NIC;
507 const efx_nic_ops_t *enop = enp->en_enop;
509 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
511 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
512 #endif /* EFSYS_OPT_MCDI */
513 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
514 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
515 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
516 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
517 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
518 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
520 efx_phy_unprobe(enp);
522 enop->eno_unprobe(enp);
524 enp->en_mod_flags &= ~EFX_MOD_PROBE;
531 efsys_identifier_t *esip = enp->en_esip;
533 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
534 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
536 enp->en_family = EFX_FAMILY_INVALID;
545 /* Free the NIC object */
546 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
549 __checkReturn efx_rc_t
553 const efx_nic_ops_t *enop = enp->en_enop;
554 unsigned int mod_flags;
557 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
558 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
560 * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
561 * (which we do not reset here) must have been shut down or never
564 * A rule of thumb here is: If the controller or MC reboots, is *any*
565 * state lost. If it's lost and needs reapplying, then the module
566 * *must* not be initialised during the reset.
568 mod_flags = enp->en_mod_flags;
569 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
570 EFX_MOD_VPD | EFX_MOD_MON);
572 mod_flags &= ~EFX_MOD_TUNNEL;
573 #endif /* EFSYS_OPT_TUNNEL */
574 EFSYS_ASSERT3U(mod_flags, ==, 0);
575 if (mod_flags != 0) {
580 if ((rc = enop->eno_reset(enp)) != 0)
588 EFSYS_PROBE1(fail1, efx_rc_t, rc);
593 const efx_nic_cfg_t *
597 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
598 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
600 return (&(enp->en_nic_cfg));
603 __checkReturn efx_rc_t
604 efx_nic_get_fw_version(
606 __out efx_nic_fw_info_t *enfip)
608 uint16_t mc_fw_version[4];
616 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
617 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
619 /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
620 EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
621 MC_CMD_GET_CAPABILITIES_OUT_RXDP);
622 EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
623 MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
624 EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
625 MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
626 EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
627 MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
628 EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
629 MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
631 rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
635 rc = efx_mcdi_get_capabilities(enp, NULL,
636 &enfip->enfi_rx_dpcpu_fw_id,
637 &enfip->enfi_tx_dpcpu_fw_id,
640 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
641 } else if (rc == ENOTSUP) {
642 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
643 enfip->enfi_rx_dpcpu_fw_id = 0;
644 enfip->enfi_tx_dpcpu_fw_id = 0;
649 memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
650 sizeof (mc_fw_version));
659 EFSYS_PROBE1(fail1, efx_rc_t, rc);
664 __checkReturn boolean_t
665 efx_nic_hw_unavailable(
668 const efx_nic_ops_t *enop = enp->en_enop;
670 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
671 /* NOTE: can be used by MCDI before NIC probe */
673 if (enop->eno_hw_unavailable != NULL) {
674 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
685 efx_nic_set_hw_unavailable(
688 const efx_nic_ops_t *enop = enp->en_enop;
690 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
692 if (enop->eno_set_hw_unavailable != NULL)
693 enop->eno_set_hw_unavailable(enp);
699 __checkReturn efx_rc_t
700 efx_nic_register_test(
703 const efx_nic_ops_t *enop = enp->en_enop;
706 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
707 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
708 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
710 if ((rc = enop->eno_register_test(enp)) != 0)
716 EFSYS_PROBE1(fail1, efx_rc_t, rc);
721 #endif /* EFSYS_OPT_DIAG */
723 #if EFSYS_OPT_LOOPBACK
727 __in efx_loopback_kind_t loopback_kind,
728 __out efx_qword_t *maskp)
732 EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
733 EFSYS_ASSERT(maskp != NULL);
735 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
736 #define LOOPBACK_CHECK(_mcdi, _efx) \
737 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
739 LOOPBACK_CHECK(NONE, OFF);
740 LOOPBACK_CHECK(DATA, DATA);
741 LOOPBACK_CHECK(GMAC, GMAC);
742 LOOPBACK_CHECK(XGMII, XGMII);
743 LOOPBACK_CHECK(XGXS, XGXS);
744 LOOPBACK_CHECK(XAUI, XAUI);
745 LOOPBACK_CHECK(GMII, GMII);
746 LOOPBACK_CHECK(SGMII, SGMII);
747 LOOPBACK_CHECK(XGBR, XGBR);
748 LOOPBACK_CHECK(XFI, XFI);
749 LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
750 LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
751 LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
752 LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
753 LOOPBACK_CHECK(GPHY, GPHY);
754 LOOPBACK_CHECK(PHYXS, PHY_XS);
755 LOOPBACK_CHECK(PCS, PCS);
756 LOOPBACK_CHECK(PMAPMD, PMA_PMD);
757 LOOPBACK_CHECK(XPORT, XPORT);
758 LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
759 LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
760 LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
761 LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
762 LOOPBACK_CHECK(GMII_WS, GMII_WS);
763 LOOPBACK_CHECK(XFI_WS, XFI_WS);
764 LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
765 LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
766 LOOPBACK_CHECK(PMA_INT, PMA_INT);
767 LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
768 LOOPBACK_CHECK(SD_FAR, SD_FAR);
769 LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
770 LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
771 LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
772 LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
773 LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
774 LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
775 LOOPBACK_CHECK(DATA_WS, DATA_WS);
776 LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
777 #undef LOOPBACK_CHECK
779 /* Build bitmask of possible loopback types */
780 EFX_ZERO_QWORD(mask);
782 if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
783 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
784 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
787 if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
788 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
790 * The "MAC" grouping has historically been used by drivers to
791 * mean loopbacks supported by on-chip hardware. Keep that
792 * meaning here, and include on-chip PHY layer loopbacks.
794 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
795 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
796 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
797 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
798 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
799 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
800 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
801 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
802 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
803 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
804 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
805 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
806 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
807 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
808 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
809 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
812 if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
813 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
815 * The "PHY" grouping has historically been used by drivers to
816 * mean loopbacks supported by off-chip hardware. Keep that
819 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
820 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
821 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
822 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
828 __checkReturn efx_rc_t
829 efx_mcdi_get_loopback_modes(
832 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
834 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
835 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
840 req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
841 req.emr_in_buf = payload;
842 req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
843 req.emr_out_buf = payload;
844 req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
846 efx_mcdi_execute(enp, &req);
848 if (req.emr_rc != 0) {
853 if (req.emr_out_length_used <
854 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
855 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
861 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
862 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
864 efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
867 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
869 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
870 EFX_AND_QWORD(modes, mask);
871 encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
873 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
874 EFX_AND_QWORD(modes, mask);
875 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
877 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
878 EFX_AND_QWORD(modes, mask);
879 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
881 if (req.emr_out_length_used >=
882 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
883 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
884 /* Response includes 40G loopback modes */
885 modes = *MCDI_OUT2(req, efx_qword_t,
886 GET_LOOPBACK_MODES_OUT_40G);
887 EFX_AND_QWORD(modes, mask);
888 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
891 if (req.emr_out_length_used >=
892 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
893 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
894 /* Response includes 25G loopback modes */
895 modes = *MCDI_OUT2(req, efx_qword_t,
896 GET_LOOPBACK_MODES_OUT_V2_25G);
897 EFX_AND_QWORD(modes, mask);
898 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
901 if (req.emr_out_length_used >=
902 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
903 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
904 /* Response includes 50G loopback modes */
905 modes = *MCDI_OUT2(req, efx_qword_t,
906 GET_LOOPBACK_MODES_OUT_V2_50G);
907 EFX_AND_QWORD(modes, mask);
908 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
911 if (req.emr_out_length_used >=
912 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
913 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
914 /* Response includes 100G loopback modes */
915 modes = *MCDI_OUT2(req, efx_qword_t,
916 GET_LOOPBACK_MODES_OUT_V2_100G);
917 EFX_AND_QWORD(modes, mask);
918 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
921 EFX_ZERO_QWORD(modes);
922 EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
923 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
924 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
925 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
926 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
927 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
928 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
929 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
930 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
937 EFSYS_PROBE1(fail1, efx_rc_t, rc);
942 #endif /* EFSYS_OPT_LOOPBACK */
944 __checkReturn efx_rc_t
945 efx_nic_calculate_pcie_link_bandwidth(
946 __in uint32_t pcie_link_width,
947 __in uint32_t pcie_link_gen,
948 __out uint32_t *bandwidth_mbpsp)
950 uint32_t lane_bandwidth;
951 uint32_t total_bandwidth;
954 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
955 !ISP2(pcie_link_width)) {
960 switch (pcie_link_gen) {
961 case EFX_PCIE_LINK_SPEED_GEN1:
962 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
963 lane_bandwidth = 2000;
965 case EFX_PCIE_LINK_SPEED_GEN2:
966 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
967 lane_bandwidth = 4000;
969 case EFX_PCIE_LINK_SPEED_GEN3:
970 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
971 lane_bandwidth = 7877;
978 total_bandwidth = lane_bandwidth * pcie_link_width;
979 *bandwidth_mbpsp = total_bandwidth;
986 EFSYS_PROBE1(fail1, efx_rc_t, rc);
991 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
993 __checkReturn efx_rc_t
994 efx_nic_get_fw_subvariant(
996 __out efx_nic_fw_subvariant_t *subvariantp)
1001 rc = efx_mcdi_get_nic_global(enp,
1002 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1006 /* Mapping is not required since values match MCDI */
1007 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1008 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1009 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1010 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1013 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1014 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1015 *subvariantp = value;
1028 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1033 __checkReturn efx_rc_t
1034 efx_nic_set_fw_subvariant(
1035 __in efx_nic_t *enp,
1036 __in efx_nic_fw_subvariant_t subvariant)
1040 switch (subvariant) {
1041 case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1042 case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1043 /* Mapping is not required since values match MCDI */
1050 rc = efx_mcdi_set_nic_global(enp,
1051 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1061 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1066 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1068 __checkReturn efx_rc_t
1069 efx_nic_check_pcie_link_speed(
1070 __in efx_nic_t *enp,
1071 __in uint32_t pcie_link_width,
1072 __in uint32_t pcie_link_gen,
1073 __out efx_pcie_link_performance_t *resultp)
1075 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1077 efx_pcie_link_performance_t result;
1080 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1081 (pcie_link_width == 0) || (pcie_link_width == 32) ||
1082 (pcie_link_gen == 0)) {
1084 * No usable info on what is required and/or in use. In virtual
1085 * machines, sometimes the PCIe link width is reported as 0 or
1086 * 32, or the speed as 0.
1088 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1092 /* Calculate the available bandwidth in megabits per second */
1093 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1094 pcie_link_gen, &bandwidth);
1098 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1099 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1100 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1101 /* The link provides enough bandwidth but not optimal latency */
1102 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1104 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1113 EFSYS_PROBE1(fail1, efx_rc_t, rc);