1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
11 __checkReturn efx_rc_t
15 __out efx_family_t *efp,
16 __out unsigned int *membarp)
18 if (venid == EFX_PCI_VENID_SFC) {
21 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
23 * Hardware default for PF0 of uninitialised Siena.
24 * manftest must be able to cope with this device id.
26 case EFX_PCI_DEVID_BETHPAGE:
27 case EFX_PCI_DEVID_SIENA:
28 *efp = EFX_FAMILY_SIENA;
29 *membarp = EFX_MEM_BAR_SIENA;
31 #endif /* EFSYS_OPT_SIENA */
33 #if EFSYS_OPT_HUNTINGTON
34 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
36 * Hardware default for PF0 of uninitialised Huntington.
37 * manftest must be able to cope with this device id.
39 case EFX_PCI_DEVID_FARMINGDALE:
40 case EFX_PCI_DEVID_GREENPORT:
41 *efp = EFX_FAMILY_HUNTINGTON;
42 *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
45 case EFX_PCI_DEVID_FARMINGDALE_VF:
46 case EFX_PCI_DEVID_GREENPORT_VF:
47 *efp = EFX_FAMILY_HUNTINGTON;
48 *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
55 * Hardware default for PF0 of uninitialised Medford.
56 * manftest must be able to cope with this device id.
58 case EFX_PCI_DEVID_MEDFORD:
59 *efp = EFX_FAMILY_MEDFORD;
60 *membarp = EFX_MEM_BAR_MEDFORD_PF;
63 case EFX_PCI_DEVID_MEDFORD_VF:
64 *efp = EFX_FAMILY_MEDFORD;
65 *membarp = EFX_MEM_BAR_MEDFORD_VF;
67 #endif /* EFSYS_OPT_MEDFORD */
69 #if EFSYS_OPT_MEDFORD2
70 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
72 * Hardware default for PF0 of uninitialised Medford2.
73 * manftest must be able to cope with this device id.
75 case EFX_PCI_DEVID_MEDFORD2:
76 case EFX_PCI_DEVID_MEDFORD2_VF:
77 *efp = EFX_FAMILY_MEDFORD2;
78 *membarp = EFX_MEM_BAR_MEDFORD2;
80 #endif /* EFSYS_OPT_MEDFORD2 */
82 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
88 *efp = EFX_FAMILY_INVALID;
95 static const efx_nic_ops_t __efx_nic_siena_ops = {
96 siena_nic_probe, /* eno_probe */
97 NULL, /* eno_board_cfg */
98 NULL, /* eno_set_drv_limits */
99 siena_nic_reset, /* eno_reset */
100 siena_nic_init, /* eno_init */
101 NULL, /* eno_get_vi_pool */
102 NULL, /* eno_get_bar_region */
104 siena_nic_register_test, /* eno_register_test */
105 #endif /* EFSYS_OPT_DIAG */
106 siena_nic_fini, /* eno_fini */
107 siena_nic_unprobe, /* eno_unprobe */
110 #endif /* EFSYS_OPT_SIENA */
112 #if EFSYS_OPT_HUNTINGTON
114 static const efx_nic_ops_t __efx_nic_hunt_ops = {
115 ef10_nic_probe, /* eno_probe */
116 hunt_board_cfg, /* eno_board_cfg */
117 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
118 ef10_nic_reset, /* eno_reset */
119 ef10_nic_init, /* eno_init */
120 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
121 ef10_nic_get_bar_region, /* eno_get_bar_region */
123 ef10_nic_register_test, /* eno_register_test */
124 #endif /* EFSYS_OPT_DIAG */
125 ef10_nic_fini, /* eno_fini */
126 ef10_nic_unprobe, /* eno_unprobe */
129 #endif /* EFSYS_OPT_HUNTINGTON */
131 #if EFSYS_OPT_MEDFORD
133 static const efx_nic_ops_t __efx_nic_medford_ops = {
134 ef10_nic_probe, /* eno_probe */
135 medford_board_cfg, /* eno_board_cfg */
136 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
137 ef10_nic_reset, /* eno_reset */
138 ef10_nic_init, /* eno_init */
139 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
140 ef10_nic_get_bar_region, /* eno_get_bar_region */
142 ef10_nic_register_test, /* eno_register_test */
143 #endif /* EFSYS_OPT_DIAG */
144 ef10_nic_fini, /* eno_fini */
145 ef10_nic_unprobe, /* eno_unprobe */
148 #endif /* EFSYS_OPT_MEDFORD */
150 #if EFSYS_OPT_MEDFORD2
152 static const efx_nic_ops_t __efx_nic_medford2_ops = {
153 ef10_nic_probe, /* eno_probe */
154 medford2_board_cfg, /* eno_board_cfg */
155 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
156 ef10_nic_reset, /* eno_reset */
157 ef10_nic_init, /* eno_init */
158 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
159 ef10_nic_get_bar_region, /* eno_get_bar_region */
161 ef10_nic_register_test, /* eno_register_test */
162 #endif /* EFSYS_OPT_DIAG */
163 ef10_nic_fini, /* eno_fini */
164 ef10_nic_unprobe, /* eno_unprobe */
167 #endif /* EFSYS_OPT_MEDFORD2 */
170 __checkReturn efx_rc_t
172 __in efx_family_t family,
173 __in efsys_identifier_t *esip,
174 __in efsys_bar_t *esbp,
175 __in efsys_lock_t *eslp,
176 __deref_out efx_nic_t **enpp)
181 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
182 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
184 /* Allocate a NIC object */
185 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
192 enp->en_magic = EFX_NIC_MAGIC;
196 case EFX_FAMILY_SIENA:
197 enp->en_enop = &__efx_nic_siena_ops;
200 EFX_FEATURE_LFSR_HASH_INSERT |
201 EFX_FEATURE_LINK_EVENTS |
202 EFX_FEATURE_PERIODIC_MAC_STATS |
204 EFX_FEATURE_LOOKAHEAD_SPLIT |
205 EFX_FEATURE_MAC_HEADER_FILTERS |
206 EFX_FEATURE_TX_SRC_FILTERS;
208 #endif /* EFSYS_OPT_SIENA */
210 #if EFSYS_OPT_HUNTINGTON
211 case EFX_FAMILY_HUNTINGTON:
212 enp->en_enop = &__efx_nic_hunt_ops;
215 EFX_FEATURE_LINK_EVENTS |
216 EFX_FEATURE_PERIODIC_MAC_STATS |
218 EFX_FEATURE_MAC_HEADER_FILTERS |
219 EFX_FEATURE_MCDI_DMA |
220 EFX_FEATURE_PIO_BUFFERS |
221 EFX_FEATURE_FW_ASSISTED_TSO |
222 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
223 EFX_FEATURE_PACKED_STREAM;
225 #endif /* EFSYS_OPT_HUNTINGTON */
227 #if EFSYS_OPT_MEDFORD
228 case EFX_FAMILY_MEDFORD:
229 enp->en_enop = &__efx_nic_medford_ops;
231 * FW_ASSISTED_TSO omitted as Medford only supports firmware
232 * assisted TSO version 2, not the v1 scheme used on Huntington.
236 EFX_FEATURE_LINK_EVENTS |
237 EFX_FEATURE_PERIODIC_MAC_STATS |
239 EFX_FEATURE_MAC_HEADER_FILTERS |
240 EFX_FEATURE_MCDI_DMA |
241 EFX_FEATURE_PIO_BUFFERS |
242 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
243 EFX_FEATURE_PACKED_STREAM;
245 #endif /* EFSYS_OPT_MEDFORD */
247 #if EFSYS_OPT_MEDFORD2
248 case EFX_FAMILY_MEDFORD2:
249 enp->en_enop = &__efx_nic_medford2_ops;
252 EFX_FEATURE_LINK_EVENTS |
253 EFX_FEATURE_PERIODIC_MAC_STATS |
255 EFX_FEATURE_MAC_HEADER_FILTERS |
256 EFX_FEATURE_MCDI_DMA |
257 EFX_FEATURE_PIO_BUFFERS |
258 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
259 EFX_FEATURE_PACKED_STREAM;
261 #endif /* EFSYS_OPT_MEDFORD2 */
268 enp->en_family = family;
282 /* Free the NIC object */
283 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
286 EFSYS_PROBE1(fail1, efx_rc_t, rc);
291 __checkReturn efx_rc_t
295 const efx_nic_ops_t *enop;
298 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
300 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
301 #endif /* EFSYS_OPT_MCDI */
302 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
305 if ((rc = enop->eno_probe(enp)) != 0)
308 if ((rc = efx_phy_probe(enp)) != 0)
311 enp->en_mod_flags |= EFX_MOD_PROBE;
318 enop->eno_unprobe(enp);
321 EFSYS_PROBE1(fail1, efx_rc_t, rc);
326 __checkReturn efx_rc_t
327 efx_nic_set_drv_limits(
328 __inout efx_nic_t *enp,
329 __in efx_drv_limits_t *edlp)
331 const efx_nic_ops_t *enop = enp->en_enop;
334 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
335 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
337 if (enop->eno_set_drv_limits != NULL) {
338 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
345 EFSYS_PROBE1(fail1, efx_rc_t, rc);
350 __checkReturn efx_rc_t
351 efx_nic_get_bar_region(
353 __in efx_nic_region_t region,
354 __out uint32_t *offsetp,
357 const efx_nic_ops_t *enop = enp->en_enop;
360 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
361 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
362 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
364 if (enop->eno_get_bar_region == NULL) {
368 if ((rc = (enop->eno_get_bar_region)(enp,
369 region, offsetp, sizep)) != 0) {
379 EFSYS_PROBE1(fail1, efx_rc_t, rc);
385 __checkReturn efx_rc_t
388 __out uint32_t *evq_countp,
389 __out uint32_t *rxq_countp,
390 __out uint32_t *txq_countp)
392 const efx_nic_ops_t *enop = enp->en_enop;
393 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
396 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
397 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
398 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
400 if (enop->eno_get_vi_pool != NULL) {
401 uint32_t vi_count = 0;
403 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
406 *evq_countp = vi_count;
407 *rxq_countp = vi_count;
408 *txq_countp = vi_count;
410 /* Use NIC limits as default value */
411 *evq_countp = encp->enc_evq_limit;
412 *rxq_countp = encp->enc_rxq_limit;
413 *txq_countp = encp->enc_txq_limit;
419 EFSYS_PROBE1(fail1, efx_rc_t, rc);
425 __checkReturn efx_rc_t
429 const efx_nic_ops_t *enop = enp->en_enop;
432 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
433 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
435 if (enp->en_mod_flags & EFX_MOD_NIC) {
440 if ((rc = enop->eno_init(enp)) != 0)
443 enp->en_mod_flags |= EFX_MOD_NIC;
450 EFSYS_PROBE1(fail1, efx_rc_t, rc);
459 const efx_nic_ops_t *enop = enp->en_enop;
461 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
462 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
463 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
464 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
465 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
466 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
467 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
471 enp->en_mod_flags &= ~EFX_MOD_NIC;
478 const efx_nic_ops_t *enop = enp->en_enop;
480 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
482 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
483 #endif /* EFSYS_OPT_MCDI */
484 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
485 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
486 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
487 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
488 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
489 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
491 efx_phy_unprobe(enp);
493 enop->eno_unprobe(enp);
495 enp->en_mod_flags &= ~EFX_MOD_PROBE;
502 efsys_identifier_t *esip = enp->en_esip;
504 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
505 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
507 enp->en_family = EFX_FAMILY_INVALID;
516 /* Free the NIC object */
517 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
520 __checkReturn efx_rc_t
524 const efx_nic_ops_t *enop = enp->en_enop;
525 unsigned int mod_flags;
528 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
529 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
531 * All modules except the MCDI, PROBE, NVRAM, VPD, MON
532 * (which we do not reset here) must have been shut down or never
535 * A rule of thumb here is: If the controller or MC reboots, is *any*
536 * state lost. If it's lost and needs reapplying, then the module
537 * *must* not be initialised during the reset.
539 mod_flags = enp->en_mod_flags;
540 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
541 EFX_MOD_VPD | EFX_MOD_MON);
542 EFSYS_ASSERT3U(mod_flags, ==, 0);
543 if (mod_flags != 0) {
548 if ((rc = enop->eno_reset(enp)) != 0)
556 EFSYS_PROBE1(fail1, efx_rc_t, rc);
561 const efx_nic_cfg_t *
565 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
567 return (&(enp->en_nic_cfg));
570 __checkReturn efx_rc_t
571 efx_nic_get_fw_version(
573 __out efx_nic_fw_info_t *enfip)
575 uint16_t mc_fw_version[4];
583 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
584 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
586 rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
590 rc = efx_mcdi_get_capabilities(enp, NULL,
591 &enfip->enfi_rx_dpcpu_fw_id,
592 &enfip->enfi_tx_dpcpu_fw_id,
595 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
596 } else if (rc == ENOTSUP) {
597 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
598 enfip->enfi_rx_dpcpu_fw_id = 0;
599 enfip->enfi_tx_dpcpu_fw_id = 0;
604 memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
605 sizeof (mc_fw_version));
614 EFSYS_PROBE1(fail1, efx_rc_t, rc);
621 __checkReturn efx_rc_t
622 efx_nic_register_test(
625 const efx_nic_ops_t *enop = enp->en_enop;
628 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
629 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
630 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
632 if ((rc = enop->eno_register_test(enp)) != 0)
638 EFSYS_PROBE1(fail1, efx_rc_t, rc);
643 #endif /* EFSYS_OPT_DIAG */
645 #if EFSYS_OPT_LOOPBACK
649 __in efx_loopback_kind_t loopback_kind,
650 __out efx_qword_t *maskp)
654 EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
655 EFSYS_ASSERT(maskp != NULL);
657 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
658 #define LOOPBACK_CHECK(_mcdi, _efx) \
659 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
661 LOOPBACK_CHECK(NONE, OFF);
662 LOOPBACK_CHECK(DATA, DATA);
663 LOOPBACK_CHECK(GMAC, GMAC);
664 LOOPBACK_CHECK(XGMII, XGMII);
665 LOOPBACK_CHECK(XGXS, XGXS);
666 LOOPBACK_CHECK(XAUI, XAUI);
667 LOOPBACK_CHECK(GMII, GMII);
668 LOOPBACK_CHECK(SGMII, SGMII);
669 LOOPBACK_CHECK(XGBR, XGBR);
670 LOOPBACK_CHECK(XFI, XFI);
671 LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
672 LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
673 LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
674 LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
675 LOOPBACK_CHECK(GPHY, GPHY);
676 LOOPBACK_CHECK(PHYXS, PHY_XS);
677 LOOPBACK_CHECK(PCS, PCS);
678 LOOPBACK_CHECK(PMAPMD, PMA_PMD);
679 LOOPBACK_CHECK(XPORT, XPORT);
680 LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
681 LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
682 LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
683 LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
684 LOOPBACK_CHECK(GMII_WS, GMII_WS);
685 LOOPBACK_CHECK(XFI_WS, XFI_WS);
686 LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
687 LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
688 LOOPBACK_CHECK(PMA_INT, PMA_INT);
689 LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
690 LOOPBACK_CHECK(SD_FAR, SD_FAR);
691 LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
692 LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
693 LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
694 LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
695 LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
696 #undef LOOPBACK_CHECK
698 /* Build bitmask of possible loopback types */
699 EFX_ZERO_QWORD(mask);
701 if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
702 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
703 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
706 if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
707 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
709 * The "MAC" grouping has historically been used by drivers to
710 * mean loopbacks supported by on-chip hardware. Keep that
711 * meaning here, and include on-chip PHY layer loopbacks.
713 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
714 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
715 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
716 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
717 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
718 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
719 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
720 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
721 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
722 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
723 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
724 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
725 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
726 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
727 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
728 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
731 if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
732 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
734 * The "PHY" grouping has historically been used by drivers to
735 * mean loopbacks supported by off-chip hardware. Keep that
738 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
739 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
740 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
741 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
747 __checkReturn efx_rc_t
748 efx_mcdi_get_loopback_modes(
751 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
753 uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
754 MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)];
759 (void) memset(payload, 0, sizeof (payload));
760 req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
761 req.emr_in_buf = payload;
762 req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
763 req.emr_out_buf = payload;
764 req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_LEN;
766 efx_mcdi_execute(enp, &req);
768 if (req.emr_rc != 0) {
773 if (req.emr_out_length_used <
774 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
775 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
781 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
782 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
784 efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
787 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
789 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
790 EFX_AND_QWORD(modes, mask);
791 encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
793 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
794 EFX_AND_QWORD(modes, mask);
795 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
797 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
798 EFX_AND_QWORD(modes, mask);
799 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
801 if (req.emr_out_length_used >=
802 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
803 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
804 /* Response includes 40G loopback modes */
806 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G);
807 EFX_AND_QWORD(modes, mask);
808 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
811 EFX_ZERO_QWORD(modes);
812 EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
813 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
814 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
815 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
816 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
817 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
824 EFSYS_PROBE1(fail1, efx_rc_t, rc);
829 #endif /* EFSYS_OPT_LOOPBACK */
831 __checkReturn efx_rc_t
832 efx_nic_calculate_pcie_link_bandwidth(
833 __in uint32_t pcie_link_width,
834 __in uint32_t pcie_link_gen,
835 __out uint32_t *bandwidth_mbpsp)
837 uint32_t lane_bandwidth;
838 uint32_t total_bandwidth;
841 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
842 !ISP2(pcie_link_width)) {
847 switch (pcie_link_gen) {
848 case EFX_PCIE_LINK_SPEED_GEN1:
849 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
850 lane_bandwidth = 2000;
852 case EFX_PCIE_LINK_SPEED_GEN2:
853 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
854 lane_bandwidth = 4000;
856 case EFX_PCIE_LINK_SPEED_GEN3:
857 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
858 lane_bandwidth = 7877;
865 total_bandwidth = lane_bandwidth * pcie_link_width;
866 *bandwidth_mbpsp = total_bandwidth;
873 EFSYS_PROBE1(fail1, efx_rc_t, rc);
879 __checkReturn efx_rc_t
880 efx_nic_check_pcie_link_speed(
882 __in uint32_t pcie_link_width,
883 __in uint32_t pcie_link_gen,
884 __out efx_pcie_link_performance_t *resultp)
886 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
888 efx_pcie_link_performance_t result;
891 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
892 (pcie_link_width == 0) || (pcie_link_width == 32) ||
893 (pcie_link_gen == 0)) {
895 * No usable info on what is required and/or in use. In virtual
896 * machines, sometimes the PCIe link width is reported as 0 or
897 * 32, or the speed as 0.
899 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
903 /* Calculate the available bandwidth in megabits per second */
904 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
905 pcie_link_gen, &bandwidth);
909 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
910 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
911 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
912 /* The link provides enough bandwidth but not optimal latency */
913 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
915 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
924 EFSYS_PROBE1(fail1, efx_rc_t, rc);