1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
12 static const efx_phy_ops_t __efx_phy_siena_ops = {
13 siena_phy_power, /* epo_power */
15 siena_phy_reconfigure, /* epo_reconfigure */
16 siena_phy_verify, /* epo_verify */
17 siena_phy_oui_get, /* epo_oui_get */
18 #if EFSYS_OPT_PHY_STATS
19 siena_phy_stats_update, /* epo_stats_update */
20 #endif /* EFSYS_OPT_PHY_STATS */
22 NULL, /* epo_bist_enable_offline */
23 siena_phy_bist_start, /* epo_bist_start */
24 siena_phy_bist_poll, /* epo_bist_poll */
25 siena_phy_bist_stop, /* epo_bist_stop */
26 #endif /* EFSYS_OPT_BIST */
28 #endif /* EFSYS_OPT_SIENA */
30 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
31 static const efx_phy_ops_t __efx_phy_ef10_ops = {
32 ef10_phy_power, /* epo_power */
34 ef10_phy_reconfigure, /* epo_reconfigure */
35 ef10_phy_verify, /* epo_verify */
36 ef10_phy_oui_get, /* epo_oui_get */
37 #if EFSYS_OPT_PHY_STATS
38 ef10_phy_stats_update, /* epo_stats_update */
39 #endif /* EFSYS_OPT_PHY_STATS */
41 ef10_bist_enable_offline, /* epo_bist_enable_offline */
42 ef10_bist_start, /* epo_bist_start */
43 ef10_bist_poll, /* epo_bist_poll */
44 ef10_bist_stop, /* epo_bist_stop */
45 #endif /* EFSYS_OPT_BIST */
47 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
49 __checkReturn efx_rc_t
53 efx_port_t *epp = &(enp->en_port);
54 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
55 const efx_phy_ops_t *epop;
58 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
60 epp->ep_port = encp->enc_port;
61 epp->ep_phy_type = encp->enc_phy_type;
63 /* Hook in operations structure */
64 switch (enp->en_family) {
66 case EFX_FAMILY_SIENA:
67 epop = &__efx_phy_siena_ops;
69 #endif /* EFSYS_OPT_SIENA */
70 #if EFSYS_OPT_HUNTINGTON
71 case EFX_FAMILY_HUNTINGTON:
72 epop = &__efx_phy_ef10_ops;
74 #endif /* EFSYS_OPT_HUNTINGTON */
76 case EFX_FAMILY_MEDFORD:
77 epop = &__efx_phy_ef10_ops;
79 #endif /* EFSYS_OPT_MEDFORD */
90 EFSYS_PROBE1(fail1, efx_rc_t, rc);
98 __checkReturn efx_rc_t
102 efx_port_t *epp = &(enp->en_port);
103 const efx_phy_ops_t *epop = epp->ep_epop;
105 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
106 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
108 return (epop->epo_verify(enp));
111 #if EFSYS_OPT_PHY_LED_CONTROL
113 __checkReturn efx_rc_t
116 __in efx_phy_led_mode_t mode)
118 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
119 efx_port_t *epp = &(enp->en_port);
120 const efx_phy_ops_t *epop = epp->ep_epop;
124 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
125 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
127 if (epp->ep_phy_led_mode == mode)
130 mask = (1 << EFX_PHY_LED_DEFAULT);
131 mask |= encp->enc_led_mask;
133 if (!((1 << mode) & mask)) {
138 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
139 epp->ep_phy_led_mode = mode;
141 if ((rc = epop->epo_reconfigure(enp)) != 0)
150 EFSYS_PROBE1(fail1, efx_rc_t, rc);
154 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
160 __out uint32_t *maskp)
162 efx_port_t *epp = &(enp->en_port);
164 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
165 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
168 case EFX_PHY_CAP_CURRENT:
169 *maskp = epp->ep_adv_cap_mask;
171 case EFX_PHY_CAP_DEFAULT:
172 *maskp = epp->ep_default_adv_cap_mask;
174 case EFX_PHY_CAP_PERM:
175 *maskp = epp->ep_phy_cap_mask;
178 EFSYS_ASSERT(B_FALSE);
183 __checkReturn efx_rc_t
188 efx_port_t *epp = &(enp->en_port);
189 const efx_phy_ops_t *epop = epp->ep_epop;
193 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
194 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
196 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
201 if (epp->ep_adv_cap_mask == mask)
204 old_mask = epp->ep_adv_cap_mask;
205 epp->ep_adv_cap_mask = mask;
207 if ((rc = epop->epo_reconfigure(enp)) != 0)
216 epp->ep_adv_cap_mask = old_mask;
217 /* Reconfigure for robustness */
218 if (epop->epo_reconfigure(enp) != 0) {
220 * We may have an inconsistent view of our advertised speed
227 EFSYS_PROBE1(fail1, efx_rc_t, rc);
235 __out uint32_t *maskp)
237 efx_port_t *epp = &(enp->en_port);
239 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
240 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
242 *maskp = epp->ep_lp_cap_mask;
245 __checkReturn efx_rc_t
248 __out uint32_t *ouip)
250 efx_port_t *epp = &(enp->en_port);
251 const efx_phy_ops_t *epop = epp->ep_epop;
253 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
254 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
256 return (epop->epo_oui_get(enp, ouip));
260 efx_phy_media_type_get(
262 __out efx_phy_media_type_t *typep)
264 efx_port_t *epp = &(enp->en_port);
266 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
267 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
269 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
270 *typep = epp->ep_module_type;
272 *typep = epp->ep_fixed_port_type;
275 __checkReturn efx_rc_t
276 efx_phy_module_get_info(
278 __in uint8_t dev_addr,
281 __out_bcount(len) uint8_t *data)
285 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
286 EFSYS_ASSERT(data != NULL);
288 if ((uint32_t)offset + len > 0xff) {
293 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
294 offset, len, data)) != 0)
302 EFSYS_PROBE1(fail1, efx_rc_t, rc);
307 #if EFSYS_OPT_PHY_STATS
311 /* START MKCONFIG GENERATED PhyStatNamesBlock af9ffa24da3bc100 */
312 static const char * const __efx_phy_stat_name[] = {
361 /* END MKCONFIG GENERATED PhyStatNamesBlock */
366 __in efx_phy_stat_t type)
368 _NOTE(ARGUNUSED(enp))
369 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
370 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
372 return (__efx_phy_stat_name[type]);
375 #endif /* EFSYS_OPT_NAMES */
377 __checkReturn efx_rc_t
378 efx_phy_stats_update(
380 __in efsys_mem_t *esmp,
381 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
383 efx_port_t *epp = &(enp->en_port);
384 const efx_phy_ops_t *epop = epp->ep_epop;
386 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
387 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
389 return (epop->epo_stats_update(enp, esmp, stat));
392 #endif /* EFSYS_OPT_PHY_STATS */
397 __checkReturn efx_rc_t
398 efx_bist_enable_offline(
401 efx_port_t *epp = &(enp->en_port);
402 const efx_phy_ops_t *epop = epp->ep_epop;
405 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
407 if (epop->epo_bist_enable_offline == NULL) {
412 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
420 EFSYS_PROBE1(fail1, efx_rc_t, rc);
426 __checkReturn efx_rc_t
429 __in efx_bist_type_t type)
431 efx_port_t *epp = &(enp->en_port);
432 const efx_phy_ops_t *epop = epp->ep_epop;
435 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
437 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
438 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
439 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
441 if (epop->epo_bist_start == NULL) {
446 if ((rc = epop->epo_bist_start(enp, type)) != 0)
449 epp->ep_current_bist = type;
456 EFSYS_PROBE1(fail1, efx_rc_t, rc);
461 __checkReturn efx_rc_t
464 __in efx_bist_type_t type,
465 __out efx_bist_result_t *resultp,
466 __out_opt uint32_t *value_maskp,
467 __out_ecount_opt(count) unsigned long *valuesp,
470 efx_port_t *epp = &(enp->en_port);
471 const efx_phy_ops_t *epop = epp->ep_epop;
474 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
476 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
477 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
478 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
480 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
481 if (epop->epo_bist_poll == NULL) {
486 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
487 valuesp, count)) != 0)
495 EFSYS_PROBE1(fail1, efx_rc_t, rc);
503 __in efx_bist_type_t type)
505 efx_port_t *epp = &(enp->en_port);
506 const efx_phy_ops_t *epop = epp->ep_epop;
508 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
510 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
511 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
512 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
514 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
516 if (epop->epo_bist_stop != NULL)
517 epop->epo_bist_stop(enp, type);
519 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
522 #endif /* EFSYS_OPT_BIST */
527 efx_port_t *epp = &(enp->en_port);
529 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
533 epp->ep_adv_cap_mask = 0;
536 epp->ep_phy_type = 0;