2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
36 static const efx_phy_ops_t __efx_phy_siena_ops = {
37 siena_phy_power, /* epo_power */
39 siena_phy_reconfigure, /* epo_reconfigure */
40 siena_phy_verify, /* epo_verify */
41 siena_phy_oui_get, /* epo_oui_get */
42 #if EFSYS_OPT_PHY_STATS
43 siena_phy_stats_update, /* epo_stats_update */
44 #endif /* EFSYS_OPT_PHY_STATS */
46 NULL, /* epo_bist_enable_offline */
47 siena_phy_bist_start, /* epo_bist_start */
48 siena_phy_bist_poll, /* epo_bist_poll */
49 siena_phy_bist_stop, /* epo_bist_stop */
50 #endif /* EFSYS_OPT_BIST */
52 #endif /* EFSYS_OPT_SIENA */
54 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
55 static const efx_phy_ops_t __efx_phy_ef10_ops = {
56 ef10_phy_power, /* epo_power */
58 ef10_phy_reconfigure, /* epo_reconfigure */
59 ef10_phy_verify, /* epo_verify */
60 ef10_phy_oui_get, /* epo_oui_get */
61 #if EFSYS_OPT_PHY_STATS
62 ef10_phy_stats_update, /* epo_stats_update */
63 #endif /* EFSYS_OPT_PHY_STATS */
65 ef10_bist_enable_offline, /* epo_bist_enable_offline */
66 ef10_bist_start, /* epo_bist_start */
67 ef10_bist_poll, /* epo_bist_poll */
68 ef10_bist_stop, /* epo_bist_stop */
69 #endif /* EFSYS_OPT_BIST */
71 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
73 __checkReturn efx_rc_t
77 efx_port_t *epp = &(enp->en_port);
78 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
79 const efx_phy_ops_t *epop;
82 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
84 epp->ep_port = encp->enc_port;
85 epp->ep_phy_type = encp->enc_phy_type;
87 /* Hook in operations structure */
88 switch (enp->en_family) {
90 case EFX_FAMILY_SIENA:
91 epop = &__efx_phy_siena_ops;
93 #endif /* EFSYS_OPT_SIENA */
94 #if EFSYS_OPT_HUNTINGTON
95 case EFX_FAMILY_HUNTINGTON:
96 epop = &__efx_phy_ef10_ops;
98 #endif /* EFSYS_OPT_HUNTINGTON */
100 case EFX_FAMILY_MEDFORD:
101 epop = &__efx_phy_ef10_ops;
103 #endif /* EFSYS_OPT_MEDFORD */
114 EFSYS_PROBE1(fail1, efx_rc_t, rc);
117 epp->ep_phy_type = 0;
122 __checkReturn efx_rc_t
126 efx_port_t *epp = &(enp->en_port);
127 const efx_phy_ops_t *epop = epp->ep_epop;
129 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
130 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
132 return (epop->epo_verify(enp));
139 __out uint32_t *maskp)
141 efx_port_t *epp = &(enp->en_port);
143 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
144 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
147 case EFX_PHY_CAP_CURRENT:
148 *maskp = epp->ep_adv_cap_mask;
150 case EFX_PHY_CAP_DEFAULT:
151 *maskp = epp->ep_default_adv_cap_mask;
153 case EFX_PHY_CAP_PERM:
154 *maskp = epp->ep_phy_cap_mask;
157 EFSYS_ASSERT(B_FALSE);
162 __checkReturn efx_rc_t
167 efx_port_t *epp = &(enp->en_port);
168 const efx_phy_ops_t *epop = epp->ep_epop;
172 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
173 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
175 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
180 if (epp->ep_adv_cap_mask == mask)
183 old_mask = epp->ep_adv_cap_mask;
184 epp->ep_adv_cap_mask = mask;
186 if ((rc = epop->epo_reconfigure(enp)) != 0)
195 epp->ep_adv_cap_mask = old_mask;
196 /* Reconfigure for robustness */
197 if (epop->epo_reconfigure(enp) != 0) {
199 * We may have an inconsistent view of our advertised speed
206 EFSYS_PROBE1(fail1, efx_rc_t, rc);
214 __out uint32_t *maskp)
216 efx_port_t *epp = &(enp->en_port);
218 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
219 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
221 *maskp = epp->ep_lp_cap_mask;
224 __checkReturn efx_rc_t
227 __out uint32_t *ouip)
229 efx_port_t *epp = &(enp->en_port);
230 const efx_phy_ops_t *epop = epp->ep_epop;
232 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
233 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
235 return (epop->epo_oui_get(enp, ouip));
239 efx_phy_media_type_get(
241 __out efx_phy_media_type_t *typep)
243 efx_port_t *epp = &(enp->en_port);
245 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
246 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
248 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
249 *typep = epp->ep_module_type;
251 *typep = epp->ep_fixed_port_type;
254 __checkReturn efx_rc_t
255 efx_phy_module_get_info(
257 __in uint8_t dev_addr,
260 __out_bcount(len) uint8_t *data)
264 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
265 EFSYS_ASSERT(data != NULL);
267 if ((uint32_t)offset + len > 0xff) {
272 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
273 offset, len, data)) != 0)
281 EFSYS_PROBE1(fail1, efx_rc_t, rc);
286 #if EFSYS_OPT_PHY_STATS
290 /* START MKCONFIG GENERATED PhyStatNamesBlock af9ffa24da3bc100 */
291 static const char * const __efx_phy_stat_name[] = {
340 /* END MKCONFIG GENERATED PhyStatNamesBlock */
345 __in efx_phy_stat_t type)
347 _NOTE(ARGUNUSED(enp))
348 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
349 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
351 return (__efx_phy_stat_name[type]);
354 #endif /* EFSYS_OPT_NAMES */
356 __checkReturn efx_rc_t
357 efx_phy_stats_update(
359 __in efsys_mem_t *esmp,
360 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
362 efx_port_t *epp = &(enp->en_port);
363 const efx_phy_ops_t *epop = epp->ep_epop;
365 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
366 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
368 return (epop->epo_stats_update(enp, esmp, stat));
371 #endif /* EFSYS_OPT_PHY_STATS */
376 __checkReturn efx_rc_t
377 efx_bist_enable_offline(
380 efx_port_t *epp = &(enp->en_port);
381 const efx_phy_ops_t *epop = epp->ep_epop;
384 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
386 if (epop->epo_bist_enable_offline == NULL) {
391 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
399 EFSYS_PROBE1(fail1, efx_rc_t, rc);
405 __checkReturn efx_rc_t
408 __in efx_bist_type_t type)
410 efx_port_t *epp = &(enp->en_port);
411 const efx_phy_ops_t *epop = epp->ep_epop;
414 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
416 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
417 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
418 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
420 if (epop->epo_bist_start == NULL) {
425 if ((rc = epop->epo_bist_start(enp, type)) != 0)
428 epp->ep_current_bist = type;
435 EFSYS_PROBE1(fail1, efx_rc_t, rc);
440 __checkReturn efx_rc_t
443 __in efx_bist_type_t type,
444 __out efx_bist_result_t *resultp,
445 __out_opt uint32_t *value_maskp,
446 __out_ecount_opt(count) unsigned long *valuesp,
449 efx_port_t *epp = &(enp->en_port);
450 const efx_phy_ops_t *epop = epp->ep_epop;
453 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
455 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
456 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
457 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
459 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
460 if (epop->epo_bist_poll == NULL) {
465 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
466 valuesp, count)) != 0)
474 EFSYS_PROBE1(fail1, efx_rc_t, rc);
482 __in efx_bist_type_t type)
484 efx_port_t *epp = &(enp->en_port);
485 const efx_phy_ops_t *epop = epp->ep_epop;
487 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
489 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
490 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
491 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
493 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
495 if (epop->epo_bist_stop != NULL)
496 epop->epo_bist_stop(enp, type);
498 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
501 #endif /* EFSYS_OPT_BIST */
506 efx_port_t *epp = &(enp->en_port);
508 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
512 epp->ep_adv_cap_mask = 0;
515 epp->ep_phy_type = 0;