2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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11 * this list of conditions and the following disclaimer in the documentation
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35 __checkReturn efx_rc_t
39 efx_port_t *epp = &(enp->en_port);
40 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
41 const efx_phy_ops_t *epop;
44 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
46 epp->ep_port = encp->enc_port;
47 epp->ep_phy_type = encp->enc_phy_type;
49 /* Hook in operations structure */
50 switch (enp->en_family) {
61 EFSYS_PROBE1(fail1, efx_rc_t, rc);
69 __checkReturn efx_rc_t
73 efx_port_t *epp = &(enp->en_port);
74 const efx_phy_ops_t *epop = epp->ep_epop;
76 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
77 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
79 return (epop->epo_verify(enp));
86 __out uint32_t *maskp)
88 efx_port_t *epp = &(enp->en_port);
90 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
91 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
94 case EFX_PHY_CAP_CURRENT:
95 *maskp = epp->ep_adv_cap_mask;
97 case EFX_PHY_CAP_DEFAULT:
98 *maskp = epp->ep_default_adv_cap_mask;
100 case EFX_PHY_CAP_PERM:
101 *maskp = epp->ep_phy_cap_mask;
104 EFSYS_ASSERT(B_FALSE);
109 __checkReturn efx_rc_t
114 efx_port_t *epp = &(enp->en_port);
115 const efx_phy_ops_t *epop = epp->ep_epop;
119 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
120 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
122 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
127 if (epp->ep_adv_cap_mask == mask)
130 old_mask = epp->ep_adv_cap_mask;
131 epp->ep_adv_cap_mask = mask;
133 if ((rc = epop->epo_reconfigure(enp)) != 0)
142 epp->ep_adv_cap_mask = old_mask;
143 /* Reconfigure for robustness */
144 if (epop->epo_reconfigure(enp) != 0) {
146 * We may have an inconsistent view of our advertised speed
153 EFSYS_PROBE1(fail1, efx_rc_t, rc);
161 __out uint32_t *maskp)
163 efx_port_t *epp = &(enp->en_port);
165 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
166 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
168 *maskp = epp->ep_lp_cap_mask;
171 __checkReturn efx_rc_t
174 __out uint32_t *ouip)
176 efx_port_t *epp = &(enp->en_port);
177 const efx_phy_ops_t *epop = epp->ep_epop;
179 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
180 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
182 return (epop->epo_oui_get(enp, ouip));
186 efx_phy_media_type_get(
188 __out efx_phy_media_type_t *typep)
190 efx_port_t *epp = &(enp->en_port);
192 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
193 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
195 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
196 *typep = epp->ep_module_type;
198 *typep = epp->ep_fixed_port_type;
201 __checkReturn efx_rc_t
202 efx_phy_module_get_info(
204 __in uint8_t dev_addr,
207 __out_bcount(len) uint8_t *data)
211 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
212 EFSYS_ASSERT(data != NULL);
214 if ((uint32_t)offset + len > 0xff) {
219 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
220 offset, len, data)) != 0)
228 EFSYS_PROBE1(fail1, efx_rc_t, rc);
238 efx_port_t *epp = &(enp->en_port);
240 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
244 epp->ep_adv_cap_mask = 0;
247 epp->ep_phy_type = 0;