1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
12 static const efx_phy_ops_t __efx_phy_siena_ops = {
13 siena_phy_power, /* epo_power */
15 siena_phy_reconfigure, /* epo_reconfigure */
16 siena_phy_verify, /* epo_verify */
17 siena_phy_oui_get, /* epo_oui_get */
18 NULL, /* epo_link_state_get */
19 #if EFSYS_OPT_PHY_STATS
20 siena_phy_stats_update, /* epo_stats_update */
21 #endif /* EFSYS_OPT_PHY_STATS */
23 NULL, /* epo_bist_enable_offline */
24 siena_phy_bist_start, /* epo_bist_start */
25 siena_phy_bist_poll, /* epo_bist_poll */
26 siena_phy_bist_stop, /* epo_bist_stop */
27 #endif /* EFSYS_OPT_BIST */
29 #endif /* EFSYS_OPT_SIENA */
32 static const efx_phy_ops_t __efx_phy_ef10_ops = {
33 ef10_phy_power, /* epo_power */
35 ef10_phy_reconfigure, /* epo_reconfigure */
36 ef10_phy_verify, /* epo_verify */
37 ef10_phy_oui_get, /* epo_oui_get */
38 ef10_phy_link_state_get, /* epo_link_state_get */
39 #if EFSYS_OPT_PHY_STATS
40 ef10_phy_stats_update, /* epo_stats_update */
41 #endif /* EFSYS_OPT_PHY_STATS */
43 ef10_bist_enable_offline, /* epo_bist_enable_offline */
44 ef10_bist_start, /* epo_bist_start */
45 ef10_bist_poll, /* epo_bist_poll */
46 ef10_bist_stop, /* epo_bist_stop */
47 #endif /* EFSYS_OPT_BIST */
49 #endif /* EFX_OPTS_EF10() */
51 __checkReturn efx_rc_t
55 efx_port_t *epp = &(enp->en_port);
56 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
57 const efx_phy_ops_t *epop;
60 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
62 epp->ep_port = encp->enc_port;
63 epp->ep_phy_type = encp->enc_phy_type;
65 /* Hook in operations structure */
66 switch (enp->en_family) {
68 case EFX_FAMILY_SIENA:
69 epop = &__efx_phy_siena_ops;
71 #endif /* EFSYS_OPT_SIENA */
73 #if EFSYS_OPT_HUNTINGTON
74 case EFX_FAMILY_HUNTINGTON:
75 epop = &__efx_phy_ef10_ops;
77 #endif /* EFSYS_OPT_HUNTINGTON */
80 case EFX_FAMILY_MEDFORD:
81 epop = &__efx_phy_ef10_ops;
83 #endif /* EFSYS_OPT_MEDFORD */
85 #if EFSYS_OPT_MEDFORD2
86 case EFX_FAMILY_MEDFORD2:
87 epop = &__efx_phy_ef10_ops;
89 #endif /* EFSYS_OPT_MEDFORD2 */
101 EFSYS_PROBE1(fail1, efx_rc_t, rc);
104 epp->ep_phy_type = 0;
109 __checkReturn efx_rc_t
113 efx_port_t *epp = &(enp->en_port);
114 const efx_phy_ops_t *epop = epp->ep_epop;
116 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
117 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
119 return (epop->epo_verify(enp));
122 #if EFSYS_OPT_PHY_LED_CONTROL
124 __checkReturn efx_rc_t
127 __in efx_phy_led_mode_t mode)
129 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
130 efx_port_t *epp = &(enp->en_port);
131 const efx_phy_ops_t *epop = epp->ep_epop;
135 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
136 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
138 if (epp->ep_phy_led_mode == mode)
141 mask = (1 << EFX_PHY_LED_DEFAULT);
142 mask |= encp->enc_led_mask;
144 if (!((1 << mode) & mask)) {
149 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
150 epp->ep_phy_led_mode = mode;
152 if ((rc = epop->epo_reconfigure(enp)) != 0)
161 EFSYS_PROBE1(fail1, efx_rc_t, rc);
165 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
171 __out uint32_t *maskp)
173 efx_port_t *epp = &(enp->en_port);
175 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
176 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
179 case EFX_PHY_CAP_CURRENT:
180 *maskp = epp->ep_adv_cap_mask;
182 case EFX_PHY_CAP_DEFAULT:
183 *maskp = epp->ep_default_adv_cap_mask;
185 case EFX_PHY_CAP_PERM:
186 *maskp = epp->ep_phy_cap_mask;
189 EFSYS_ASSERT(B_FALSE);
195 __checkReturn efx_rc_t
200 efx_port_t *epp = &(enp->en_port);
201 const efx_phy_ops_t *epop = epp->ep_epop;
205 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
206 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
208 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
213 if (epp->ep_adv_cap_mask == mask)
216 old_mask = epp->ep_adv_cap_mask;
217 epp->ep_adv_cap_mask = mask;
219 if ((rc = epop->epo_reconfigure(enp)) != 0)
228 epp->ep_adv_cap_mask = old_mask;
229 /* Reconfigure for robustness */
230 if (epop->epo_reconfigure(enp) != 0) {
232 * We may have an inconsistent view of our advertised speed
239 EFSYS_PROBE1(fail1, efx_rc_t, rc);
247 __out uint32_t *maskp)
249 efx_port_t *epp = &(enp->en_port);
251 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
252 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
254 *maskp = epp->ep_lp_cap_mask;
257 __checkReturn efx_rc_t
260 __out uint32_t *ouip)
262 efx_port_t *epp = &(enp->en_port);
263 const efx_phy_ops_t *epop = epp->ep_epop;
265 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
266 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
268 return (epop->epo_oui_get(enp, ouip));
272 efx_phy_media_type_get(
274 __out efx_phy_media_type_t *typep)
276 efx_port_t *epp = &(enp->en_port);
278 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
279 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
281 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
282 *typep = epp->ep_module_type;
284 *typep = epp->ep_fixed_port_type;
287 __checkReturn efx_rc_t
288 efx_phy_module_get_info(
290 __in uint8_t dev_addr,
293 __out_bcount(len) uint8_t *data)
297 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
298 EFSYS_ASSERT(data != NULL);
300 if ((offset > EFX_PHY_MEDIA_INFO_MAX_OFFSET) ||
301 ((offset + len) > EFX_PHY_MEDIA_INFO_MAX_OFFSET)) {
306 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
307 offset, len, data)) != 0)
315 EFSYS_PROBE1(fail1, efx_rc_t, rc);
320 __checkReturn efx_rc_t
321 efx_phy_fec_type_get(
323 __out efx_phy_fec_type_t *typep)
326 efx_phy_link_state_t epls;
328 if ((rc = efx_phy_link_state_get(enp, &epls)) != 0)
331 *typep = epls.epls_fec;
336 EFSYS_PROBE1(fail1, efx_rc_t, rc);
341 __checkReturn efx_rc_t
342 efx_phy_link_state_get(
344 __out efx_phy_link_state_t *eplsp)
346 efx_port_t *epp = &(enp->en_port);
347 const efx_phy_ops_t *epop = epp->ep_epop;
350 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
351 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
353 if (epop->epo_link_state_get == NULL) {
358 if ((rc = epop->epo_link_state_get(enp, eplsp)) != 0)
366 EFSYS_PROBE1(fail1, efx_rc_t, rc);
371 #if EFSYS_OPT_PHY_STATS
375 /* START MKCONFIG GENERATED PhyStatNamesBlock af9ffa24da3bc100 */
376 static const char * const __efx_phy_stat_name[] = {
425 /* END MKCONFIG GENERATED PhyStatNamesBlock */
430 __in efx_phy_stat_t type)
432 _NOTE(ARGUNUSED(enp))
433 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
434 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
436 return (__efx_phy_stat_name[type]);
439 #endif /* EFSYS_OPT_NAMES */
441 __checkReturn efx_rc_t
442 efx_phy_stats_update(
444 __in efsys_mem_t *esmp,
445 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
447 efx_port_t *epp = &(enp->en_port);
448 const efx_phy_ops_t *epop = epp->ep_epop;
450 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
451 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
453 return (epop->epo_stats_update(enp, esmp, stat));
456 #endif /* EFSYS_OPT_PHY_STATS */
461 __checkReturn efx_rc_t
462 efx_bist_enable_offline(
465 efx_port_t *epp = &(enp->en_port);
466 const efx_phy_ops_t *epop = epp->ep_epop;
469 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
471 if (epop->epo_bist_enable_offline == NULL) {
476 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
484 EFSYS_PROBE1(fail1, efx_rc_t, rc);
490 __checkReturn efx_rc_t
493 __in efx_bist_type_t type)
495 efx_port_t *epp = &(enp->en_port);
496 const efx_phy_ops_t *epop = epp->ep_epop;
499 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
501 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
502 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
503 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
505 if (epop->epo_bist_start == NULL) {
510 if ((rc = epop->epo_bist_start(enp, type)) != 0)
513 epp->ep_current_bist = type;
520 EFSYS_PROBE1(fail1, efx_rc_t, rc);
525 __checkReturn efx_rc_t
528 __in efx_bist_type_t type,
529 __out efx_bist_result_t *resultp,
530 __out_opt uint32_t *value_maskp,
531 __out_ecount_opt(count) unsigned long *valuesp,
534 efx_port_t *epp = &(enp->en_port);
535 const efx_phy_ops_t *epop = epp->ep_epop;
538 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
540 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
541 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
542 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
544 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
545 if (epop->epo_bist_poll == NULL) {
550 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
551 valuesp, count)) != 0)
559 EFSYS_PROBE1(fail1, efx_rc_t, rc);
567 __in efx_bist_type_t type)
569 efx_port_t *epp = &(enp->en_port);
570 const efx_phy_ops_t *epop = epp->ep_epop;
572 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
574 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
575 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
576 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
578 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
580 if (epop->epo_bist_stop != NULL)
581 epop->epo_bist_stop(enp, type);
583 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
586 #endif /* EFSYS_OPT_BIST */
591 efx_port_t *epp = &(enp->en_port);
593 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
597 epp->ep_adv_cap_mask = 0;
600 epp->ep_phy_type = 0;