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36 static const efx_phy_ops_t __efx_phy_siena_ops = {
37 siena_phy_power, /* epo_power */
39 siena_phy_reconfigure, /* epo_reconfigure */
40 siena_phy_verify, /* epo_verify */
41 siena_phy_oui_get, /* epo_oui_get */
43 #endif /* EFSYS_OPT_SIENA */
45 __checkReturn efx_rc_t
49 efx_port_t *epp = &(enp->en_port);
50 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
51 const efx_phy_ops_t *epop;
54 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
56 epp->ep_port = encp->enc_port;
57 epp->ep_phy_type = encp->enc_phy_type;
59 /* Hook in operations structure */
60 switch (enp->en_family) {
62 case EFX_FAMILY_SIENA:
63 epop = &__efx_phy_siena_ops;
65 #endif /* EFSYS_OPT_SIENA */
76 EFSYS_PROBE1(fail1, efx_rc_t, rc);
84 __checkReturn efx_rc_t
88 efx_port_t *epp = &(enp->en_port);
89 const efx_phy_ops_t *epop = epp->ep_epop;
91 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
92 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
94 return (epop->epo_verify(enp));
101 __out uint32_t *maskp)
103 efx_port_t *epp = &(enp->en_port);
105 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
106 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
109 case EFX_PHY_CAP_CURRENT:
110 *maskp = epp->ep_adv_cap_mask;
112 case EFX_PHY_CAP_DEFAULT:
113 *maskp = epp->ep_default_adv_cap_mask;
115 case EFX_PHY_CAP_PERM:
116 *maskp = epp->ep_phy_cap_mask;
119 EFSYS_ASSERT(B_FALSE);
124 __checkReturn efx_rc_t
129 efx_port_t *epp = &(enp->en_port);
130 const efx_phy_ops_t *epop = epp->ep_epop;
134 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
135 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
137 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
142 if (epp->ep_adv_cap_mask == mask)
145 old_mask = epp->ep_adv_cap_mask;
146 epp->ep_adv_cap_mask = mask;
148 if ((rc = epop->epo_reconfigure(enp)) != 0)
157 epp->ep_adv_cap_mask = old_mask;
158 /* Reconfigure for robustness */
159 if (epop->epo_reconfigure(enp) != 0) {
161 * We may have an inconsistent view of our advertised speed
168 EFSYS_PROBE1(fail1, efx_rc_t, rc);
176 __out uint32_t *maskp)
178 efx_port_t *epp = &(enp->en_port);
180 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
181 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
183 *maskp = epp->ep_lp_cap_mask;
186 __checkReturn efx_rc_t
189 __out uint32_t *ouip)
191 efx_port_t *epp = &(enp->en_port);
192 const efx_phy_ops_t *epop = epp->ep_epop;
194 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
195 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
197 return (epop->epo_oui_get(enp, ouip));
201 efx_phy_media_type_get(
203 __out efx_phy_media_type_t *typep)
205 efx_port_t *epp = &(enp->en_port);
207 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
208 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
210 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
211 *typep = epp->ep_module_type;
213 *typep = epp->ep_fixed_port_type;
216 __checkReturn efx_rc_t
217 efx_phy_module_get_info(
219 __in uint8_t dev_addr,
222 __out_bcount(len) uint8_t *data)
226 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
227 EFSYS_ASSERT(data != NULL);
229 if ((uint32_t)offset + len > 0xff) {
234 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
235 offset, len, data)) != 0)
243 EFSYS_PROBE1(fail1, efx_rc_t, rc);
253 efx_port_t *epp = &(enp->en_port);
255 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
259 epp->ep_adv_cap_mask = 0;
262 epp->ep_phy_type = 0;