2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
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11 * this list of conditions and the following disclaimer in the documentation
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36 static const efx_phy_ops_t __efx_phy_siena_ops = {
37 siena_phy_power, /* epo_power */
39 siena_phy_reconfigure, /* epo_reconfigure */
40 siena_phy_verify, /* epo_verify */
41 siena_phy_oui_get, /* epo_oui_get */
42 #if EFSYS_OPT_PHY_STATS
43 siena_phy_stats_update, /* epo_stats_update */
44 #endif /* EFSYS_OPT_PHY_STATS */
46 NULL, /* epo_bist_enable_offline */
47 siena_phy_bist_start, /* epo_bist_start */
48 siena_phy_bist_poll, /* epo_bist_poll */
49 siena_phy_bist_stop, /* epo_bist_stop */
50 #endif /* EFSYS_OPT_BIST */
52 #endif /* EFSYS_OPT_SIENA */
54 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
55 static const efx_phy_ops_t __efx_phy_ef10_ops = {
56 ef10_phy_power, /* epo_power */
58 ef10_phy_reconfigure, /* epo_reconfigure */
59 ef10_phy_verify, /* epo_verify */
60 ef10_phy_oui_get, /* epo_oui_get */
61 #if EFSYS_OPT_PHY_STATS
62 ef10_phy_stats_update, /* epo_stats_update */
63 #endif /* EFSYS_OPT_PHY_STATS */
65 ef10_bist_enable_offline, /* epo_bist_enable_offline */
66 ef10_bist_start, /* epo_bist_start */
67 ef10_bist_poll, /* epo_bist_poll */
68 ef10_bist_stop, /* epo_bist_stop */
69 #endif /* EFSYS_OPT_BIST */
71 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
73 __checkReturn efx_rc_t
77 efx_port_t *epp = &(enp->en_port);
78 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
79 const efx_phy_ops_t *epop;
82 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
84 epp->ep_port = encp->enc_port;
85 epp->ep_phy_type = encp->enc_phy_type;
87 /* Hook in operations structure */
88 switch (enp->en_family) {
90 case EFX_FAMILY_SIENA:
91 epop = &__efx_phy_siena_ops;
93 #endif /* EFSYS_OPT_SIENA */
94 #if EFSYS_OPT_HUNTINGTON
95 case EFX_FAMILY_HUNTINGTON:
96 epop = &__efx_phy_ef10_ops;
98 #endif /* EFSYS_OPT_HUNTINGTON */
100 case EFX_FAMILY_MEDFORD:
101 epop = &__efx_phy_ef10_ops;
103 #endif /* EFSYS_OPT_MEDFORD */
114 EFSYS_PROBE1(fail1, efx_rc_t, rc);
117 epp->ep_phy_type = 0;
122 __checkReturn efx_rc_t
126 efx_port_t *epp = &(enp->en_port);
127 const efx_phy_ops_t *epop = epp->ep_epop;
129 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
130 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
132 return (epop->epo_verify(enp));
135 #if EFSYS_OPT_PHY_LED_CONTROL
137 __checkReturn efx_rc_t
140 __in efx_phy_led_mode_t mode)
142 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
143 efx_port_t *epp = &(enp->en_port);
144 const efx_phy_ops_t *epop = epp->ep_epop;
148 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
149 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
151 if (epp->ep_phy_led_mode == mode)
154 mask = (1 << EFX_PHY_LED_DEFAULT);
155 mask |= encp->enc_led_mask;
157 if (!((1 << mode) & mask)) {
162 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
163 epp->ep_phy_led_mode = mode;
165 if ((rc = epop->epo_reconfigure(enp)) != 0)
174 EFSYS_PROBE1(fail1, efx_rc_t, rc);
178 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
184 __out uint32_t *maskp)
186 efx_port_t *epp = &(enp->en_port);
188 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
189 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
192 case EFX_PHY_CAP_CURRENT:
193 *maskp = epp->ep_adv_cap_mask;
195 case EFX_PHY_CAP_DEFAULT:
196 *maskp = epp->ep_default_adv_cap_mask;
198 case EFX_PHY_CAP_PERM:
199 *maskp = epp->ep_phy_cap_mask;
202 EFSYS_ASSERT(B_FALSE);
207 __checkReturn efx_rc_t
212 efx_port_t *epp = &(enp->en_port);
213 const efx_phy_ops_t *epop = epp->ep_epop;
217 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
218 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
220 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
225 if (epp->ep_adv_cap_mask == mask)
228 old_mask = epp->ep_adv_cap_mask;
229 epp->ep_adv_cap_mask = mask;
231 if ((rc = epop->epo_reconfigure(enp)) != 0)
240 epp->ep_adv_cap_mask = old_mask;
241 /* Reconfigure for robustness */
242 if (epop->epo_reconfigure(enp) != 0) {
244 * We may have an inconsistent view of our advertised speed
251 EFSYS_PROBE1(fail1, efx_rc_t, rc);
259 __out uint32_t *maskp)
261 efx_port_t *epp = &(enp->en_port);
263 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
266 *maskp = epp->ep_lp_cap_mask;
269 __checkReturn efx_rc_t
272 __out uint32_t *ouip)
274 efx_port_t *epp = &(enp->en_port);
275 const efx_phy_ops_t *epop = epp->ep_epop;
277 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
278 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
280 return (epop->epo_oui_get(enp, ouip));
284 efx_phy_media_type_get(
286 __out efx_phy_media_type_t *typep)
288 efx_port_t *epp = &(enp->en_port);
290 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
291 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
293 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
294 *typep = epp->ep_module_type;
296 *typep = epp->ep_fixed_port_type;
299 __checkReturn efx_rc_t
300 efx_phy_module_get_info(
302 __in uint8_t dev_addr,
305 __out_bcount(len) uint8_t *data)
309 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
310 EFSYS_ASSERT(data != NULL);
312 if ((uint32_t)offset + len > 0xff) {
317 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
318 offset, len, data)) != 0)
326 EFSYS_PROBE1(fail1, efx_rc_t, rc);
331 #if EFSYS_OPT_PHY_STATS
335 /* START MKCONFIG GENERATED PhyStatNamesBlock af9ffa24da3bc100 */
336 static const char * const __efx_phy_stat_name[] = {
385 /* END MKCONFIG GENERATED PhyStatNamesBlock */
390 __in efx_phy_stat_t type)
392 _NOTE(ARGUNUSED(enp))
393 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
394 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
396 return (__efx_phy_stat_name[type]);
399 #endif /* EFSYS_OPT_NAMES */
401 __checkReturn efx_rc_t
402 efx_phy_stats_update(
404 __in efsys_mem_t *esmp,
405 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
407 efx_port_t *epp = &(enp->en_port);
408 const efx_phy_ops_t *epop = epp->ep_epop;
410 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
411 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
413 return (epop->epo_stats_update(enp, esmp, stat));
416 #endif /* EFSYS_OPT_PHY_STATS */
421 __checkReturn efx_rc_t
422 efx_bist_enable_offline(
425 efx_port_t *epp = &(enp->en_port);
426 const efx_phy_ops_t *epop = epp->ep_epop;
429 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
431 if (epop->epo_bist_enable_offline == NULL) {
436 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
444 EFSYS_PROBE1(fail1, efx_rc_t, rc);
450 __checkReturn efx_rc_t
453 __in efx_bist_type_t type)
455 efx_port_t *epp = &(enp->en_port);
456 const efx_phy_ops_t *epop = epp->ep_epop;
459 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
461 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
462 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
463 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
465 if (epop->epo_bist_start == NULL) {
470 if ((rc = epop->epo_bist_start(enp, type)) != 0)
473 epp->ep_current_bist = type;
480 EFSYS_PROBE1(fail1, efx_rc_t, rc);
485 __checkReturn efx_rc_t
488 __in efx_bist_type_t type,
489 __out efx_bist_result_t *resultp,
490 __out_opt uint32_t *value_maskp,
491 __out_ecount_opt(count) unsigned long *valuesp,
494 efx_port_t *epp = &(enp->en_port);
495 const efx_phy_ops_t *epop = epp->ep_epop;
498 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
500 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
501 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
502 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
504 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
505 if (epop->epo_bist_poll == NULL) {
510 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
511 valuesp, count)) != 0)
519 EFSYS_PROBE1(fail1, efx_rc_t, rc);
527 __in efx_bist_type_t type)
529 efx_port_t *epp = &(enp->en_port);
530 const efx_phy_ops_t *epop = epp->ep_epop;
532 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
534 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
535 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
536 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
538 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
540 if (epop->epo_bist_stop != NULL)
541 epop->epo_bist_stop(enp, type);
543 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
546 #endif /* EFSYS_OPT_BIST */
551 efx_port_t *epp = &(enp->en_port);
553 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
557 epp->ep_adv_cap_mask = 0;
560 epp->ep_phy_type = 0;