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36 static const efx_phy_ops_t __efx_phy_siena_ops = {
37 siena_phy_power, /* epo_power */
39 siena_phy_reconfigure, /* epo_reconfigure */
40 siena_phy_verify, /* epo_verify */
41 siena_phy_oui_get, /* epo_oui_get */
43 #endif /* EFSYS_OPT_SIENA */
45 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
46 static const efx_phy_ops_t __efx_phy_ef10_ops = {
47 ef10_phy_power, /* epo_power */
49 ef10_phy_reconfigure, /* epo_reconfigure */
50 ef10_phy_verify, /* epo_verify */
51 ef10_phy_oui_get, /* epo_oui_get */
53 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
55 __checkReturn efx_rc_t
59 efx_port_t *epp = &(enp->en_port);
60 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
61 const efx_phy_ops_t *epop;
64 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
66 epp->ep_port = encp->enc_port;
67 epp->ep_phy_type = encp->enc_phy_type;
69 /* Hook in operations structure */
70 switch (enp->en_family) {
72 case EFX_FAMILY_SIENA:
73 epop = &__efx_phy_siena_ops;
75 #endif /* EFSYS_OPT_SIENA */
76 #if EFSYS_OPT_HUNTINGTON
77 case EFX_FAMILY_HUNTINGTON:
78 epop = &__efx_phy_ef10_ops;
80 #endif /* EFSYS_OPT_HUNTINGTON */
82 case EFX_FAMILY_MEDFORD:
83 epop = &__efx_phy_ef10_ops;
85 #endif /* EFSYS_OPT_MEDFORD */
96 EFSYS_PROBE1(fail1, efx_rc_t, rc);
104 __checkReturn efx_rc_t
108 efx_port_t *epp = &(enp->en_port);
109 const efx_phy_ops_t *epop = epp->ep_epop;
111 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
112 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
114 return (epop->epo_verify(enp));
121 __out uint32_t *maskp)
123 efx_port_t *epp = &(enp->en_port);
125 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
126 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
129 case EFX_PHY_CAP_CURRENT:
130 *maskp = epp->ep_adv_cap_mask;
132 case EFX_PHY_CAP_DEFAULT:
133 *maskp = epp->ep_default_adv_cap_mask;
135 case EFX_PHY_CAP_PERM:
136 *maskp = epp->ep_phy_cap_mask;
139 EFSYS_ASSERT(B_FALSE);
144 __checkReturn efx_rc_t
149 efx_port_t *epp = &(enp->en_port);
150 const efx_phy_ops_t *epop = epp->ep_epop;
154 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
155 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
157 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
162 if (epp->ep_adv_cap_mask == mask)
165 old_mask = epp->ep_adv_cap_mask;
166 epp->ep_adv_cap_mask = mask;
168 if ((rc = epop->epo_reconfigure(enp)) != 0)
177 epp->ep_adv_cap_mask = old_mask;
178 /* Reconfigure for robustness */
179 if (epop->epo_reconfigure(enp) != 0) {
181 * We may have an inconsistent view of our advertised speed
188 EFSYS_PROBE1(fail1, efx_rc_t, rc);
196 __out uint32_t *maskp)
198 efx_port_t *epp = &(enp->en_port);
200 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
201 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
203 *maskp = epp->ep_lp_cap_mask;
206 __checkReturn efx_rc_t
209 __out uint32_t *ouip)
211 efx_port_t *epp = &(enp->en_port);
212 const efx_phy_ops_t *epop = epp->ep_epop;
214 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
215 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
217 return (epop->epo_oui_get(enp, ouip));
221 efx_phy_media_type_get(
223 __out efx_phy_media_type_t *typep)
225 efx_port_t *epp = &(enp->en_port);
227 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
228 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
230 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
231 *typep = epp->ep_module_type;
233 *typep = epp->ep_fixed_port_type;
236 __checkReturn efx_rc_t
237 efx_phy_module_get_info(
239 __in uint8_t dev_addr,
242 __out_bcount(len) uint8_t *data)
246 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
247 EFSYS_ASSERT(data != NULL);
249 if ((uint32_t)offset + len > 0xff) {
254 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
255 offset, len, data)) != 0)
263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
273 efx_port_t *epp = &(enp->en_port);
275 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
279 epp->ep_adv_cap_mask = 0;
282 epp->ep_phy_type = 0;