1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2008-2018 Solarflare Communications Inc.
7 /*! \cidoxg_firmware_mc_cmd */
9 #ifndef _SIENA_MC_DRIVER_PCOL_H
10 #define _SIENA_MC_DRIVER_PCOL_H
13 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
14 /* Power-on reset state */
15 #define MC_FW_STATE_POR (1)
16 /* If this is set in MC_RESET_STATE_REG then it should be
17 * possible to jump into IMEM without loading code from flash. */
18 #define MC_FW_WARM_BOOT_OK (2)
19 /* The MC main image has started to boot. */
20 #define MC_FW_STATE_BOOTING (4)
21 /* The Scheduler has started. */
22 #define MC_FW_STATE_SCHED (8)
23 /* If this is set in MC_RESET_STATE_REG then it should be
24 * possible to jump into IMEM without loading code from flash.
25 * Unlike a warm boot, assume DMEM has been reloaded, so that
26 * the MC persistent data must be reinitialised. */
27 #define MC_FW_TEPID_BOOT_OK (16)
28 /* We have entered the main firmware via recovery mode. This
29 * means that MC persistent data must be reinitialised, but that
30 * we shouldn't touch PCIe config. */
31 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
32 /* BIST state has been initialized */
33 #define MC_FW_BIST_INIT_OK (128)
35 /* Siena MC shared memmory offsets */
36 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
37 #define MC_SMEM_P0_DOORBELL_OFST 0x000
38 #define MC_SMEM_P1_DOORBELL_OFST 0x004
39 /* The rest of these are firmware-defined */
40 #define MC_SMEM_P0_PDU_OFST 0x008
41 #define MC_SMEM_P1_PDU_OFST 0x108
42 #define MC_SMEM_PDU_LEN 0x100
43 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
44 #define MC_SMEM_P0_STATUS_OFST 0x7f8
45 #define MC_SMEM_P1_STATUS_OFST 0x7fc
47 /* Values to be written to the per-port status dword in shared
48 * memory on reboot and assert */
49 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
50 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
52 /* Check whether an mcfw version (in host order) belongs to a bootloader */
53 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
55 /* The current version of the MCDI protocol.
57 * Note that the ROM burnt into the card only talks V0, so at the very
58 * least every driver must support version 0 and MCDI_PCOL_VERSION
61 #define MCDI_PCOL_VERSION 2
63 #define MCDI_PCOL_VERSION 1
66 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
70 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
71 * structure, filled in by the client.
73 * 0 7 8 16 20 22 23 24 31
74 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
78 * \------------------------------ Resync (always set)
80 * The client writes it's request into MC shared memory, and rings the
81 * doorbell. Each request is completed by either by the MC writting
82 * back into shared memory, or by writting out an event.
84 * All MCDI commands support completion by shared memory response. Each
85 * request may also contain additional data (accounted for by HEADER.LEN),
86 * and some response's may also contain additional data (again, accounted
89 * Some MCDI commands support completion by event, in which any associated
90 * response data is included in the event.
92 * The protocol requires one response to be delivered for every request, a
93 * request should not be sent unless the response for the previous request
94 * has been received (either by polling shared memory, or by receiving
98 /** Request/Response structure */
99 #define MCDI_HEADER_OFST 0
100 #define MCDI_HEADER_CODE_LBN 0
101 #define MCDI_HEADER_CODE_WIDTH 7
102 #define MCDI_HEADER_RESYNC_LBN 7
103 #define MCDI_HEADER_RESYNC_WIDTH 1
104 #define MCDI_HEADER_DATALEN_LBN 8
105 #define MCDI_HEADER_DATALEN_WIDTH 8
106 #define MCDI_HEADER_SEQ_LBN 16
107 #define MCDI_HEADER_SEQ_WIDTH 4
108 #define MCDI_HEADER_RSVD_LBN 20
109 #define MCDI_HEADER_RSVD_WIDTH 1
110 #define MCDI_HEADER_NOT_EPOCH_LBN 21
111 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1
112 #define MCDI_HEADER_ERROR_LBN 22
113 #define MCDI_HEADER_ERROR_WIDTH 1
114 #define MCDI_HEADER_RESPONSE_LBN 23
115 #define MCDI_HEADER_RESPONSE_WIDTH 1
116 #define MCDI_HEADER_XFLAGS_LBN 24
117 #define MCDI_HEADER_XFLAGS_WIDTH 8
118 /* Request response using event */
119 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
120 /* Request (and signal) early doorbell return */
121 #define MCDI_HEADER_XFLAGS_DBRET 0x02
123 /* Maximum number of payload bytes */
124 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
125 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
128 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
130 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1
134 /* The MC can generate events for two reasons:
135 * - To advance a shared memory request if XFLAGS_EVREQ was set
136 * - As a notification (link state, i2c event), controlled
137 * via MC_CMD_LOG_CTRL
139 * Both events share a common structure:
141 * 0 32 33 36 44 52 60
142 * | Data | Cont | Level | Src | Code | Rsvd |
144 * \ There is another event pending in this notification
146 * If Code==CMDDONE, then the fields are further interpreted as:
148 * - LEVEL==INFO Command succeeded
149 * - LEVEL==ERR Command failed
152 * | Seq | Datalen | Errno | Rsvd |
154 * These fields are taken directly out of the standard MCDI header, i.e.,
155 * LEVEL==ERR, Datalen == 0 => Reboot
157 * Events can be squirted out of the UART (using LOG_CTRL) without a
158 * MCDI header. An event can be distinguished from a MCDI response by
159 * examining the first byte which is 0xc0. This corresponds to the
160 * non-existent MCDI command MC_CMD_DEBUG_LOG.
163 * | command | Resync | = 0xc0
165 * Since the event is written in big-endian byte order, this works
166 * providing bits 56-63 of the event are 0xc0.
169 * | Rsvd | Code | = 0xc0
171 * Which means for convenience the event code is 0xc for all MC
174 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
177 /* Operation not permitted. */
178 #define MC_CMD_ERR_EPERM 1
179 /* Non-existent command target */
180 #define MC_CMD_ERR_ENOENT 2
181 /* assert() has killed the MC */
182 #define MC_CMD_ERR_EINTR 4
184 #define MC_CMD_ERR_EIO 5
186 #define MC_CMD_ERR_EEXIST 6
188 #define MC_CMD_ERR_EAGAIN 11
190 #define MC_CMD_ERR_ENOMEM 12
191 /* Caller does not hold required locks */
192 #define MC_CMD_ERR_EACCES 13
193 /* Resource is currently unavailable (e.g. lock contention) */
194 #define MC_CMD_ERR_EBUSY 16
196 #define MC_CMD_ERR_ENODEV 19
197 /* Invalid argument to target */
198 #define MC_CMD_ERR_EINVAL 22
200 #define MC_CMD_ERR_EPIPE 32
202 #define MC_CMD_ERR_EROFS 30
204 #define MC_CMD_ERR_ERANGE 34
205 /* Non-recursive resource is already acquired */
206 #define MC_CMD_ERR_EDEADLK 35
207 /* Operation not implemented */
208 #define MC_CMD_ERR_ENOSYS 38
209 /* Operation timed out */
210 #define MC_CMD_ERR_ETIME 62
211 /* Link has been severed */
212 #define MC_CMD_ERR_ENOLINK 67
214 #define MC_CMD_ERR_EPROTO 71
215 /* Operation not supported */
216 #define MC_CMD_ERR_ENOTSUP 95
217 /* Address not available */
218 #define MC_CMD_ERR_EADDRNOTAVAIL 99
220 #define MC_CMD_ERR_ENOTCONN 107
221 /* Operation already in progress */
222 #define MC_CMD_ERR_EALREADY 114
224 /* Resource allocation failed. */
225 #define MC_CMD_ERR_ALLOC_FAIL 0x1000
226 /* V-adaptor not found. */
227 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
228 /* EVB port not found. */
229 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
230 /* V-switch not found. */
231 #define MC_CMD_ERR_NO_VSWITCH 0x1003
232 /* Too many VLAN tags. */
233 #define MC_CMD_ERR_VLAN_LIMIT 0x1004
234 /* Bad PCI function number. */
235 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
236 /* Invalid VLAN mode. */
237 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
238 /* Invalid v-switch type. */
239 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
240 /* Invalid v-port type. */
241 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
242 /* MAC address exists. */
243 #define MC_CMD_ERR_MAC_EXIST 0x1009
244 /* Slave core not present */
245 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
246 /* The datapath is disabled. */
247 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
248 /* The requesting client is not a function */
249 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
250 /* The requested operation might require the
251 command to be passed between MCs, and the
252 transport doesn't support that. Should
253 only ever been seen over the UART. */
254 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
255 /* VLAN tag(s) exists */
256 #define MC_CMD_ERR_VLAN_EXIST 0x100e
257 /* No MAC address assigned to an EVB port */
258 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
259 /* Notifies the driver that the request has been relayed
260 * to an admin function for authorization. The driver should
261 * wait for a PROXY_RESPONSE event and then resend its request.
262 * This error code is followed by a 32-bit handle that
263 * helps matching it with the respective PROXY_RESPONSE event. */
264 #define MC_CMD_ERR_PROXY_PENDING 0x1010
265 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
266 /* The request cannot be passed for authorization because
267 * another request from the same function is currently being
268 * authorized. The drvier should try again later. */
269 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
270 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
271 * that has enabled proxying or BLOCK_INDEX points to a function that
272 * doesn't await an authorization. */
273 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
274 /* This code is currently only used internally in FW. Its meaning is that
275 * an operation failed due to lack of SR-IOV privilege.
276 * Normally it is translated to EPERM by send_cmd_err(),
277 * but it may also be used to trigger some special mechanism
278 * for handling such case, e.g. to relay the failed request
279 * to a designated admin function for authorization. */
280 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
281 /* Workaround 26807 could not be turned on/off because some functions
282 * have already installed filters. See the comment at
283 * MC_CMD_WORKAROUND_BUG26807. */
284 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
285 /* The clock whose frequency you've attempted to set set
286 * doesn't exist on this NIC */
287 #define MC_CMD_ERR_NO_CLOCK 0x1015
288 /* Returned by MC_CMD_TESTASSERT if the action that should
289 * have caused an assertion failed to do so. */
290 #define MC_CMD_ERR_UNREACHABLE 0x1016
291 /* This command needs to be processed in the background but there were no
292 * resources to do so. Send it again after a command has completed. */
293 #define MC_CMD_ERR_QUEUE_FULL 0x1017
294 /* The operation could not be completed because the PCIe link has gone
295 * away. This error code is never expected to be returned over the TLP
297 #define MC_CMD_ERR_NO_PCIE 0x1018
298 /* The operation could not be completed because the datapath has gone
299 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
300 * datapath absence may be temporary*/
301 #define MC_CMD_ERR_NO_DATAPATH 0x1019
303 #define MC_CMD_ERR_CODE_OFST 0
305 /* We define 8 "escape" commands to allow
306 for command number space extension */
308 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
309 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
310 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
311 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
312 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
313 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
314 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
315 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
317 /* Vectors in the boot ROM */
318 /* Point to the copycode entry point. */
319 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
320 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
321 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
322 /* Points to the recovery mode entry point. */
323 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
324 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
325 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
327 /* The command set exported by the boot ROM (MCDI v0) */
328 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
329 (1 << MC_CMD_READ32) | \
330 (1 << MC_CMD_WRITE32) | \
331 (1 << MC_CMD_COPYCODE) | \
332 (1 << MC_CMD_GET_VERSION), \
335 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
336 (MC_CMD_SENSOR_ENTRY_OFST + (_x))
338 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \
339 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
340 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \
341 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
343 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \
344 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
345 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \
346 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
348 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \
349 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
350 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \
351 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
353 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
354 * stack ID (which must be in the range 1-255) along with an EVB port ID.
356 #define EVB_STACK_ID(n) (((n) & 0xff) << 16)
361 /* Version 2 adds an optional argument to error returns: the errno value
362 * may be followed by the (0-based) number of the first argument that
363 * could not be processed.
365 #define MC_CMD_ERR_ARG_OFST 4
368 #define MC_CMD_ERR_ENOSPC 28
372 /* MCDI_EVENT structuredef */
373 #define MCDI_EVENT_LEN 8
374 #define MCDI_EVENT_CONT_LBN 32
375 #define MCDI_EVENT_CONT_WIDTH 1
376 #define MCDI_EVENT_LEVEL_LBN 33
377 #define MCDI_EVENT_LEVEL_WIDTH 3
379 #define MCDI_EVENT_LEVEL_INFO 0x0
381 #define MCDI_EVENT_LEVEL_WARN 0x1
383 #define MCDI_EVENT_LEVEL_ERR 0x2
385 #define MCDI_EVENT_LEVEL_FATAL 0x3
386 #define MCDI_EVENT_DATA_OFST 0
387 #define MCDI_EVENT_DATA_LEN 4
388 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
389 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
390 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
391 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
392 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
393 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
394 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
395 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
396 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
397 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
399 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
401 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
403 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
405 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
407 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
409 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
411 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
412 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
413 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
414 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
415 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
416 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
417 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
418 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8
419 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
420 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
421 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
422 #define MCDI_EVENT_FWALERT_DATA_LBN 8
423 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24
424 #define MCDI_EVENT_FWALERT_REASON_LBN 0
425 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8
426 /* enum: SRAM Access. */
427 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
428 #define MCDI_EVENT_FLR_VF_LBN 0
429 #define MCDI_EVENT_FLR_VF_WIDTH 8
430 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
431 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
432 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12
433 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
434 /* enum: Descriptor loader reported failure */
435 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
436 /* enum: Descriptor ring empty and no EOP seen for packet */
437 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2
438 /* enum: Overlength packet */
439 #define MCDI_EVENT_TX_ERR_2BIG 0x3
440 /* enum: Malformed option descriptor */
441 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5
442 /* enum: Option descriptor part way through a packet */
443 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8
444 /* enum: DMA or PIO data access error */
445 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
446 #define MCDI_EVENT_TX_ERR_INFO_LBN 16
447 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
448 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
449 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
450 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
451 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
452 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
453 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
454 /* enum: PLL lost lock */
455 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
456 /* enum: Filter overflow (PDMA) */
457 #define MCDI_EVENT_PTP_ERR_FILTER 0x2
458 /* enum: FIFO overflow (FPGA) */
459 #define MCDI_EVENT_PTP_ERR_FIFO 0x3
460 /* enum: Merge queue overflow */
461 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4
462 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
463 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
464 /* enum: AOE failed to load - no valid image? */
465 #define MCDI_EVENT_AOE_NO_LOAD 0x1
466 /* enum: AOE FC reported an exception */
467 #define MCDI_EVENT_AOE_FC_ASSERT 0x2
468 /* enum: AOE FC watchdogged */
469 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
470 /* enum: AOE FC failed to start */
471 #define MCDI_EVENT_AOE_FC_NO_START 0x4
472 /* enum: Generic AOE fault - likely to have been reported via other means too
473 * but intended for use by aoex driver.
475 #define MCDI_EVENT_AOE_FAULT 0x5
476 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
477 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
478 /* enum: AOE loaded successfully */
479 #define MCDI_EVENT_AOE_LOAD 0x7
480 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
481 #define MCDI_EVENT_AOE_DMA 0x8
482 /* enum: AOE byteblaster connected/disconnected (Connection status in
485 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9
486 /* enum: DDR ECC status update */
487 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
488 /* enum: PTP status update */
489 #define MCDI_EVENT_AOE_PTP_STATUS 0xb
490 /* enum: FPGA header incorrect */
491 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
492 /* enum: FPGA Powered Off due to error in powering up FPGA */
493 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
494 /* enum: AOE FPGA load failed due to MC to MUM communication failure */
495 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
496 /* enum: Notify that invalid flash type detected */
497 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
498 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */
499 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
500 /* enum: Failure to probe one or more FPGA boot flash chips */
501 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
502 /* enum: FPGA boot-flash contains an invalid image header */
503 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
504 /* enum: Failed to program clocks required by the FPGA */
505 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
506 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */
507 #define MCDI_EVENT_AOE_FC_RUNNING 0x14
508 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8
509 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
510 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
511 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
512 /* enum: FC Assert happened, but the register information is not available */
513 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
514 /* enum: The register information for FC Assert is ready for readinng by driver
516 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
517 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
518 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
519 /* enum: Reading from NV failed */
520 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
521 /* enum: Invalid Magic Number if FPGA header */
522 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
523 /* enum: Invalid Silicon type detected in header */
524 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
525 /* enum: Unsupported VRatio */
526 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
527 /* enum: Unsupported DDR Type */
528 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
529 /* enum: DDR Voltage out of supported range */
530 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
531 /* enum: Unsupported DDR speed */
532 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
533 /* enum: Unsupported DDR size */
534 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
535 /* enum: Unsupported DDR rank */
536 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
537 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
538 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
539 /* enum: Primary boot flash */
540 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
541 /* enum: Secondary boot flash */
542 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
543 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
544 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
545 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
546 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
547 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0
548 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
549 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12
550 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
551 #define MCDI_EVENT_RX_ERR_INFO_LBN 16
552 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16
553 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
554 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
555 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
556 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
557 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
558 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
559 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
560 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
561 /* enum: MUM failed to load - no valid image? */
562 #define MCDI_EVENT_MUM_NO_LOAD 0x1
563 /* enum: MUM f/w reported an exception */
564 #define MCDI_EVENT_MUM_ASSERT 0x2
565 /* enum: MUM not kicking watchdog */
566 #define MCDI_EVENT_MUM_WATCHDOG 0x3
567 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8
568 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
569 #define MCDI_EVENT_DBRET_SEQ_LBN 0
570 #define MCDI_EVENT_DBRET_SEQ_WIDTH 8
571 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
572 #define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8
573 /* enum: Corrupted or bad SUC application. */
574 #define MCDI_EVENT_SUC_BAD_APP 0x1
575 /* enum: SUC application reported an assert. */
576 #define MCDI_EVENT_SUC_ASSERT 0x2
577 /* enum: SUC application reported an exception. */
578 #define MCDI_EVENT_SUC_EXCEPTION 0x3
579 /* enum: SUC watchdog timer expired. */
580 #define MCDI_EVENT_SUC_WATCHDOG 0x4
581 #define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8
582 #define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24
583 #define MCDI_EVENT_SUC_ERR_DATA_LBN 8
584 #define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24
585 #define MCDI_EVENT_DATA_LBN 0
586 #define MCDI_EVENT_DATA_WIDTH 32
587 #define MCDI_EVENT_SRC_LBN 36
588 #define MCDI_EVENT_SRC_WIDTH 8
589 #define MCDI_EVENT_EV_CODE_LBN 60
590 #define MCDI_EVENT_EV_CODE_WIDTH 4
591 #define MCDI_EVENT_CODE_LBN 44
592 #define MCDI_EVENT_CODE_WIDTH 8
593 /* enum: Event generated by host software */
594 #define MCDI_EVENT_SW_EVENT 0x0
595 /* enum: Bad assert. */
596 #define MCDI_EVENT_CODE_BADSSERT 0x1
597 /* enum: PM Notice. */
598 #define MCDI_EVENT_CODE_PMNOTICE 0x2
599 /* enum: Command done. */
600 #define MCDI_EVENT_CODE_CMDDONE 0x3
601 /* enum: Link change. */
602 #define MCDI_EVENT_CODE_LINKCHANGE 0x4
603 /* enum: Sensor Event. */
604 #define MCDI_EVENT_CODE_SENSOREVT 0x5
605 /* enum: Schedule error. */
606 #define MCDI_EVENT_CODE_SCHEDERR 0x6
608 #define MCDI_EVENT_CODE_REBOOT 0x7
609 /* enum: Mac stats DMA. */
610 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
611 /* enum: Firmware alert. */
612 #define MCDI_EVENT_CODE_FWALERT 0x9
613 /* enum: Function level reset. */
614 #define MCDI_EVENT_CODE_FLR 0xa
615 /* enum: Transmit error */
616 #define MCDI_EVENT_CODE_TX_ERR 0xb
617 /* enum: Tx flush has completed */
618 #define MCDI_EVENT_CODE_TX_FLUSH 0xc
619 /* enum: PTP packet received timestamp */
620 #define MCDI_EVENT_CODE_PTP_RX 0xd
621 /* enum: PTP NIC failure */
622 #define MCDI_EVENT_CODE_PTP_FAULT 0xe
623 /* enum: PTP PPS event */
624 #define MCDI_EVENT_CODE_PTP_PPS 0xf
625 /* enum: Rx flush has completed */
626 #define MCDI_EVENT_CODE_RX_FLUSH 0x10
627 /* enum: Receive error */
628 #define MCDI_EVENT_CODE_RX_ERR 0x11
629 /* enum: AOE fault */
630 #define MCDI_EVENT_CODE_AOE 0x12
631 /* enum: Network port calibration failed (VCAL). */
632 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13
633 /* enum: HW PPS event */
634 #define MCDI_EVENT_CODE_HW_PPS 0x14
635 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
636 * a different format)
638 #define MCDI_EVENT_CODE_MC_REBOOT 0x15
639 /* enum: the MC has detected a parity error */
640 #define MCDI_EVENT_CODE_PAR_ERR 0x16
641 /* enum: the MC has detected a correctable error */
642 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
643 /* enum: the MC has detected an uncorrectable error */
644 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
645 /* enum: The MC has entered offline BIST mode */
646 #define MCDI_EVENT_CODE_MC_BIST 0x19
647 /* enum: PTP tick event providing current NIC time */
648 #define MCDI_EVENT_CODE_PTP_TIME 0x1a
649 /* enum: MUM fault */
650 #define MCDI_EVENT_CODE_MUM 0x1b
651 /* enum: notify the designated PF of a new authorization request */
652 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
653 /* enum: notify a function that awaits an authorization that its request has
654 * been processed and it may now resend the command
656 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
657 /* enum: MCDI command accepted. New commands can be issued but this command is
660 #define MCDI_EVENT_CODE_DBRET 0x1e
661 /* enum: The MC has detected a fault on the SUC */
662 #define MCDI_EVENT_CODE_SUC 0x1f
663 /* enum: Artificial event generated by host and posted via MC for test
666 #define MCDI_EVENT_CODE_TESTGEN 0xfa
667 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
668 #define MCDI_EVENT_CMDDONE_DATA_LEN 4
669 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
670 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
671 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
672 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
673 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
674 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
675 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
676 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4
677 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
678 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
679 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
680 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
681 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
682 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
683 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
684 #define MCDI_EVENT_TX_ERR_DATA_LEN 4
685 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
686 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
687 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
690 #define MCDI_EVENT_PTP_SECONDS_OFST 0
691 #define MCDI_EVENT_PTP_SECONDS_LEN 4
692 #define MCDI_EVENT_PTP_SECONDS_LBN 0
693 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32
694 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
697 #define MCDI_EVENT_PTP_MAJOR_OFST 0
698 #define MCDI_EVENT_PTP_MAJOR_LEN 4
699 #define MCDI_EVENT_PTP_MAJOR_LBN 0
700 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32
701 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
704 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
705 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
706 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
707 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
708 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
711 #define MCDI_EVENT_PTP_MINOR_OFST 0
712 #define MCDI_EVENT_PTP_MINOR_LEN 4
713 #define MCDI_EVENT_PTP_MINOR_LBN 0
714 #define MCDI_EVENT_PTP_MINOR_WIDTH 32
715 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
717 #define MCDI_EVENT_PTP_UUID_OFST 0
718 #define MCDI_EVENT_PTP_UUID_LEN 4
719 #define MCDI_EVENT_PTP_UUID_LBN 0
720 #define MCDI_EVENT_PTP_UUID_WIDTH 32
721 #define MCDI_EVENT_RX_ERR_DATA_OFST 0
722 #define MCDI_EVENT_RX_ERR_DATA_LEN 4
723 #define MCDI_EVENT_RX_ERR_DATA_LBN 0
724 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32
725 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0
726 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4
727 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0
728 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
729 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
730 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
731 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
732 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
733 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
734 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
735 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
736 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
737 /* For CODE_PTP_TIME events, the major value of the PTP clock */
738 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
739 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
740 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
741 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
742 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
743 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
744 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
745 /* For CODE_PTP_TIME events, most significant bits of the minor value of the
746 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.
748 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36
749 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8
750 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
751 * whether the NIC clock has ever been set
753 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
754 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
755 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
756 * whether the NIC and System clocks are in sync
758 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
759 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
760 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
761 * the minor value of the PTP clock
763 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
764 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
765 /* For CODE_PTP_TIME events, most significant bits of the minor value of the
766 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.
768 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38
769 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6
770 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
771 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
772 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
773 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
774 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
775 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
776 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
777 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
778 /* Zero means that the request has been completed or authorized, and the driver
779 * should resend it. A non-zero value means that the authorization has been
780 * denied, and gives the reason. Typically it will be EPERM.
782 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
783 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
784 #define MCDI_EVENT_DBRET_DATA_OFST 0
785 #define MCDI_EVENT_DBRET_DATA_LEN 4
786 #define MCDI_EVENT_DBRET_DATA_LBN 0
787 #define MCDI_EVENT_DBRET_DATA_WIDTH 32
789 /* FCDI_EVENT structuredef */
790 #define FCDI_EVENT_LEN 8
791 #define FCDI_EVENT_CONT_LBN 32
792 #define FCDI_EVENT_CONT_WIDTH 1
793 #define FCDI_EVENT_LEVEL_LBN 33
794 #define FCDI_EVENT_LEVEL_WIDTH 3
796 #define FCDI_EVENT_LEVEL_INFO 0x0
798 #define FCDI_EVENT_LEVEL_WARN 0x1
800 #define FCDI_EVENT_LEVEL_ERR 0x2
802 #define FCDI_EVENT_LEVEL_FATAL 0x3
803 #define FCDI_EVENT_DATA_OFST 0
804 #define FCDI_EVENT_DATA_LEN 4
805 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
806 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
807 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
808 #define FCDI_EVENT_LINK_UP 0x1 /* enum */
809 #define FCDI_EVENT_DATA_LBN 0
810 #define FCDI_EVENT_DATA_WIDTH 32
811 #define FCDI_EVENT_SRC_LBN 36
812 #define FCDI_EVENT_SRC_WIDTH 8
813 #define FCDI_EVENT_EV_CODE_LBN 60
814 #define FCDI_EVENT_EV_CODE_WIDTH 4
815 #define FCDI_EVENT_CODE_LBN 44
816 #define FCDI_EVENT_CODE_WIDTH 8
817 /* enum: The FC was rebooted. */
818 #define FCDI_EVENT_CODE_REBOOT 0x1
819 /* enum: Bad assert. */
820 #define FCDI_EVENT_CODE_ASSERT 0x2
821 /* enum: DDR3 test result. */
822 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
823 /* enum: Link status. */
824 #define FCDI_EVENT_CODE_LINK_STATE 0x4
825 /* enum: A timed read is ready to be serviced. */
826 #define FCDI_EVENT_CODE_TIMED_READ 0x5
827 /* enum: One or more PPS IN events */
828 #define FCDI_EVENT_CODE_PPS_IN 0x6
829 /* enum: Tick event from PTP clock */
830 #define FCDI_EVENT_CODE_PTP_TICK 0x7
831 /* enum: ECC error counters */
832 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
833 /* enum: Current status of PTP */
834 #define FCDI_EVENT_CODE_PTP_STATUS 0x9
835 /* enum: Port id config to map MC-FC port idx */
836 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa
837 /* enum: Boot result or error code */
838 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb
839 #define FCDI_EVENT_REBOOT_SRC_LBN 36
840 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8
841 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
842 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
843 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
844 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
845 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
846 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
847 #define FCDI_EVENT_ASSERT_TYPE_LBN 36
848 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8
849 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
850 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
851 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
852 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
853 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
854 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
855 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0
856 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4
857 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0
858 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
859 #define FCDI_EVENT_PTP_STATE_OFST 0
860 #define FCDI_EVENT_PTP_STATE_LEN 4
861 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
862 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
863 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
864 #define FCDI_EVENT_PTP_STATE_LBN 0
865 #define FCDI_EVENT_PTP_STATE_WIDTH 32
866 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
867 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
868 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
869 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
870 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
871 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
872 /* Index of MC port being referred to */
873 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36
874 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8
875 /* FC Port index that matches the MC port index in SRC */
876 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
877 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
878 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
879 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32
880 #define FCDI_EVENT_BOOT_RESULT_OFST 0
881 #define FCDI_EVENT_BOOT_RESULT_LEN 4
882 /* Enum values, see field(s): */
883 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */
884 #define FCDI_EVENT_BOOT_RESULT_LBN 0
885 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32
887 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
888 * to the MC. Note that this structure | is overlayed over a normal FCDI event
889 * such that bits 32-63 containing | event code, level, source etc remain the
890 * same. In this case the data | field of the header is defined to be the
891 * number of timestamps
893 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16
894 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248
895 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
896 /* Number of timestamps following */
897 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
898 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
899 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
900 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
901 /* Seconds field of a timestamp record */
902 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
903 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
904 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
905 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
906 /* Nanoseconds field of a timestamp record */
907 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
908 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
909 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
910 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
911 /* Timestamp records comprising the event */
912 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
913 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
914 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
915 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
916 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
917 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
918 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
919 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
921 /* MUM_EVENT structuredef */
922 #define MUM_EVENT_LEN 8
923 #define MUM_EVENT_CONT_LBN 32
924 #define MUM_EVENT_CONT_WIDTH 1
925 #define MUM_EVENT_LEVEL_LBN 33
926 #define MUM_EVENT_LEVEL_WIDTH 3
928 #define MUM_EVENT_LEVEL_INFO 0x0
930 #define MUM_EVENT_LEVEL_WARN 0x1
932 #define MUM_EVENT_LEVEL_ERR 0x2
934 #define MUM_EVENT_LEVEL_FATAL 0x3
935 #define MUM_EVENT_DATA_OFST 0
936 #define MUM_EVENT_DATA_LEN 4
937 #define MUM_EVENT_SENSOR_ID_LBN 0
938 #define MUM_EVENT_SENSOR_ID_WIDTH 8
939 /* Enum values, see field(s): */
940 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
941 #define MUM_EVENT_SENSOR_STATE_LBN 8
942 #define MUM_EVENT_SENSOR_STATE_WIDTH 8
943 #define MUM_EVENT_PORT_PHY_READY_LBN 0
944 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1
945 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
946 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
947 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
948 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
949 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
950 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
951 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
952 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
953 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
954 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
955 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
956 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
957 #define MUM_EVENT_DATA_LBN 0
958 #define MUM_EVENT_DATA_WIDTH 32
959 #define MUM_EVENT_SRC_LBN 36
960 #define MUM_EVENT_SRC_WIDTH 8
961 #define MUM_EVENT_EV_CODE_LBN 60
962 #define MUM_EVENT_EV_CODE_WIDTH 4
963 #define MUM_EVENT_CODE_LBN 44
964 #define MUM_EVENT_CODE_WIDTH 8
965 /* enum: The MUM was rebooted. */
966 #define MUM_EVENT_CODE_REBOOT 0x1
967 /* enum: Bad assert. */
968 #define MUM_EVENT_CODE_ASSERT 0x2
969 /* enum: Sensor failure. */
970 #define MUM_EVENT_CODE_SENSOR 0x3
971 /* enum: Link fault has been asserted, or has cleared. */
972 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
973 #define MUM_EVENT_SENSOR_DATA_OFST 0
974 #define MUM_EVENT_SENSOR_DATA_LEN 4
975 #define MUM_EVENT_SENSOR_DATA_LBN 0
976 #define MUM_EVENT_SENSOR_DATA_WIDTH 32
977 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0
978 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4
979 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0
980 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32
981 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
982 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
983 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
984 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32
985 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0
986 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4
987 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0
988 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32
989 #define MUM_EVENT_PORT_PHY_TECH_OFST 0
990 #define MUM_EVENT_PORT_PHY_TECH_LEN 4
991 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
992 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
993 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
994 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
995 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
996 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
997 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
998 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
999 #define MUM_EVENT_PORT_PHY_TECH_LBN 0
1000 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32
1001 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36
1002 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1003 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1004 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1005 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1006 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1007 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1008 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40
1009 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1012 /***********************************/
1014 * Read multiple 32byte words from MC memory. Note - this command really
1015 * belongs to INSECURE category but is required by shmboot. The command handler
1016 * has additional checks to reject insecure calls.
1018 #define MC_CMD_READ32 0x1
1019 #undef MC_CMD_0x1_PRIVILEGE_CTG
1021 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1023 /* MC_CMD_READ32_IN msgrequest */
1024 #define MC_CMD_READ32_IN_LEN 8
1025 #define MC_CMD_READ32_IN_ADDR_OFST 0
1026 #define MC_CMD_READ32_IN_ADDR_LEN 4
1027 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1028 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1030 /* MC_CMD_READ32_OUT msgresponse */
1031 #define MC_CMD_READ32_OUT_LENMIN 4
1032 #define MC_CMD_READ32_OUT_LENMAX 252
1033 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1034 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
1035 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
1036 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
1037 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
1040 /***********************************/
1042 * Write multiple 32byte words to MC memory.
1044 #define MC_CMD_WRITE32 0x2
1045 #undef MC_CMD_0x2_PRIVILEGE_CTG
1047 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1049 /* MC_CMD_WRITE32_IN msgrequest */
1050 #define MC_CMD_WRITE32_IN_LENMIN 8
1051 #define MC_CMD_WRITE32_IN_LENMAX 252
1052 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1053 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
1054 #define MC_CMD_WRITE32_IN_ADDR_LEN 4
1055 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1056 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1057 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
1058 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
1060 /* MC_CMD_WRITE32_OUT msgresponse */
1061 #define MC_CMD_WRITE32_OUT_LEN 0
1064 /***********************************/
1066 * Copy MC code between two locations and jump. Note - this command really
1067 * belongs to INSECURE category but is required by shmboot. The command handler
1068 * has additional checks to reject insecure calls.
1070 #define MC_CMD_COPYCODE 0x3
1071 #undef MC_CMD_0x3_PRIVILEGE_CTG
1073 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1075 /* MC_CMD_COPYCODE_IN msgrequest */
1076 #define MC_CMD_COPYCODE_IN_LEN 16
1079 * The main image should be entered via a copy of a single word from and to a
1080 * magic address, which controls various aspects of the boot. The magic address
1081 * is a bitfield, with each bit as documented below.
1083 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1084 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
1085 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
1086 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1087 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
1088 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
1090 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
1091 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
1092 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see
1095 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
1096 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
1097 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
1098 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
1099 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
1100 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
1101 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
1102 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
1103 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
1104 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
1105 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
1106 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6
1107 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
1108 /* Destination address */
1109 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
1110 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
1111 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
1112 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
1113 /* Address of where to jump after copy. */
1114 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12
1115 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4
1116 /* enum: Control should return to the caller rather than jumping */
1117 #define MC_CMD_COPYCODE_JUMP_NONE 0x1
1119 /* MC_CMD_COPYCODE_OUT msgresponse */
1120 #define MC_CMD_COPYCODE_OUT_LEN 0
1123 /***********************************/
1125 * Select function for function-specific commands.
1127 #define MC_CMD_SET_FUNC 0x4
1128 #undef MC_CMD_0x4_PRIVILEGE_CTG
1130 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1132 /* MC_CMD_SET_FUNC_IN msgrequest */
1133 #define MC_CMD_SET_FUNC_IN_LEN 4
1135 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
1136 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4
1138 /* MC_CMD_SET_FUNC_OUT msgresponse */
1139 #define MC_CMD_SET_FUNC_OUT_LEN 0
1142 /***********************************/
1143 /* MC_CMD_GET_BOOT_STATUS
1144 * Get the instruction address from which the MC booted.
1146 #define MC_CMD_GET_BOOT_STATUS 0x5
1147 #undef MC_CMD_0x5_PRIVILEGE_CTG
1149 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1151 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
1152 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1154 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
1155 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
1157 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1158 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
1159 /* enum: indicates that the MC wasn't flash booted */
1160 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1161 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1162 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1163 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1164 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
1165 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
1166 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
1167 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
1168 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
1171 /***********************************/
1172 /* MC_CMD_GET_ASSERTS
1173 * Get (and optionally clear) the current assertion status. Only
1174 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
1175 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
1177 #define MC_CMD_GET_ASSERTS 0x6
1178 #undef MC_CMD_0x6_PRIVILEGE_CTG
1180 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1182 /* MC_CMD_GET_ASSERTS_IN msgrequest */
1183 #define MC_CMD_GET_ASSERTS_IN_LEN 4
1184 /* Set to clear assertion */
1185 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1186 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
1188 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
1189 #define MC_CMD_GET_ASSERTS_OUT_LEN 140
1190 /* Assertion status flag. */
1191 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1192 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
1193 /* enum: No assertions have failed. */
1194 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1195 /* enum: A system-level assertion has failed. */
1196 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1197 /* enum: A thread-level assertion has failed. */
1198 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1199 /* enum: The system was reset by the watchdog. */
1200 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1201 /* enum: An illegal address trap stopped the system (huntington and later) */
1202 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1203 /* Failing PC value */
1204 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1205 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
1207 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
1208 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1209 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
1210 /* enum: A magic value hinting that the value in this register at the time of
1211 * the failure has likely been lost.
1213 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1214 /* Failing thread address */
1215 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
1216 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
1217 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
1218 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
1221 /***********************************/
1223 * Configure the output stream for log events such as link state changes,
1224 * sensor notifications and MCDI completions
1226 #define MC_CMD_LOG_CTRL 0x7
1227 #undef MC_CMD_0x7_PRIVILEGE_CTG
1229 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1231 /* MC_CMD_LOG_CTRL_IN msgrequest */
1232 #define MC_CMD_LOG_CTRL_IN_LEN 8
1233 /* Log destination */
1234 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
1235 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
1237 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
1238 /* enum: Event queue. */
1239 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
1240 /* Legacy argument. Must be zero. */
1241 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
1242 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
1244 /* MC_CMD_LOG_CTRL_OUT msgresponse */
1245 #define MC_CMD_LOG_CTRL_OUT_LEN 0
1248 /***********************************/
1249 /* MC_CMD_GET_VERSION
1250 * Get version information about the MC firmware.
1252 #define MC_CMD_GET_VERSION 0x8
1253 #undef MC_CMD_0x8_PRIVILEGE_CTG
1255 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1257 /* MC_CMD_GET_VERSION_IN msgrequest */
1258 #define MC_CMD_GET_VERSION_IN_LEN 0
1260 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
1261 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4
1262 /* placeholder, set to 0 */
1263 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
1264 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
1266 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
1267 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
1268 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
1269 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
1270 /* enum: Reserved version number to indicate "any" version. */
1271 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
1272 /* enum: Bootrom version value for Siena. */
1273 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
1274 /* enum: Bootrom version value for Huntington. */
1275 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
1276 /* enum: Bootrom version value for Medford2. */
1277 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
1279 /* MC_CMD_GET_VERSION_OUT msgresponse */
1280 #define MC_CMD_GET_VERSION_OUT_LEN 32
1281 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1282 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1283 /* Enum values, see field(s): */
1284 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1285 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
1286 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
1287 /* 128bit mask of functions supported by the current firmware */
1288 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
1289 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
1290 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
1291 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
1292 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
1293 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
1295 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
1296 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
1297 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1298 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1299 /* Enum values, see field(s): */
1300 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1301 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
1302 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
1303 /* 128bit mask of functions supported by the current firmware */
1304 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
1305 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
1306 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
1307 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
1308 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
1309 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
1311 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
1312 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
1315 /***********************************/
1317 * Perform PTP operation
1319 #define MC_CMD_PTP 0xb
1320 #undef MC_CMD_0xb_PRIVILEGE_CTG
1322 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1324 /* MC_CMD_PTP_IN msgrequest */
1325 #define MC_CMD_PTP_IN_LEN 1
1326 /* PTP operation code */
1327 #define MC_CMD_PTP_IN_OP_OFST 0
1328 #define MC_CMD_PTP_IN_OP_LEN 1
1329 /* enum: Enable PTP packet timestamping operation. */
1330 #define MC_CMD_PTP_OP_ENABLE 0x1
1331 /* enum: Disable PTP packet timestamping operation. */
1332 #define MC_CMD_PTP_OP_DISABLE 0x2
1333 /* enum: Send a PTP packet. This operation is used on Siena and Huntington.
1334 * From Medford onwards it is not supported: on those platforms PTP transmit
1335 * timestamping is done using the fast path.
1337 #define MC_CMD_PTP_OP_TRANSMIT 0x3
1338 /* enum: Read the current NIC time. */
1339 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
1340 /* enum: Get the current PTP status. Note that the clock frequency returned (in
1341 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).
1343 #define MC_CMD_PTP_OP_STATUS 0x5
1344 /* enum: Adjust the PTP NIC's time. */
1345 #define MC_CMD_PTP_OP_ADJUST 0x6
1346 /* enum: Synchronize host and NIC time. */
1347 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
1348 /* enum: Basic manufacturing tests. Siena PTP adapters only. */
1349 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
1350 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */
1351 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
1352 /* enum: Reset some of the PTP related statistics */
1353 #define MC_CMD_PTP_OP_RESET_STATS 0xa
1354 /* enum: Debug operations to MC. */
1355 #define MC_CMD_PTP_OP_DEBUG 0xb
1356 /* enum: Read an FPGA register. Siena PTP adapters only. */
1357 #define MC_CMD_PTP_OP_FPGAREAD 0xc
1358 /* enum: Write an FPGA register. Siena PTP adapters only. */
1359 #define MC_CMD_PTP_OP_FPGAWRITE 0xd
1360 /* enum: Apply an offset to the NIC clock */
1361 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
1362 /* enum: Change the frequency correction applied to the NIC clock */
1363 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
1364 /* enum: Set the MC packet filter VLAN tags for received PTP packets.
1365 * Deprecated for Huntington onwards.
1367 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
1368 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for
1369 * Huntington onwards.
1371 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
1372 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated
1373 * for Huntington onwards.
1375 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
1376 /* enum: Set the clock source. Required for snapper tests on Huntington and
1377 * Medford. Not implemented for Siena or Medford2.
1379 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
1380 /* enum: Reset value of Timer Reg. Not implemented. */
1381 #define MC_CMD_PTP_OP_RST_CLK 0x14
1382 /* enum: Enable the forwarding of PPS events to the host */
1383 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15
1384 /* enum: Get the time format used by this NIC for PTP operations */
1385 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
1386 /* enum: Get the clock attributes. NOTE- extended version of
1387 * MC_CMD_PTP_OP_GET_TIME_FORMAT
1389 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
1390 /* enum: Get corrections that should be applied to the various different
1393 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
1394 /* enum: Subscribe to receive periodic time events indicating the current NIC
1397 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
1398 /* enum: Unsubscribe to stop receiving time events */
1399 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
1400 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
1401 * input on the same NIC. Siena PTP adapters only.
1403 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
1404 /* enum: Set the PTP sync status. Status is used by firmware to report to event
1407 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
1408 /* enum: Above this for future use. */
1409 #define MC_CMD_PTP_OP_MAX 0x1c
1411 /* MC_CMD_PTP_IN_ENABLE msgrequest */
1412 #define MC_CMD_PTP_IN_ENABLE_LEN 16
1413 #define MC_CMD_PTP_IN_CMD_OFST 0
1414 #define MC_CMD_PTP_IN_CMD_LEN 4
1415 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
1416 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
1417 /* Not used. Events are always sent to function relative queue 0. */
1418 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
1419 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
1420 /* PTP timestamping mode. Not used from Huntington onwards. */
1421 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
1422 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
1423 /* enum: PTP, version 1 */
1424 #define MC_CMD_PTP_MODE_V1 0x0
1425 /* enum: PTP, version 1, with VLAN headers - deprecated */
1426 #define MC_CMD_PTP_MODE_V1_VLAN 0x1
1427 /* enum: PTP, version 2 */
1428 #define MC_CMD_PTP_MODE_V2 0x2
1429 /* enum: PTP, version 2, with VLAN headers - deprecated */
1430 #define MC_CMD_PTP_MODE_V2_VLAN 0x3
1431 /* enum: PTP, version 2, with improved UUID filtering */
1432 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
1433 /* enum: FCoE (seconds and microseconds) */
1434 #define MC_CMD_PTP_MODE_FCOE 0x5
1436 /* MC_CMD_PTP_IN_DISABLE msgrequest */
1437 #define MC_CMD_PTP_IN_DISABLE_LEN 8
1438 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1439 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1440 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1441 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1443 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
1444 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
1445 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
1446 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
1447 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1448 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1449 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1450 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1451 /* Transmit packet length */
1452 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
1453 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
1454 /* Transmit packet data */
1455 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
1456 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
1457 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
1458 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
1460 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
1461 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
1462 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1463 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1464 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1465 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1467 /* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */
1468 #define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8
1469 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1470 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1471 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1472 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1474 /* MC_CMD_PTP_IN_STATUS msgrequest */
1475 #define MC_CMD_PTP_IN_STATUS_LEN 8
1476 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1477 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1478 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1479 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1481 /* MC_CMD_PTP_IN_ADJUST msgrequest */
1482 #define MC_CMD_PTP_IN_ADJUST_LEN 24
1483 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1484 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1485 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1486 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1487 /* Frequency adjustment 40 bit fixed point ns */
1488 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
1489 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
1490 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
1491 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
1492 /* enum: Number of fractional bits in frequency adjustment */
1493 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28
1494 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1495 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
1498 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
1499 /* Time adjustment in seconds */
1500 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
1501 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
1502 /* Time adjustment major value */
1503 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
1504 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
1505 /* Time adjustment in nanoseconds */
1506 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
1507 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
1508 /* Time adjustment minor value */
1509 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
1510 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
1512 /* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */
1513 #define MC_CMD_PTP_IN_ADJUST_V2_LEN 28
1514 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1515 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1516 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1517 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1518 /* Frequency adjustment 40 bit fixed point ns */
1519 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
1520 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
1521 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
1522 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
1523 /* enum: Number of fractional bits in frequency adjustment */
1524 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
1525 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1526 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
1529 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
1530 /* Time adjustment in seconds */
1531 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16
1532 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
1533 /* Time adjustment major value */
1534 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16
1535 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
1536 /* Time adjustment in nanoseconds */
1537 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20
1538 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
1539 /* Time adjustment minor value */
1540 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20
1541 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
1542 /* Upper 32bits of major time offset adjustment */
1543 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24
1544 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
1546 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
1547 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
1548 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1549 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1550 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1551 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1552 /* Number of time readings to capture */
1553 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
1554 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
1555 /* Host address in which to write "synchronization started" indication (64
1558 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
1559 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
1560 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
1561 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
1563 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
1564 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
1565 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1566 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1567 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1568 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1570 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
1571 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
1572 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1573 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1574 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1575 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1576 /* Enable or disable packet testing */
1577 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
1578 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
1580 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */
1581 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8
1582 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1583 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1584 /* Reset PTP statistics */
1585 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1586 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1588 /* MC_CMD_PTP_IN_DEBUG msgrequest */
1589 #define MC_CMD_PTP_IN_DEBUG_LEN 12
1590 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1591 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1592 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1593 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1594 /* Debug operations */
1595 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
1596 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
1598 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */
1599 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16
1600 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1601 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1602 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1603 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1604 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
1605 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
1606 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
1607 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
1609 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
1610 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
1611 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
1612 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
1613 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1614 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1615 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1616 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1617 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
1618 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
1619 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
1620 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
1621 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
1622 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
1624 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
1625 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
1626 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1627 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1628 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1629 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1630 /* Time adjustment in seconds */
1631 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
1632 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
1633 /* Time adjustment major value */
1634 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
1635 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
1636 /* Time adjustment in nanoseconds */
1637 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
1638 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
1639 /* Time adjustment minor value */
1640 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
1641 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
1643 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */
1644 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20
1645 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1646 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1647 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1648 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1649 /* Time adjustment in seconds */
1650 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8
1651 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
1652 /* Time adjustment major value */
1653 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8
1654 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
1655 /* Time adjustment in nanoseconds */
1656 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12
1657 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
1658 /* Time adjustment minor value */
1659 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12
1660 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
1661 /* Upper 32bits of major time offset adjustment */
1662 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16
1663 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
1665 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
1666 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
1667 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1668 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1669 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1670 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1671 /* Frequency adjustment 40 bit fixed point ns */
1672 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
1673 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
1674 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
1675 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
1676 /* Enum values, see field(s): */
1677 /* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
1679 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
1680 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
1681 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1682 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1683 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1684 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1685 /* Number of VLAN tags, 0 if not VLAN */
1686 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
1687 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
1688 /* Set of VLAN tags to filter against */
1689 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
1690 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
1691 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
1693 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
1694 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
1695 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1696 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1697 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1698 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1699 /* 1 to enable UUID filtering, 0 to disable */
1700 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
1701 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
1702 /* UUID to filter against */
1703 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
1704 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
1705 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
1706 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
1708 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
1709 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
1710 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1711 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1712 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1713 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1714 /* 1 to enable Domain filtering, 0 to disable */
1715 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
1716 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
1717 /* Domain number to filter against */
1718 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
1719 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
1721 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
1722 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
1723 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1724 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1725 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1726 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1727 /* Set the clock source. */
1728 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
1729 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
1730 /* enum: Internal. */
1731 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
1732 /* enum: External. */
1733 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
1735 /* MC_CMD_PTP_IN_RST_CLK msgrequest */
1736 #define MC_CMD_PTP_IN_RST_CLK_LEN 8
1737 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1738 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1739 /* Reset value of Timer Reg. */
1740 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1741 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1743 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
1744 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
1745 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1746 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1747 /* Enable or disable */
1748 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
1749 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
1751 #define MC_CMD_PTP_ENABLE_PPS 0x0
1753 #define MC_CMD_PTP_DISABLE_PPS 0x1
1754 /* Not used. Events are always sent to function relative queue 0. */
1755 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
1756 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
1758 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
1759 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
1760 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1761 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1762 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1763 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1765 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
1766 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
1767 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1768 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1769 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1770 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1772 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
1773 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
1774 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1775 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1776 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1777 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1779 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
1780 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
1781 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1782 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1783 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1784 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1785 /* Original field containing queue ID. Now extended to include flags. */
1786 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
1787 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
1788 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
1789 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
1790 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
1791 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
1793 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
1794 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
1795 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1796 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1797 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1798 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1799 /* Unsubscribe options */
1800 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
1801 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
1802 /* enum: Unsubscribe a single queue */
1803 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
1804 /* enum: Unsubscribe all queues */
1805 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
1806 /* Event queue ID */
1807 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
1808 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
1810 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
1811 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
1812 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1813 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1814 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1815 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1816 /* 1 to enable PPS test mode, 0 to disable and return result. */
1817 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
1818 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
1820 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
1821 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
1822 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1823 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1824 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1825 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1826 /* NIC - Host System Clock Synchronization status */
1827 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
1828 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
1829 /* enum: Host System clock and NIC clock are not in sync */
1830 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
1831 /* enum: Host System clock and NIC clock are synchronized */
1832 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
1833 /* If synchronized, number of seconds until clocks should be considered to be
1834 * no longer in sync.
1836 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
1837 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
1838 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
1839 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
1840 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
1841 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
1843 /* MC_CMD_PTP_OUT msgresponse */
1844 #define MC_CMD_PTP_OUT_LEN 0
1846 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
1847 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
1848 /* Value of seconds timestamp */
1849 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
1850 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
1851 /* Timestamp major value */
1852 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
1853 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
1854 /* Value of nanoseconds timestamp */
1855 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
1856 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
1857 /* Timestamp minor value */
1858 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
1859 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
1861 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
1862 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
1864 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
1865 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
1867 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
1868 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
1869 /* Value of seconds timestamp */
1870 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
1871 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
1872 /* Timestamp major value */
1873 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
1874 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
1875 /* Value of nanoseconds timestamp */
1876 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
1877 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
1878 /* Timestamp minor value */
1879 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
1880 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
1882 /* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */
1883 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12
1884 /* Value of seconds timestamp */
1885 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
1886 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
1887 /* Timestamp major value */
1888 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
1889 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
1890 /* Value of nanoseconds timestamp */
1891 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
1892 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
1893 /* Timestamp minor value */
1894 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
1895 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
1896 /* Upper 32bits of major timestamp value */
1897 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8
1898 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
1900 /* MC_CMD_PTP_OUT_STATUS msgresponse */
1901 #define MC_CMD_PTP_OUT_STATUS_LEN 64
1902 /* Frequency of NIC's hardware clock */
1903 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
1904 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
1905 /* Number of packets transmitted and timestamped */
1906 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
1907 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
1908 /* Number of packets received and timestamped */
1909 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
1910 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
1911 /* Number of packets timestamped by the FPGA */
1912 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
1913 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
1914 /* Number of packets filter matched */
1915 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
1916 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
1917 /* Number of packets not filter matched */
1918 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
1919 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
1920 /* Number of PPS overflows (noise on input?) */
1921 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
1922 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
1923 /* Number of PPS bad periods */
1924 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
1925 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
1926 /* Minimum period of PPS pulse in nanoseconds */
1927 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
1928 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
1929 /* Maximum period of PPS pulse in nanoseconds */
1930 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
1931 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
1932 /* Last period of PPS pulse in nanoseconds */
1933 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
1934 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
1935 /* Mean period of PPS pulse in nanoseconds */
1936 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
1937 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
1938 /* Minimum offset of PPS pulse in nanoseconds (signed) */
1939 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
1940 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
1941 /* Maximum offset of PPS pulse in nanoseconds (signed) */
1942 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
1943 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
1944 /* Last offset of PPS pulse in nanoseconds (signed) */
1945 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
1946 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
1947 /* Mean offset of PPS pulse in nanoseconds (signed) */
1948 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
1949 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
1951 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
1952 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
1953 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
1954 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
1955 /* A set of host and NIC times */
1956 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
1957 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
1958 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
1959 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
1960 /* Host time immediately before NIC's hardware clock read */
1961 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
1962 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
1963 /* Value of seconds timestamp */
1964 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
1965 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
1966 /* Timestamp major value */
1967 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
1968 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
1969 /* Value of nanoseconds timestamp */
1970 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
1971 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
1972 /* Timestamp minor value */
1973 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
1974 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
1975 /* Host time immediately after NIC's hardware clock read */
1976 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
1977 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
1978 /* Number of nanoseconds waited after reading NIC's hardware clock */
1979 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
1980 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
1982 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
1983 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
1984 /* Results of testing */
1985 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
1986 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
1987 /* enum: Successful test */
1988 #define MC_CMD_PTP_MANF_SUCCESS 0x0
1989 /* enum: FPGA load failed */
1990 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
1991 /* enum: FPGA version invalid */
1992 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
1993 /* enum: FPGA registers incorrect */
1994 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
1995 /* enum: Oscillator possibly not working? */
1996 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4
1997 /* enum: Timestamps not increasing */
1998 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
1999 /* enum: Mismatched packet count */
2000 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
2001 /* enum: Mismatched packet count (Siena filter and FPGA) */
2002 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
2003 /* enum: Not enough packets to perform timestamp check */
2004 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
2005 /* enum: Timestamp trigger GPIO not working */
2006 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
2007 /* enum: Insufficient PPS events to perform checks */
2008 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
2009 /* enum: PPS time event period not sufficiently close to 1s. */
2010 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
2011 /* enum: PPS time event nS reading not sufficiently close to zero. */
2012 #define MC_CMD_PTP_MANF_PPS_NS 0xc
2013 /* enum: PTP peripheral registers incorrect */
2014 #define MC_CMD_PTP_MANF_REGISTERS 0xd
2015 /* enum: Failed to read time from PTP peripheral */
2016 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe
2017 /* Presence of external oscillator */
2018 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
2019 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
2021 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
2022 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
2023 /* Results of testing */
2024 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
2025 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
2026 /* Number of packets received by FPGA */
2027 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
2028 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
2029 /* Number of packets received by Siena filters */
2030 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
2031 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
2033 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
2034 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
2035 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
2036 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2037 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
2038 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
2039 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
2040 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
2042 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
2043 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
2044 /* Time format required/used by for this NIC. Applies to all PTP MCDI
2045 * operations that pass times between the host and firmware. If this operation
2046 * is not supported (older firmware) a format of seconds and nanoseconds should
2047 * be assumed. Note this enum is deprecated. Do not add to it- use the
2048 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.
2050 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
2051 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
2052 /* enum: Times are in seconds and nanoseconds */
2053 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
2054 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2055 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
2056 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2057 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
2059 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
2060 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
2061 /* Time format required/used by for this NIC. Applies to all PTP MCDI
2062 * operations that pass times between the host and firmware. If this operation
2063 * is not supported (older firmware) a format of seconds and nanoseconds should
2066 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
2067 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
2068 /* enum: Times are in seconds and nanoseconds */
2069 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
2070 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2071 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
2072 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2073 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
2074 /* enum: Major register units are seconds, minor units are quarter nanoseconds
2076 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
2077 /* Minimum acceptable value for a corrected synchronization timeset. When
2078 * comparing host and NIC clock times, the MC returns a set of samples that
2079 * contain the host start and end time, the MC time when the host start was
2080 * detected and the time the MC waited between reading the time and detecting
2081 * the host end. The corrected sync window is the difference between the host
2082 * end and start times minus the time that the MC waited for host end.
2084 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
2085 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
2086 /* Various PTP capabilities */
2087 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
2088 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
2089 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
2090 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
2091 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
2092 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
2093 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2
2094 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
2095 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3
2096 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
2097 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
2098 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
2099 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
2100 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
2101 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
2102 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
2104 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
2105 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
2106 /* Uncorrected error on PTP transmit timestamps in NIC clock format */
2107 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
2108 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
2109 /* Uncorrected error on PTP receive timestamps in NIC clock format */
2110 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
2111 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
2112 /* Uncorrected error on PPS output in NIC clock format */
2113 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
2114 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
2115 /* Uncorrected error on PPS input in NIC clock format */
2116 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
2117 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
2119 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */
2120 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24
2121 /* Uncorrected error on PTP transmit timestamps in NIC clock format */
2122 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
2123 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
2124 /* Uncorrected error on PTP receive timestamps in NIC clock format */
2125 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
2126 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
2127 /* Uncorrected error on PPS output in NIC clock format */
2128 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8
2129 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
2130 /* Uncorrected error on PPS input in NIC clock format */
2131 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12
2132 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
2133 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
2134 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16
2135 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
2136 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
2137 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20
2138 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
2140 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
2141 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
2142 /* Results of testing */
2143 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
2144 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
2145 /* Enum values, see field(s): */
2146 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
2148 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
2149 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
2152 /***********************************/
2153 /* MC_CMD_CSR_READ32
2154 * Read 32bit words from the indirect memory map.
2156 #define MC_CMD_CSR_READ32 0xc
2157 #undef MC_CMD_0xc_PRIVILEGE_CTG
2159 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2161 /* MC_CMD_CSR_READ32_IN msgrequest */
2162 #define MC_CMD_CSR_READ32_IN_LEN 12
2164 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
2165 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4
2166 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
2167 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4
2168 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
2169 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
2171 /* MC_CMD_CSR_READ32_OUT msgresponse */
2172 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
2173 #define MC_CMD_CSR_READ32_OUT_LENMAX 252
2174 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2175 /* The last dword is the status, not a value read */
2176 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
2177 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
2178 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
2179 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
2182 /***********************************/
2183 /* MC_CMD_CSR_WRITE32
2184 * Write 32bit dwords to the indirect memory map.
2186 #define MC_CMD_CSR_WRITE32 0xd
2187 #undef MC_CMD_0xd_PRIVILEGE_CTG
2189 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2191 /* MC_CMD_CSR_WRITE32_IN msgrequest */
2192 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12
2193 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252
2194 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
2196 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
2197 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
2198 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
2199 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
2200 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
2201 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
2202 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
2203 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
2205 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
2206 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
2207 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
2208 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
2211 /***********************************/
2213 * These commands are used for HP related features. They are grouped under one
2214 * MCDI command to avoid creating too many MCDI commands.
2216 #define MC_CMD_HP 0x54
2217 #undef MC_CMD_0x54_PRIVILEGE_CTG
2219 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2221 /* MC_CMD_HP_IN msgrequest */
2222 #define MC_CMD_HP_IN_LEN 16
2223 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
2224 * the specified address with the specified interval.When address is NULL,
2225 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
2226 * state / 2: (debug) Show temperature reported by one of the supported
2229 #define MC_CMD_HP_IN_SUBCMD_OFST 0
2230 #define MC_CMD_HP_IN_SUBCMD_LEN 4
2231 /* enum: OCSD (Option Card Sensor Data) sub-command. */
2232 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
2233 /* enum: Last known valid HP sub-command. */
2234 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0
2235 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
2237 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
2238 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
2239 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
2240 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
2241 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
2244 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
2245 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
2247 /* MC_CMD_HP_OUT msgresponse */
2248 #define MC_CMD_HP_OUT_LEN 4
2249 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
2250 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
2251 /* enum: OCSD stopped for this card. */
2252 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
2253 /* enum: OCSD was successfully started with the address provided. */
2254 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2
2255 /* enum: OCSD was already started for this card. */
2256 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
2259 /***********************************/
2261 * Get stack information.
2263 #define MC_CMD_STACKINFO 0xf
2264 #undef MC_CMD_0xf_PRIVILEGE_CTG
2266 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2268 /* MC_CMD_STACKINFO_IN msgrequest */
2269 #define MC_CMD_STACKINFO_IN_LEN 0
2271 /* MC_CMD_STACKINFO_OUT msgresponse */
2272 #define MC_CMD_STACKINFO_OUT_LENMIN 12
2273 #define MC_CMD_STACKINFO_OUT_LENMAX 252
2274 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
2275 /* (thread ptr, stack size, free space) for each thread in system */
2276 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
2277 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
2278 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
2279 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
2282 /***********************************/
2284 * MDIO register read.
2286 #define MC_CMD_MDIO_READ 0x10
2287 #undef MC_CMD_0x10_PRIVILEGE_CTG
2289 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2291 /* MC_CMD_MDIO_READ_IN msgrequest */
2292 #define MC_CMD_MDIO_READ_IN_LEN 16
2293 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
2296 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
2297 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4
2298 /* enum: Internal. */
2299 #define MC_CMD_MDIO_BUS_INTERNAL 0x0
2300 /* enum: External. */
2301 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1
2303 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
2304 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
2305 /* Device Address or clause 22. */
2306 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
2307 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
2308 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2309 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
2311 #define MC_CMD_MDIO_CLAUSE22 0x20
2313 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
2314 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4
2316 /* MC_CMD_MDIO_READ_OUT msgresponse */
2317 #define MC_CMD_MDIO_READ_OUT_LEN 8
2319 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
2320 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
2321 /* Status the MDIO commands return the raw status bits from the MDIO block. A
2322 * "good" transaction should have the DONE bit set and all other bits clear.
2324 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
2325 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
2327 #define MC_CMD_MDIO_STATUS_GOOD 0x8
2330 /***********************************/
2331 /* MC_CMD_MDIO_WRITE
2332 * MDIO register write.
2334 #define MC_CMD_MDIO_WRITE 0x11
2335 #undef MC_CMD_0x11_PRIVILEGE_CTG
2337 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2339 /* MC_CMD_MDIO_WRITE_IN msgrequest */
2340 #define MC_CMD_MDIO_WRITE_IN_LEN 20
2341 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
2344 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
2345 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
2346 /* enum: Internal. */
2347 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
2348 /* enum: External. */
2349 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
2351 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
2352 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
2353 /* Device Address or clause 22. */
2354 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
2355 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
2356 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2357 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
2359 /* MC_CMD_MDIO_CLAUSE22 0x20 */
2361 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
2362 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
2364 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
2365 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
2367 /* MC_CMD_MDIO_WRITE_OUT msgresponse */
2368 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
2369 /* Status; the MDIO commands return the raw status bits from the MDIO block. A
2370 * "good" transaction should have the DONE bit set and all other bits clear.
2372 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
2373 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
2375 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
2378 /***********************************/
2380 * Write DBI register(s).
2382 #define MC_CMD_DBI_WRITE 0x12
2383 #undef MC_CMD_0x12_PRIVILEGE_CTG
2385 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2387 /* MC_CMD_DBI_WRITE_IN msgrequest */
2388 #define MC_CMD_DBI_WRITE_IN_LENMIN 12
2389 #define MC_CMD_DBI_WRITE_IN_LENMAX 252
2390 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
2391 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
2392 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
2394 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
2395 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
2396 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
2397 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
2399 /* MC_CMD_DBI_WRITE_OUT msgresponse */
2400 #define MC_CMD_DBI_WRITE_OUT_LEN 0
2402 /* MC_CMD_DBIWROP_TYPEDEF structuredef */
2403 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12
2404 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
2405 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
2406 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
2407 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
2408 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
2409 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
2410 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
2411 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
2412 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
2413 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
2414 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
2415 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
2416 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
2417 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
2418 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
2419 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
2420 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
2421 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
2424 /***********************************/
2425 /* MC_CMD_PORT_READ32
2426 * Read a 32-bit register from the indirect port register map. The port to
2427 * access is implied by the Shared memory channel used.
2429 #define MC_CMD_PORT_READ32 0x14
2431 /* MC_CMD_PORT_READ32_IN msgrequest */
2432 #define MC_CMD_PORT_READ32_IN_LEN 4
2434 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
2435 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4
2437 /* MC_CMD_PORT_READ32_OUT msgresponse */
2438 #define MC_CMD_PORT_READ32_OUT_LEN 8
2440 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
2441 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
2443 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
2444 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
2447 /***********************************/
2448 /* MC_CMD_PORT_WRITE32
2449 * Write a 32-bit register to the indirect port register map. The port to
2450 * access is implied by the Shared memory channel used.
2452 #define MC_CMD_PORT_WRITE32 0x15
2454 /* MC_CMD_PORT_WRITE32_IN msgrequest */
2455 #define MC_CMD_PORT_WRITE32_IN_LEN 8
2457 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
2458 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
2460 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
2461 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
2463 /* MC_CMD_PORT_WRITE32_OUT msgresponse */
2464 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
2466 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
2467 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
2470 /***********************************/
2471 /* MC_CMD_PORT_READ128
2472 * Read a 128-bit register from the indirect port register map. The port to
2473 * access is implied by the Shared memory channel used.
2475 #define MC_CMD_PORT_READ128 0x16
2477 /* MC_CMD_PORT_READ128_IN msgrequest */
2478 #define MC_CMD_PORT_READ128_IN_LEN 4
2480 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
2481 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4
2483 /* MC_CMD_PORT_READ128_OUT msgresponse */
2484 #define MC_CMD_PORT_READ128_OUT_LEN 20
2486 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
2487 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
2489 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
2490 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
2493 /***********************************/
2494 /* MC_CMD_PORT_WRITE128
2495 * Write a 128-bit register to the indirect port register map. The port to
2496 * access is implied by the Shared memory channel used.
2498 #define MC_CMD_PORT_WRITE128 0x17
2500 /* MC_CMD_PORT_WRITE128_IN msgrequest */
2501 #define MC_CMD_PORT_WRITE128_IN_LEN 20
2503 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
2504 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
2506 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
2507 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
2509 /* MC_CMD_PORT_WRITE128_OUT msgresponse */
2510 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
2512 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
2513 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
2515 /* MC_CMD_CAPABILITIES structuredef */
2516 #define MC_CMD_CAPABILITIES_LEN 4
2517 /* Small buf table. */
2518 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
2519 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
2520 /* Turbo mode (for Maranello). */
2521 #define MC_CMD_CAPABILITIES_TURBO_LBN 1
2522 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1
2523 /* Turbo mode active (for Maranello). */
2524 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
2525 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
2527 #define MC_CMD_CAPABILITIES_PTP_LBN 3
2528 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1
2530 #define MC_CMD_CAPABILITIES_AOE_LBN 4
2531 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1
2532 /* AOE mode active. */
2533 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
2534 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
2535 /* AOE mode active. */
2536 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
2537 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
2538 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7
2539 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25
2542 /***********************************/
2543 /* MC_CMD_GET_BOARD_CFG
2544 * Returns the MC firmware configuration structure.
2546 #define MC_CMD_GET_BOARD_CFG 0x18
2547 #undef MC_CMD_0x18_PRIVILEGE_CTG
2549 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2551 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */
2552 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
2554 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
2555 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
2556 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
2557 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
2558 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
2559 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
2560 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
2561 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
2562 /* See MC_CMD_CAPABILITIES */
2563 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
2564 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
2565 /* See MC_CMD_CAPABILITIES */
2566 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
2567 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
2568 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
2569 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
2570 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
2571 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
2572 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
2573 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
2574 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
2575 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
2576 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
2577 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
2578 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
2579 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
2580 /* This field contains a 16-bit value for each of the types of NVRAM area. The
2581 * values are defined in the firmware/mc/platform/.c file for a specific board
2582 * type, but otherwise have no meaning to the MC; they are used by the driver
2583 * to manage selection of appropriate firmware updates.
2585 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
2586 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
2587 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
2588 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
2591 /***********************************/
2593 * Read DBI register(s) -- extended functionality
2595 #define MC_CMD_DBI_READX 0x19
2596 #undef MC_CMD_0x19_PRIVILEGE_CTG
2598 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2600 /* MC_CMD_DBI_READX_IN msgrequest */
2601 #define MC_CMD_DBI_READX_IN_LENMIN 8
2602 #define MC_CMD_DBI_READX_IN_LENMAX 248
2603 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
2604 /* Each Read op consists of an address (offset 0), VF/CS2) */
2605 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
2606 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
2607 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
2608 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
2609 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
2610 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
2612 /* MC_CMD_DBI_READX_OUT msgresponse */
2613 #define MC_CMD_DBI_READX_OUT_LENMIN 4
2614 #define MC_CMD_DBI_READX_OUT_LENMAX 252
2615 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
2617 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
2618 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
2619 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
2620 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
2622 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */
2623 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8
2624 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
2625 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
2626 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
2627 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
2628 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
2629 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
2630 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
2631 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
2632 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
2633 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
2634 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
2635 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
2636 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
2637 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32
2640 /***********************************/
2641 /* MC_CMD_SET_RAND_SEED
2642 * Set the 16byte seed for the MC pseudo-random generator.
2644 #define MC_CMD_SET_RAND_SEED 0x1a
2645 #undef MC_CMD_0x1a_PRIVILEGE_CTG
2647 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2649 /* MC_CMD_SET_RAND_SEED_IN msgrequest */
2650 #define MC_CMD_SET_RAND_SEED_IN_LEN 16
2652 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
2653 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
2655 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */
2656 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
2659 /***********************************/
2660 /* MC_CMD_LTSSM_HIST
2661 * Retrieve the history of the LTSSM, if the build supports it.
2663 #define MC_CMD_LTSSM_HIST 0x1b
2665 /* MC_CMD_LTSSM_HIST_IN msgrequest */
2666 #define MC_CMD_LTSSM_HIST_IN_LEN 0
2668 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
2669 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
2670 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
2671 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
2672 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
2673 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
2674 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
2675 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
2676 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
2679 /***********************************/
2680 /* MC_CMD_DRV_ATTACH
2681 * Inform MCPU that this port is managed on the host (i.e. driver active). For
2682 * Huntington, also request the preferred datapath firmware to use if possible
2683 * (it may not be possible for this request to be fulfilled; the driver must
2684 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
2685 * features are actually available). The FIRMWARE_ID field is ignored by older
2688 #define MC_CMD_DRV_ATTACH 0x1c
2689 #undef MC_CMD_0x1c_PRIVILEGE_CTG
2691 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2693 /* MC_CMD_DRV_ATTACH_IN msgrequest */
2694 #define MC_CMD_DRV_ATTACH_IN_LEN 12
2695 /* new state to set if UPDATE=1 */
2696 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
2697 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
2698 #define MC_CMD_DRV_ATTACH_LBN 0
2699 #define MC_CMD_DRV_ATTACH_WIDTH 1
2700 #define MC_CMD_DRV_PREBOOT_LBN 1
2701 #define MC_CMD_DRV_PREBOOT_WIDTH 1
2702 /* 1 to set new state, or 0 to just report the existing state */
2703 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
2704 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
2705 /* preferred datapath firmware (for Huntington; ignored for Siena) */
2706 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
2707 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
2708 /* enum: Prefer to use full featured firmware */
2709 #define MC_CMD_FW_FULL_FEATURED 0x0
2710 /* enum: Prefer to use firmware with fewer features but lower latency */
2711 #define MC_CMD_FW_LOW_LATENCY 0x1
2712 /* enum: Prefer to use firmware for SolarCapture packed stream mode */
2713 #define MC_CMD_FW_PACKED_STREAM 0x2
2714 /* enum: Prefer to use firmware with fewer features and simpler TX event
2715 * batching but higher TX packet rate
2717 #define MC_CMD_FW_HIGH_TX_RATE 0x3
2718 /* enum: Reserved value */
2719 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
2720 /* enum: Prefer to use firmware with additional "rules engine" filtering
2723 #define MC_CMD_FW_RULES_ENGINE 0x5
2724 /* enum: Only this option is allowed for non-admin functions */
2725 #define MC_CMD_FW_DONT_CARE 0xffffffff
2727 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
2728 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
2729 /* previous or existing state, see the bitmask at NEW_STATE */
2730 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
2731 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
2733 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
2734 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
2735 /* previous or existing state, see the bitmask at NEW_STATE */
2736 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
2737 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
2738 /* Flags associated with this function */
2739 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
2740 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
2741 /* enum: Labels the lowest-numbered function visible to the OS */
2742 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
2743 /* enum: The function can control the link state of the physical port it is
2746 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
2747 /* enum: The function can perform privileged operations */
2748 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
2749 /* enum: The function does not have an active port associated with it. The port
2750 * refers to the Sorrento external FPGA port.
2752 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
2755 /***********************************/
2757 * Route UART output to circular buffer in shared memory instead.
2759 #define MC_CMD_SHMUART 0x1f
2761 /* MC_CMD_SHMUART_IN msgrequest */
2762 #define MC_CMD_SHMUART_IN_LEN 4
2764 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
2765 #define MC_CMD_SHMUART_IN_FLAG_LEN 4
2767 /* MC_CMD_SHMUART_OUT msgresponse */
2768 #define MC_CMD_SHMUART_OUT_LEN 0
2771 /***********************************/
2772 /* MC_CMD_PORT_RESET
2773 * Generic per-port reset. There is no equivalent for per-board reset. Locks
2774 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
2775 * use MC_CMD_ENTITY_RESET instead.
2777 #define MC_CMD_PORT_RESET 0x20
2778 #undef MC_CMD_0x20_PRIVILEGE_CTG
2780 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2782 /* MC_CMD_PORT_RESET_IN msgrequest */
2783 #define MC_CMD_PORT_RESET_IN_LEN 0
2785 /* MC_CMD_PORT_RESET_OUT msgresponse */
2786 #define MC_CMD_PORT_RESET_OUT_LEN 0
2789 /***********************************/
2790 /* MC_CMD_ENTITY_RESET
2791 * Generic per-resource reset. There is no equivalent for per-board reset.
2792 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
2793 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
2795 #define MC_CMD_ENTITY_RESET 0x20
2796 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
2798 /* MC_CMD_ENTITY_RESET_IN msgrequest */
2799 #define MC_CMD_ENTITY_RESET_IN_LEN 4
2800 /* Optional flags field. Omitting this will perform a "legacy" reset action
2803 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
2804 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
2805 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
2806 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
2808 /* MC_CMD_ENTITY_RESET_OUT msgresponse */
2809 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
2812 /***********************************/
2813 /* MC_CMD_PCIE_CREDITS
2814 * Read instantaneous and minimum flow control thresholds.
2816 #define MC_CMD_PCIE_CREDITS 0x21
2818 /* MC_CMD_PCIE_CREDITS_IN msgrequest */
2819 #define MC_CMD_PCIE_CREDITS_IN_LEN 8
2820 /* poll period. 0 is disabled */
2821 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
2822 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
2823 /* wipe statistics */
2824 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
2825 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
2827 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */
2828 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16
2829 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
2830 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
2831 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
2832 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
2833 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
2834 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
2835 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
2836 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
2837 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
2838 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
2839 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
2840 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
2841 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
2842 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
2843 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
2844 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
2847 /***********************************/
2848 /* MC_CMD_RXD_MONITOR
2849 * Get histogram of RX queue fill level.
2851 #define MC_CMD_RXD_MONITOR 0x22
2853 /* MC_CMD_RXD_MONITOR_IN msgrequest */
2854 #define MC_CMD_RXD_MONITOR_IN_LEN 12
2855 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
2856 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4
2857 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
2858 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
2859 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
2860 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
2862 /* MC_CMD_RXD_MONITOR_OUT msgresponse */
2863 #define MC_CMD_RXD_MONITOR_OUT_LEN 80
2864 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
2865 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
2866 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
2867 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
2868 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
2869 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
2870 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
2871 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
2872 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
2873 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
2874 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
2875 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
2876 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
2877 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
2878 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
2879 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
2880 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
2881 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
2882 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
2883 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
2884 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
2885 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
2886 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
2887 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
2888 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
2889 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
2890 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
2891 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
2892 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
2893 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
2894 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
2895 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
2896 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
2897 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
2898 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
2899 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
2900 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
2901 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
2902 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
2903 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
2906 /***********************************/
2908 * Copy the given ASCII string out onto UART and/or out of the network port.
2910 #define MC_CMD_PUTS 0x23
2911 #undef MC_CMD_0x23_PRIVILEGE_CTG
2913 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2915 /* MC_CMD_PUTS_IN msgrequest */
2916 #define MC_CMD_PUTS_IN_LENMIN 13
2917 #define MC_CMD_PUTS_IN_LENMAX 252
2918 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
2919 #define MC_CMD_PUTS_IN_DEST_OFST 0
2920 #define MC_CMD_PUTS_IN_DEST_LEN 4
2921 #define MC_CMD_PUTS_IN_UART_LBN 0
2922 #define MC_CMD_PUTS_IN_UART_WIDTH 1
2923 #define MC_CMD_PUTS_IN_PORT_LBN 1
2924 #define MC_CMD_PUTS_IN_PORT_WIDTH 1
2925 #define MC_CMD_PUTS_IN_DHOST_OFST 4
2926 #define MC_CMD_PUTS_IN_DHOST_LEN 6
2927 #define MC_CMD_PUTS_IN_STRING_OFST 12
2928 #define MC_CMD_PUTS_IN_STRING_LEN 1
2929 #define MC_CMD_PUTS_IN_STRING_MINNUM 1
2930 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240
2932 /* MC_CMD_PUTS_OUT msgresponse */
2933 #define MC_CMD_PUTS_OUT_LEN 0
2936 /***********************************/
2937 /* MC_CMD_GET_PHY_CFG
2938 * Report PHY configuration. This guarantees to succeed even if the PHY is in a
2939 * 'zombie' state. Locks required: None
2941 #define MC_CMD_GET_PHY_CFG 0x24
2942 #undef MC_CMD_0x24_PRIVILEGE_CTG
2944 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2946 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
2947 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
2949 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
2950 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72
2952 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
2953 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
2954 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
2955 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
2956 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
2957 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
2958 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
2959 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
2960 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
2961 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
2962 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
2963 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
2964 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
2965 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
2966 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
2967 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
2969 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
2970 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
2971 /* Bitmask of supported capabilities */
2972 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
2973 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
2974 #define MC_CMD_PHY_CAP_10HDX_LBN 1
2975 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1
2976 #define MC_CMD_PHY_CAP_10FDX_LBN 2
2977 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1
2978 #define MC_CMD_PHY_CAP_100HDX_LBN 3
2979 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1
2980 #define MC_CMD_PHY_CAP_100FDX_LBN 4
2981 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1
2982 #define MC_CMD_PHY_CAP_1000HDX_LBN 5
2983 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
2984 #define MC_CMD_PHY_CAP_1000FDX_LBN 6
2985 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
2986 #define MC_CMD_PHY_CAP_10000FDX_LBN 7
2987 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
2988 #define MC_CMD_PHY_CAP_PAUSE_LBN 8
2989 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
2990 #define MC_CMD_PHY_CAP_ASYM_LBN 9
2991 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1
2992 #define MC_CMD_PHY_CAP_AN_LBN 10
2993 #define MC_CMD_PHY_CAP_AN_WIDTH 1
2994 #define MC_CMD_PHY_CAP_40000FDX_LBN 11
2995 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
2996 #define MC_CMD_PHY_CAP_DDM_LBN 12
2997 #define MC_CMD_PHY_CAP_DDM_WIDTH 1
2998 #define MC_CMD_PHY_CAP_100000FDX_LBN 13
2999 #define MC_CMD_PHY_CAP_100000FDX_WIDTH 1
3000 #define MC_CMD_PHY_CAP_25000FDX_LBN 14
3001 #define MC_CMD_PHY_CAP_25000FDX_WIDTH 1
3002 #define MC_CMD_PHY_CAP_50000FDX_LBN 15
3003 #define MC_CMD_PHY_CAP_50000FDX_WIDTH 1
3004 #define MC_CMD_PHY_CAP_BASER_FEC_LBN 16
3005 #define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
3006 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17
3007 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
3008 #define MC_CMD_PHY_CAP_RS_FEC_LBN 18
3009 #define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
3010 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19
3011 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
3012 #define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20
3013 #define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
3014 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21
3015 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
3017 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
3018 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
3020 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
3021 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
3023 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
3024 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
3026 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
3027 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
3029 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
3030 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
3032 #define MC_CMD_MEDIA_XAUI 0x1
3034 #define MC_CMD_MEDIA_CX4 0x2
3036 #define MC_CMD_MEDIA_KX4 0x3
3037 /* enum: XFP Far. */
3038 #define MC_CMD_MEDIA_XFP 0x4
3040 #define MC_CMD_MEDIA_SFP_PLUS 0x5
3041 /* enum: 10GBaseT. */
3042 #define MC_CMD_MEDIA_BASE_T 0x6
3044 #define MC_CMD_MEDIA_QSFP_PLUS 0x7
3045 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
3046 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
3047 /* enum: Native clause 22 */
3048 #define MC_CMD_MMD_CLAUSE22 0x0
3049 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
3050 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
3051 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
3052 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
3053 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
3054 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
3055 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
3056 /* enum: Clause22 proxied over clause45 by PHY. */
3057 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
3058 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
3059 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
3060 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
3061 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
3064 /***********************************/
3065 /* MC_CMD_START_BIST
3066 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
3067 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
3069 #define MC_CMD_START_BIST 0x25
3070 #undef MC_CMD_0x25_PRIVILEGE_CTG
3072 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3074 /* MC_CMD_START_BIST_IN msgrequest */
3075 #define MC_CMD_START_BIST_IN_LEN 4
3077 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
3078 #define MC_CMD_START_BIST_IN_TYPE_LEN 4
3079 /* enum: Run the PHY's short cable BIST. */
3080 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
3081 /* enum: Run the PHY's long cable BIST. */
3082 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2
3083 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
3084 #define MC_CMD_BPX_SERDES_BIST 0x3
3085 /* enum: Run the MC loopback tests. */
3086 #define MC_CMD_MC_LOOPBACK_BIST 0x4
3087 /* enum: Run the PHY's standard BIST. */
3088 #define MC_CMD_PHY_BIST 0x5
3089 /* enum: Run MC RAM test. */
3090 #define MC_CMD_MC_MEM_BIST 0x6
3091 /* enum: Run Port RAM test. */
3092 #define MC_CMD_PORT_MEM_BIST 0x7
3093 /* enum: Run register test. */
3094 #define MC_CMD_REG_BIST 0x8
3096 /* MC_CMD_START_BIST_OUT msgresponse */
3097 #define MC_CMD_START_BIST_OUT_LEN 0
3100 /***********************************/
3102 * Poll for BIST completion. Returns a single status code, and optionally some
3103 * PHY specific bist output. The driver should only consume the BIST output
3104 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
3105 * successfully parse the BIST output, it should still respect the pass/Fail in
3106 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
3107 * EACCES (if PHY_LOCK is not held).
3109 #define MC_CMD_POLL_BIST 0x26
3110 #undef MC_CMD_0x26_PRIVILEGE_CTG
3112 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3114 /* MC_CMD_POLL_BIST_IN msgrequest */
3115 #define MC_CMD_POLL_BIST_IN_LEN 0
3117 /* MC_CMD_POLL_BIST_OUT msgresponse */
3118 #define MC_CMD_POLL_BIST_OUT_LEN 8
3120 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
3121 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
3122 /* enum: Running. */
3123 #define MC_CMD_POLL_BIST_RUNNING 0x1
3125 #define MC_CMD_POLL_BIST_PASSED 0x2
3127 #define MC_CMD_POLL_BIST_FAILED 0x3
3128 /* enum: Timed-out. */
3129 #define MC_CMD_POLL_BIST_TIMEOUT 0x4
3130 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
3131 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
3133 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
3134 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
3136 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3137 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3138 /* Enum values, see field(s): */
3139 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3140 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
3141 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
3142 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
3143 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
3144 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
3145 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
3146 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
3147 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
3148 /* Status of each channel A */
3149 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
3150 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
3152 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
3154 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
3155 /* enum: Intra-pair short. */
3156 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
3157 /* enum: Inter-pair short. */
3158 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
3160 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
3161 /* Status of each channel B */
3162 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
3163 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
3164 /* Enum values, see field(s): */
3165 /* CABLE_STATUS_A */
3166 /* Status of each channel C */
3167 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
3168 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
3169 /* Enum values, see field(s): */
3170 /* CABLE_STATUS_A */
3171 /* Status of each channel D */
3172 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
3173 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
3174 /* Enum values, see field(s): */
3175 /* CABLE_STATUS_A */
3177 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
3178 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
3180 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3181 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3182 /* Enum values, see field(s): */
3183 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3184 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
3185 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
3186 /* enum: Complete. */
3187 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
3188 /* enum: Bus switch off I2C write. */
3189 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
3190 /* enum: Bus switch off I2C no access IO exp. */
3191 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
3192 /* enum: Bus switch off I2C no access module. */
3193 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
3194 /* enum: IO exp I2C configure. */
3195 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
3196 /* enum: Bus switch I2C no cross talk. */
3197 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
3198 /* enum: Module presence. */
3199 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
3200 /* enum: Module ID I2C access. */
3201 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
3202 /* enum: Module ID sane value. */
3203 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
3205 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
3206 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36
3208 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3209 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3210 /* Enum values, see field(s): */
3211 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3212 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
3213 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
3214 /* enum: Test has completed. */
3215 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
3216 /* enum: RAM test - walk ones. */
3217 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
3218 /* enum: RAM test - walk zeros. */
3219 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
3220 /* enum: RAM test - walking inversions zeros/ones. */
3221 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
3222 /* enum: RAM test - walking inversions checkerboard. */
3223 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
3224 /* enum: Register test - set / clear individual bits. */
3225 #define MC_CMD_POLL_BIST_MEM_REG 0x5
3226 /* enum: ECC error detected. */
3227 #define MC_CMD_POLL_BIST_MEM_ECC 0x6
3228 /* Failure address, only valid if result is POLL_BIST_FAILED */
3229 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
3230 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
3231 /* Bus or address space to which the failure address corresponds */
3232 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
3233 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
3234 /* enum: MC MIPS bus. */
3235 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
3236 /* enum: CSR IREG bus. */
3237 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
3238 /* enum: RX0 DPCPU bus. */
3239 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
3240 /* enum: TX0 DPCPU bus. */
3241 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
3242 /* enum: TX1 DPCPU bus. */
3243 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
3244 /* enum: RX0 DICPU bus. */
3245 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
3246 /* enum: TX DICPU bus. */
3247 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
3248 /* enum: RX1 DPCPU bus. */
3249 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
3250 /* enum: RX1 DICPU bus. */
3251 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
3252 /* Pattern written to RAM / register */
3253 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
3254 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
3255 /* Actual value read from RAM / register */
3256 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
3257 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
3258 /* ECC error mask */
3259 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
3260 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
3261 /* ECC parity error mask */
3262 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
3263 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
3264 /* ECC fatal error mask */
3265 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
3266 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
3269 /***********************************/
3270 /* MC_CMD_FLUSH_RX_QUEUES
3271 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
3272 * flushes should be initiated via this MCDI operation, rather than via
3273 * directly writing FLUSH_CMD.
3275 * The flush is completed (either done/fail) asynchronously (after this command
3276 * returns). The driver must still wait for flush done/failure events as usual.
3278 #define MC_CMD_FLUSH_RX_QUEUES 0x27
3280 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
3281 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
3282 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
3283 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3284 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
3285 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
3286 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
3287 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
3289 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
3290 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
3293 /***********************************/
3294 /* MC_CMD_GET_LOOPBACK_MODES
3295 * Returns a bitmask of loopback modes available at each speed.
3297 #define MC_CMD_GET_LOOPBACK_MODES 0x28
3298 #undef MC_CMD_0x28_PRIVILEGE_CTG
3300 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3302 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
3303 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
3305 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
3306 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
3307 /* Supported loopbacks. */
3308 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
3309 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
3310 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
3311 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
3313 #define MC_CMD_LOOPBACK_NONE 0x0
3315 #define MC_CMD_LOOPBACK_DATA 0x1
3317 #define MC_CMD_LOOPBACK_GMAC 0x2
3319 #define MC_CMD_LOOPBACK_XGMII 0x3
3321 #define MC_CMD_LOOPBACK_XGXS 0x4
3323 #define MC_CMD_LOOPBACK_XAUI 0x5
3325 #define MC_CMD_LOOPBACK_GMII 0x6
3327 #define MC_CMD_LOOPBACK_SGMII 0x7
3329 #define MC_CMD_LOOPBACK_XGBR 0x8
3331 #define MC_CMD_LOOPBACK_XFI 0x9
3332 /* enum: XAUI Far. */
3333 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa
3334 /* enum: GMII Far. */
3335 #define MC_CMD_LOOPBACK_GMII_FAR 0xb
3336 /* enum: SGMII Far. */
3337 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc
3338 /* enum: XFI Far. */
3339 #define MC_CMD_LOOPBACK_XFI_FAR 0xd
3341 #define MC_CMD_LOOPBACK_GPHY 0xe
3343 #define MC_CMD_LOOPBACK_PHYXS 0xf
3345 #define MC_CMD_LOOPBACK_PCS 0x10
3346 /* enum: PMA-PMD. */
3347 #define MC_CMD_LOOPBACK_PMAPMD 0x11
3348 /* enum: Cross-Port. */
3349 #define MC_CMD_LOOPBACK_XPORT 0x12
3350 /* enum: XGMII-Wireside. */
3351 #define MC_CMD_LOOPBACK_XGMII_WS 0x13
3352 /* enum: XAUI Wireside. */
3353 #define MC_CMD_LOOPBACK_XAUI_WS 0x14
3354 /* enum: XAUI Wireside Far. */
3355 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
3356 /* enum: XAUI Wireside near. */
3357 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
3358 /* enum: GMII Wireside. */
3359 #define MC_CMD_LOOPBACK_GMII_WS 0x17
3360 /* enum: XFI Wireside. */
3361 #define MC_CMD_LOOPBACK_XFI_WS 0x18
3362 /* enum: XFI Wireside Far. */
3363 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
3364 /* enum: PhyXS Wireside. */
3365 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
3366 /* enum: PMA lanes MAC-Serdes. */
3367 #define MC_CMD_LOOPBACK_PMA_INT 0x1b
3368 /* enum: KR Serdes Parallel (Encoder). */
3369 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c
3370 /* enum: KR Serdes Serial. */
3371 #define MC_CMD_LOOPBACK_SD_FAR 0x1d
3372 /* enum: PMA lanes MAC-Serdes Wireside. */
3373 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
3374 /* enum: KR Serdes Parallel Wireside (Full PCS). */
3375 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
3376 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3377 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
3378 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3379 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
3380 /* enum: KR Serdes Serial Wireside. */
3381 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22
3382 /* enum: Near side of AOE Siena side port */
3383 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
3384 /* enum: Medford Wireside datapath loopback */
3385 #define MC_CMD_LOOPBACK_DATA_WS 0x24
3386 /* enum: Force link up without setting up any physical loopback (snapper use
3389 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
3390 /* Supported loopbacks. */
3391 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
3392 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
3393 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
3394 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
3395 /* Enum values, see field(s): */
3397 /* Supported loopbacks. */
3398 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
3399 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
3400 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
3401 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
3402 /* Enum values, see field(s): */
3404 /* Supported loopbacks. */
3405 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
3406 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
3407 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
3408 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
3409 /* Enum values, see field(s): */
3411 /* Supported loopbacks. */
3412 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
3413 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
3414 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
3415 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
3416 /* Enum values, see field(s): */
3419 /* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for
3420 * newer NICs with 25G/50G/100G support
3422 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64
3423 /* Supported loopbacks. */
3424 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
3425 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
3426 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
3427 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
3429 /* MC_CMD_LOOPBACK_NONE 0x0 */
3431 /* MC_CMD_LOOPBACK_DATA 0x1 */
3433 /* MC_CMD_LOOPBACK_GMAC 0x2 */
3435 /* MC_CMD_LOOPBACK_XGMII 0x3 */
3437 /* MC_CMD_LOOPBACK_XGXS 0x4 */
3439 /* MC_CMD_LOOPBACK_XAUI 0x5 */
3441 /* MC_CMD_LOOPBACK_GMII 0x6 */
3443 /* MC_CMD_LOOPBACK_SGMII 0x7 */
3445 /* MC_CMD_LOOPBACK_XGBR 0x8 */
3447 /* MC_CMD_LOOPBACK_XFI 0x9 */
3448 /* enum: XAUI Far. */
3449 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
3450 /* enum: GMII Far. */
3451 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */
3452 /* enum: SGMII Far. */
3453 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
3454 /* enum: XFI Far. */
3455 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */
3457 /* MC_CMD_LOOPBACK_GPHY 0xe */
3459 /* MC_CMD_LOOPBACK_PHYXS 0xf */
3461 /* MC_CMD_LOOPBACK_PCS 0x10 */
3462 /* enum: PMA-PMD. */
3463 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */
3464 /* enum: Cross-Port. */
3465 /* MC_CMD_LOOPBACK_XPORT 0x12 */
3466 /* enum: XGMII-Wireside. */
3467 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
3468 /* enum: XAUI Wireside. */
3469 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
3470 /* enum: XAUI Wireside Far. */
3471 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
3472 /* enum: XAUI Wireside near. */
3473 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
3474 /* enum: GMII Wireside. */
3475 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */
3476 /* enum: XFI Wireside. */
3477 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */
3478 /* enum: XFI Wireside Far. */
3479 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
3480 /* enum: PhyXS Wireside. */
3481 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
3482 /* enum: PMA lanes MAC-Serdes. */
3483 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */
3484 /* enum: KR Serdes Parallel (Encoder). */
3485 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
3486 /* enum: KR Serdes Serial. */
3487 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */
3488 /* enum: PMA lanes MAC-Serdes Wireside. */
3489 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
3490 /* enum: KR Serdes Parallel Wireside (Full PCS). */
3491 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
3492 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3493 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
3494 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3495 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
3496 /* enum: KR Serdes Serial Wireside. */
3497 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
3498 /* enum: Near side of AOE Siena side port */
3499 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
3500 /* enum: Medford Wireside datapath loopback */
3501 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */
3502 /* enum: Force link up without setting up any physical loopback (snapper use
3505 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
3506 /* Supported loopbacks. */
3507 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
3508 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
3509 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
3510 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
3511 /* Enum values, see field(s): */
3513 /* Supported loopbacks. */
3514 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
3515 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
3516 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
3517 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
3518 /* Enum values, see field(s): */
3520 /* Supported loopbacks. */
3521 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
3522 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
3523 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
3524 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
3525 /* Enum values, see field(s): */
3527 /* Supported loopbacks. */
3528 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
3529 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
3530 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
3531 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
3532 /* Enum values, see field(s): */
3534 /* Supported 25G loopbacks. */
3535 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
3536 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
3537 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
3538 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
3539 /* Enum values, see field(s): */
3541 /* Supported 50 loopbacks. */
3542 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
3543 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
3544 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
3545 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
3546 /* Enum values, see field(s): */
3548 /* Supported 100G loopbacks. */
3549 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
3550 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
3551 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
3552 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
3553 /* Enum values, see field(s): */
3557 /***********************************/
3559 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
3562 #define MC_CMD_GET_LINK 0x29
3563 #undef MC_CMD_0x29_PRIVILEGE_CTG
3565 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3567 /* MC_CMD_GET_LINK_IN msgrequest */
3568 #define MC_CMD_GET_LINK_IN_LEN 0
3570 /* MC_CMD_GET_LINK_OUT msgresponse */
3571 #define MC_CMD_GET_LINK_OUT_LEN 28
3572 /* near-side advertised capabilities */
3573 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
3574 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4
3575 /* link-partner advertised capabilities */
3576 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
3577 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
3578 /* Autonegotiated speed in mbit/s. The link may still be down even if this
3581 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
3582 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
3583 /* Current loopback setting. */
3584 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
3585 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
3586 /* Enum values, see field(s): */
3587 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3588 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
3589 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
3590 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
3591 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
3592 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
3593 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
3594 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
3595 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
3596 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
3597 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
3598 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
3599 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
3600 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
3601 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
3602 /* This returns the negotiated flow control value. */
3603 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
3604 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
3605 /* Enum values, see field(s): */
3606 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
3607 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
3608 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
3609 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
3610 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
3611 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
3612 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
3613 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
3614 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
3615 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
3616 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
3619 /***********************************/
3621 * Write the unified MAC/PHY link configuration. Locks required: None. Return
3622 * code: 0, EINVAL, ETIME
3624 #define MC_CMD_SET_LINK 0x2a
3625 #undef MC_CMD_0x2a_PRIVILEGE_CTG
3627 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
3629 /* MC_CMD_SET_LINK_IN msgrequest */
3630 #define MC_CMD_SET_LINK_IN_LEN 16
3632 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
3633 #define MC_CMD_SET_LINK_IN_CAP_LEN 4
3635 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
3636 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
3637 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
3638 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
3639 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
3640 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
3641 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
3642 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
3643 /* Loopback mode. */
3644 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
3645 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
3646 /* Enum values, see field(s): */
3647 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
3648 /* A loopback speed of "0" is supported, and means (choose any available
3651 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
3652 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
3654 /* MC_CMD_SET_LINK_OUT msgresponse */
3655 #define MC_CMD_SET_LINK_OUT_LEN 0
3658 /***********************************/
3659 /* MC_CMD_SET_ID_LED
3660 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
3662 #define MC_CMD_SET_ID_LED 0x2b
3663 #undef MC_CMD_0x2b_PRIVILEGE_CTG
3665 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
3667 /* MC_CMD_SET_ID_LED_IN msgrequest */
3668 #define MC_CMD_SET_ID_LED_IN_LEN 4
3669 /* Set LED state. */
3670 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
3671 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
3672 #define MC_CMD_LED_OFF 0x0 /* enum */
3673 #define MC_CMD_LED_ON 0x1 /* enum */
3674 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
3676 /* MC_CMD_SET_ID_LED_OUT msgresponse */
3677 #define MC_CMD_SET_ID_LED_OUT_LEN 0
3680 /***********************************/
3682 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
3684 #define MC_CMD_SET_MAC 0x2c
3685 #undef MC_CMD_0x2c_PRIVILEGE_CTG
3687 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3689 /* MC_CMD_SET_MAC_IN msgrequest */
3690 #define MC_CMD_SET_MAC_IN_LEN 28
3691 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
3692 * EtherII, VLAN, bug16011 padding).
3694 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
3695 #define MC_CMD_SET_MAC_IN_MTU_LEN 4
3696 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
3697 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
3698 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8
3699 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8
3700 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
3701 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
3702 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16
3703 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4
3704 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
3705 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
3706 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
3707 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
3708 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
3709 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
3710 /* enum: Flow control is off. */
3711 #define MC_CMD_FCNTL_OFF 0x0
3712 /* enum: Respond to flow control. */
3713 #define MC_CMD_FCNTL_RESPOND 0x1
3714 /* enum: Respond to and Issue flow control. */
3715 #define MC_CMD_FCNTL_BIDIR 0x2
3716 /* enum: Auto neg flow control. */
3717 #define MC_CMD_FCNTL_AUTO 0x3
3718 /* enum: Priority flow control (eftest builds only). */
3719 #define MC_CMD_FCNTL_QBB 0x4
3720 /* enum: Issue flow control. */
3721 #define MC_CMD_FCNTL_GENERATE 0x5
3722 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24
3723 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
3724 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
3725 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
3727 /* MC_CMD_SET_MAC_EXT_IN msgrequest */
3728 #define MC_CMD_SET_MAC_EXT_IN_LEN 32
3729 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
3730 * EtherII, VLAN, bug16011 padding).
3732 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
3733 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
3734 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
3735 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
3736 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
3737 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
3738 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
3739 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
3740 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
3741 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
3742 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
3743 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
3744 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
3745 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
3746 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
3747 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
3748 /* enum: Flow control is off. */
3749 /* MC_CMD_FCNTL_OFF 0x0 */
3750 /* enum: Respond to flow control. */
3751 /* MC_CMD_FCNTL_RESPOND 0x1 */
3752 /* enum: Respond to and Issue flow control. */
3753 /* MC_CMD_FCNTL_BIDIR 0x2 */
3754 /* enum: Auto neg flow control. */
3755 /* MC_CMD_FCNTL_AUTO 0x3 */
3756 /* enum: Priority flow control (eftest builds only). */
3757 /* MC_CMD_FCNTL_QBB 0x4 */
3758 /* enum: Issue flow control. */
3759 /* MC_CMD_FCNTL_GENERATE 0x5 */
3760 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
3761 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
3762 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
3763 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
3764 /* Select which parameters to configure. A parameter will only be modified if
3765 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
3766 * capabilities then this field is ignored (and all flags are assumed to be
3769 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
3770 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
3771 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
3772 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
3773 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
3774 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
3775 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
3776 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
3777 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
3778 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
3779 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
3780 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
3782 /* MC_CMD_SET_MAC_OUT msgresponse */
3783 #define MC_CMD_SET_MAC_OUT_LEN 0
3785 /* MC_CMD_SET_MAC_V2_OUT msgresponse */
3786 #define MC_CMD_SET_MAC_V2_OUT_LEN 4
3787 /* MTU as configured after processing the request. See comment at
3788 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
3791 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
3792 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
3795 /***********************************/
3797 * Get generic PHY statistics. This call returns the statistics for a generic
3798 * PHY in a sparse array (indexed by the enumerate). Each value is represented
3799 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
3800 * statistics may be read from the message response. If DMA_ADDR != 0, then the
3801 * statistics are dmad to that (page-aligned location). Locks required: None.
3804 #define MC_CMD_PHY_STATS 0x2d
3805 #undef MC_CMD_0x2d_PRIVILEGE_CTG
3807 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
3809 /* MC_CMD_PHY_STATS_IN msgrequest */
3810 #define MC_CMD_PHY_STATS_IN_LEN 8
3812 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
3813 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
3814 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
3815 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
3817 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
3818 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
3820 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
3821 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
3822 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
3823 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
3824 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
3826 #define MC_CMD_OUI 0x0
3827 /* enum: PMA-PMD Link Up. */
3828 #define MC_CMD_PMA_PMD_LINK_UP 0x1
3829 /* enum: PMA-PMD RX Fault. */
3830 #define MC_CMD_PMA_PMD_RX_FAULT 0x2
3831 /* enum: PMA-PMD TX Fault. */
3832 #define MC_CMD_PMA_PMD_TX_FAULT 0x3
3833 /* enum: PMA-PMD Signal */
3834 #define MC_CMD_PMA_PMD_SIGNAL 0x4
3835 /* enum: PMA-PMD SNR A. */
3836 #define MC_CMD_PMA_PMD_SNR_A 0x5
3837 /* enum: PMA-PMD SNR B. */
3838 #define MC_CMD_PMA_PMD_SNR_B 0x6
3839 /* enum: PMA-PMD SNR C. */
3840 #define MC_CMD_PMA_PMD_SNR_C 0x7
3841 /* enum: PMA-PMD SNR D. */
3842 #define MC_CMD_PMA_PMD_SNR_D 0x8
3843 /* enum: PCS Link Up. */
3844 #define MC_CMD_PCS_LINK_UP 0x9
3845 /* enum: PCS RX Fault. */
3846 #define MC_CMD_PCS_RX_FAULT 0xa
3847 /* enum: PCS TX Fault. */
3848 #define MC_CMD_PCS_TX_FAULT 0xb
3849 /* enum: PCS BER. */
3850 #define MC_CMD_PCS_BER 0xc
3851 /* enum: PCS Block Errors. */
3852 #define MC_CMD_PCS_BLOCK_ERRORS 0xd
3853 /* enum: PhyXS Link Up. */
3854 #define MC_CMD_PHYXS_LINK_UP 0xe
3855 /* enum: PhyXS RX Fault. */
3856 #define MC_CMD_PHYXS_RX_FAULT 0xf
3857 /* enum: PhyXS TX Fault. */
3858 #define MC_CMD_PHYXS_TX_FAULT 0x10
3859 /* enum: PhyXS Align. */
3860 #define MC_CMD_PHYXS_ALIGN 0x11
3861 /* enum: PhyXS Sync. */
3862 #define MC_CMD_PHYXS_SYNC 0x12
3863 /* enum: AN link-up. */
3864 #define MC_CMD_AN_LINK_UP 0x13
3865 /* enum: AN Complete. */
3866 #define MC_CMD_AN_COMPLETE 0x14
3867 /* enum: AN 10GBaseT Status. */
3868 #define MC_CMD_AN_10GBT_STATUS 0x15
3869 /* enum: Clause 22 Link-Up. */
3870 #define MC_CMD_CL22_LINK_UP 0x16
3871 /* enum: (Last entry) */
3872 #define MC_CMD_PHY_NSTATS 0x17
3875 /***********************************/
3877 * Get generic MAC statistics. This call returns unified statistics maintained
3878 * by the MC as it switches between the GMAC and XMAC. The MC will write out
3879 * all supported stats. The driver should zero initialise the buffer to
3880 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
3881 * performed, and the statistics may be read from the message response. If
3882 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
3883 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no
3884 * effect. Returns: 0, ETIME
3886 #define MC_CMD_MAC_STATS 0x2e
3887 #undef MC_CMD_0x2e_PRIVILEGE_CTG
3889 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3891 /* MC_CMD_MAC_STATS_IN msgrequest */
3892 #define MC_CMD_MAC_STATS_IN_LEN 20
3894 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
3895 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
3896 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
3897 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
3898 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8
3899 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4
3900 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
3901 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
3902 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
3903 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
3904 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
3905 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
3906 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
3907 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
3908 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
3909 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
3910 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
3911 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
3912 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
3913 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
3914 /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
3915 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not
3916 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to
3917 * MC_CMD_MAC_NSTATS * sizeof(uint64_t)
3919 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
3920 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
3921 /* port id so vadapter stats can be provided */
3922 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
3923 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
3925 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
3926 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
3928 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
3929 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
3930 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
3931 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
3932 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
3933 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
3934 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
3935 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
3936 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
3937 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
3938 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
3939 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
3940 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
3941 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
3942 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
3943 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
3944 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
3945 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
3946 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
3947 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
3948 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
3949 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
3950 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
3951 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
3952 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
3953 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
3954 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
3955 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
3956 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
3957 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
3958 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
3959 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
3960 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
3961 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
3962 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
3963 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
3964 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
3965 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
3966 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
3967 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
3968 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
3969 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
3970 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
3971 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
3972 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
3973 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
3974 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
3975 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
3976 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
3977 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
3978 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
3979 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
3980 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
3981 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
3982 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
3983 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
3984 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
3985 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
3986 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
3987 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
3988 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
3989 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
3990 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
3991 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
3992 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
3993 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
3994 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
3995 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
3996 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
3999 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
4000 /* enum: PM discard_bb_overflow counter. Valid for EF10 with
4001 * PM_AND_RXDP_COUNTERS capability only.
4003 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
4004 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4007 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
4008 /* enum: PM discard_vfifo_full counter. Valid for EF10 with
4009 * PM_AND_RXDP_COUNTERS capability only.
4011 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
4012 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4015 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40
4016 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4019 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41
4020 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4023 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
4024 /* enum: RXDP counter: Number of packets dropped due to the queue being
4025 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4027 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
4028 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
4029 * with PM_AND_RXDP_COUNTERS capability only.
4031 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
4032 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
4033 * PM_AND_RXDP_COUNTERS capability only.
4035 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
4036 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
4037 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4039 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
4040 /* enum: RXDP counter: Number of times the DPCPU waited for an existing
4041 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4043 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
4044 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
4045 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
4046 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
4047 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
4048 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
4049 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
4050 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
4051 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
4052 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
4053 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
4054 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
4055 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
4056 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
4057 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
4058 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
4059 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
4060 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
4061 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
4062 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
4063 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
4064 /* enum: Start of GMAC stats buffer space, for Siena only. */
4065 #define MC_CMD_GMAC_DMABUF_START 0x40
4066 /* enum: End of GMAC stats buffer space, for Siena only. */
4067 #define MC_CMD_GMAC_DMABUF_END 0x5f
4068 /* enum: GENERATION_END value, used together with GENERATION_START to verify
4069 * consistency of DMAd data. For legacy firmware / drivers without extended
4070 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
4071 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,
4072 * this value is invalid/ reserved and GENERATION_END is written as the last
4073 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
4074 * this is consistent with the legacy behaviour, in the sense that entry 96 is
4075 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
4076 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
4078 #define MC_CMD_MAC_GENERATION_END 0x60
4079 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
4081 /* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
4082 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
4084 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */
4085 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)
4086 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
4087 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
4088 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
4089 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
4090 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
4091 /* enum: Start of FEC stats buffer space, Medford2 and up */
4092 #define MC_CMD_MAC_FEC_DMABUF_START 0x61
4093 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
4095 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
4096 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
4098 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
4099 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
4100 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
4101 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
4102 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
4103 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
4104 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
4105 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
4106 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
4107 /* enum: This includes the final GENERATION_END */
4108 #define MC_CMD_MAC_NSTATS_V2 0x68
4109 /* Other enum values, see field(s): */
4110 /* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */
4113 /***********************************/
4117 #define MC_CMD_SRIOV 0x30
4119 /* MC_CMD_SRIOV_IN msgrequest */
4120 #define MC_CMD_SRIOV_IN_LEN 12
4121 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
4122 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4
4123 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
4124 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4
4125 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
4126 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
4128 /* MC_CMD_SRIOV_OUT msgresponse */
4129 #define MC_CMD_SRIOV_OUT_LEN 8
4130 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
4131 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
4132 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
4133 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
4135 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
4136 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
4137 /* this is only used for the first record */
4138 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
4139 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
4140 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
4141 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
4142 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
4143 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
4144 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
4145 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
4146 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
4147 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
4148 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
4149 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
4150 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
4151 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
4152 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
4153 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
4154 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
4155 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
4156 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
4157 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
4158 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
4159 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
4160 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
4161 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
4162 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
4163 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
4164 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
4165 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
4166 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
4169 /***********************************/
4171 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
4172 * embedded directly in the command.
4174 * A common pattern is for a client to use generation counts to signal a dma
4175 * update of a datastructure. To facilitate this, this MCDI operation can
4176 * contain multiple requests which are executed in strict order. Requests take
4177 * the form of duplicating the entire MCDI request continuously (including the
4178 * requests record, which is ignored in all but the first structure)
4180 * The source data can either come from a DMA from the host, or it can be
4181 * embedded within the request directly, thereby eliminating a DMA read. To
4182 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
4183 * ADDR_LO=offset, and inserts the data at %offset from the start of the
4184 * payload. It's the callers responsibility to ensure that the embedded data
4185 * doesn't overlap the records.
4187 * Returns: 0, EINVAL (invalid RID)
4189 #define MC_CMD_MEMCPY 0x31
4191 /* MC_CMD_MEMCPY_IN msgrequest */
4192 #define MC_CMD_MEMCPY_IN_LENMIN 32
4193 #define MC_CMD_MEMCPY_IN_LENMAX 224
4194 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
4195 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
4196 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
4197 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32
4198 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
4199 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
4201 /* MC_CMD_MEMCPY_OUT msgresponse */
4202 #define MC_CMD_MEMCPY_OUT_LEN 0
4205 /***********************************/
4206 /* MC_CMD_WOL_FILTER_SET
4209 #define MC_CMD_WOL_FILTER_SET 0x32
4210 #undef MC_CMD_0x32_PRIVILEGE_CTG
4212 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
4214 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */
4215 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192
4216 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
4217 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
4218 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
4219 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
4220 /* A type value of 1 is unused. */
4221 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
4222 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
4224 #define MC_CMD_WOL_TYPE_MAGIC 0x0
4225 /* enum: MS Windows Magic */
4226 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
4227 /* enum: IPv4 Syn */
4228 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
4229 /* enum: IPv6 Syn */
4230 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
4232 #define MC_CMD_WOL_TYPE_BITMAP 0x5
4234 #define MC_CMD_WOL_TYPE_LINK 0x6
4235 /* enum: (Above this for future use) */
4236 #define MC_CMD_WOL_TYPE_MAX 0x7
4237 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
4238 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
4239 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
4241 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
4242 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
4243 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4244 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4245 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4246 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4247 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
4248 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
4249 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
4250 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
4252 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
4253 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
4254 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4255 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4256 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4257 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4258 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
4259 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
4260 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
4261 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
4262 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
4263 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
4264 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
4265 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
4267 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
4268 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
4269 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4270 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4271 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4272 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4273 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
4274 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
4275 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
4276 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
4277 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
4278 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
4279 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
4280 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
4282 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
4283 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
4284 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4285 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4286 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4287 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4288 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
4289 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
4290 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
4291 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
4292 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
4293 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
4294 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
4295 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
4296 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
4297 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
4299 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
4300 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
4301 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4302 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
4303 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
4304 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
4305 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
4306 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
4307 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
4308 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
4309 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
4310 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
4312 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
4313 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
4314 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
4315 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
4318 /***********************************/
4319 /* MC_CMD_WOL_FILTER_REMOVE
4320 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
4322 #define MC_CMD_WOL_FILTER_REMOVE 0x33
4323 #undef MC_CMD_0x33_PRIVILEGE_CTG
4325 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
4327 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
4328 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
4329 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
4330 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
4332 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
4333 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
4336 /***********************************/
4337 /* MC_CMD_WOL_FILTER_RESET
4338 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
4341 #define MC_CMD_WOL_FILTER_RESET 0x34
4342 #undef MC_CMD_0x34_PRIVILEGE_CTG
4344 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
4346 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
4347 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
4348 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
4349 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
4350 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
4351 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
4353 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
4354 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
4357 /***********************************/
4358 /* MC_CMD_SET_MCAST_HASH
4359 * Set the MCAST hash value without otherwise reconfiguring the MAC
4361 #define MC_CMD_SET_MCAST_HASH 0x35
4363 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */
4364 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32
4365 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
4366 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
4367 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
4368 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
4370 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
4371 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
4374 /***********************************/
4375 /* MC_CMD_NVRAM_TYPES
4376 * Return bitfield indicating available types of virtual NVRAM partitions.
4377 * Locks required: none. Returns: 0
4379 #define MC_CMD_NVRAM_TYPES 0x36
4380 #undef MC_CMD_0x36_PRIVILEGE_CTG
4382 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4384 /* MC_CMD_NVRAM_TYPES_IN msgrequest */
4385 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
4387 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */
4388 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
4389 /* Bit mask of supported types. */
4390 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
4391 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
4392 /* enum: Disabled callisto. */
4393 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
4394 /* enum: MC firmware. */
4395 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1
4396 /* enum: MC backup firmware. */
4397 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
4398 /* enum: Static configuration Port0. */
4399 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
4400 /* enum: Static configuration Port1. */
4401 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
4402 /* enum: Dynamic configuration Port0. */
4403 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
4404 /* enum: Dynamic configuration Port1. */
4405 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
4406 /* enum: Expansion Rom. */
4407 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
4408 /* enum: Expansion Rom Configuration Port0. */
4409 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
4410 /* enum: Expansion Rom Configuration Port1. */
4411 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
4412 /* enum: Phy Configuration Port0. */
4413 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
4414 /* enum: Phy Configuration Port1. */
4415 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
4417 #define MC_CMD_NVRAM_TYPE_LOG 0xc
4418 /* enum: FPGA image. */
4419 #define MC_CMD_NVRAM_TYPE_FPGA 0xd
4420 /* enum: FPGA backup image */
4421 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
4422 /* enum: FC firmware. */
4423 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf
4424 /* enum: FC backup firmware. */
4425 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
4426 /* enum: CPLD image. */
4427 #define MC_CMD_NVRAM_TYPE_CPLD 0x11
4428 /* enum: Licensing information. */
4429 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12
4431 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
4432 /* enum: Additional flash on FPGA. */
4433 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
4436 /***********************************/
4437 /* MC_CMD_NVRAM_INFO
4438 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
4439 * EINVAL (bad type).
4441 #define MC_CMD_NVRAM_INFO 0x37
4442 #undef MC_CMD_0x37_PRIVILEGE_CTG
4444 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4446 /* MC_CMD_NVRAM_INFO_IN msgrequest */
4447 #define MC_CMD_NVRAM_INFO_IN_LEN 4
4448 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
4449 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
4450 /* Enum values, see field(s): */
4451 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4453 /* MC_CMD_NVRAM_INFO_OUT msgresponse */
4454 #define MC_CMD_NVRAM_INFO_OUT_LEN 24
4455 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
4456 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
4457 /* Enum values, see field(s): */
4458 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4459 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
4460 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
4461 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
4462 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
4463 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
4464 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
4465 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
4466 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
4467 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
4468 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
4469 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
4470 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
4471 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
4472 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
4473 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
4474 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
4475 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
4476 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
4477 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
4478 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
4480 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */
4481 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28
4482 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
4483 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
4484 /* Enum values, see field(s): */
4485 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4486 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
4487 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
4488 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8
4489 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
4490 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
4491 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
4492 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
4493 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
4494 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
4495 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
4496 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
4497 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
4498 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
4499 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
4500 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
4501 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
4502 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20
4503 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
4504 /* Writes must be multiples of this size. Added to support the MUM on Sorrento.
4506 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24
4507 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
4510 /***********************************/
4511 /* MC_CMD_NVRAM_UPDATE_START
4512 * Start a group of update operations on a virtual NVRAM partition. Locks
4513 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
4514 * PHY_LOCK required and not held).
4516 #define MC_CMD_NVRAM_UPDATE_START 0x38
4517 #undef MC_CMD_0x38_PRIVILEGE_CTG
4519 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4521 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.
4522 * Use NVRAM_UPDATE_START_V2_IN in new code
4524 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
4525 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
4526 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
4527 /* Enum values, see field(s): */
4528 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4530 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START
4531 * request with additional flags indicating version of command in use. See
4532 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use
4533 * paired up with NVRAM_UPDATE_FINISH_V2_IN.
4535 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8
4536 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
4537 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
4538 /* Enum values, see field(s): */
4539 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4540 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
4541 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
4542 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
4543 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
4545 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
4546 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
4549 /***********************************/
4550 /* MC_CMD_NVRAM_READ
4551 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
4552 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4553 * PHY_LOCK required and not held)
4555 #define MC_CMD_NVRAM_READ 0x39
4556 #undef MC_CMD_0x39_PRIVILEGE_CTG
4558 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4560 /* MC_CMD_NVRAM_READ_IN msgrequest */
4561 #define MC_CMD_NVRAM_READ_IN_LEN 12
4562 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
4563 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
4564 /* Enum values, see field(s): */
4565 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4566 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
4567 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
4568 /* amount to read in bytes */
4569 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
4570 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
4572 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */
4573 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16
4574 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
4575 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
4576 /* Enum values, see field(s): */
4577 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4578 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
4579 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
4580 /* amount to read in bytes */
4581 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8
4582 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
4583 /* Optional control info. If a partition is stored with an A/B versioning
4584 * scheme (i.e. in more than one physical partition in NVRAM) the host can set
4585 * this to control which underlying physical partition is used to read data
4586 * from. This allows it to perform a read-modify-write-verify with the write
4587 * lock continuously held by calling NVRAM_UPDATE_START, reading the old
4588 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then
4589 * verifying by reading with MODE=TARGET_BACKUP.
4591 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12
4592 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
4593 /* enum: Same as omitting MODE: caller sees data in current partition unless it
4594 * holds the write lock in which case it sees data in the partition it is
4597 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
4598 /* enum: Read from the current partition of an A/B pair, even if holding the
4601 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
4602 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
4605 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
4607 /* MC_CMD_NVRAM_READ_OUT msgresponse */
4608 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1
4609 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252
4610 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
4611 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
4612 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
4613 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
4614 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
4617 /***********************************/
4618 /* MC_CMD_NVRAM_WRITE
4619 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
4620 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4621 * PHY_LOCK required and not held)
4623 #define MC_CMD_NVRAM_WRITE 0x3a
4624 #undef MC_CMD_0x3a_PRIVILEGE_CTG
4626 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4628 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
4629 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
4630 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
4631 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
4632 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
4633 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
4634 /* Enum values, see field(s): */
4635 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4636 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
4637 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
4638 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
4639 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
4640 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
4641 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
4642 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
4643 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
4645 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
4646 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
4649 /***********************************/
4650 /* MC_CMD_NVRAM_ERASE
4651 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
4652 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4653 * PHY_LOCK required and not held)
4655 #define MC_CMD_NVRAM_ERASE 0x3b
4656 #undef MC_CMD_0x3b_PRIVILEGE_CTG
4658 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4660 /* MC_CMD_NVRAM_ERASE_IN msgrequest */
4661 #define MC_CMD_NVRAM_ERASE_IN_LEN 12
4662 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
4663 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
4664 /* Enum values, see field(s): */
4665 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4666 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
4667 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
4668 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
4669 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
4671 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */
4672 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
4675 /***********************************/
4676 /* MC_CMD_NVRAM_UPDATE_FINISH
4677 * Finish a group of update operations on a virtual NVRAM partition. Locks
4678 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad
4679 * type/offset/length), EACCES (if PHY_LOCK required and not held)
4681 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
4682 #undef MC_CMD_0x3c_PRIVILEGE_CTG
4684 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4686 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH
4687 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code
4689 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
4690 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
4691 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
4692 /* Enum values, see field(s): */
4693 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4694 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
4695 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
4697 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH
4698 * request with additional flags indicating version of NVRAM_UPDATE commands in
4699 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended
4700 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.
4702 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12
4703 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
4704 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
4705 /* Enum values, see field(s): */
4706 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
4707 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
4708 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
4709 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8
4710 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
4711 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
4712 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
4714 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
4715 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
4717 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
4719 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:
4721 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure
4722 * firmware validation where applicable back to the host.
4724 * Medford only: For signed firmware images, such as those for medford, the MC
4725 * firmware verifies the signature before marking the firmware image as valid.
4726 * This process takes a few seconds to complete. So is likely to take more than
4727 * the MCDI timeout. Hence signature verification is initiated when
4728 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the
4729 * MCDI command is run in a background MCDI processing thread. This response
4730 * payload includes the results of the signature verification. Note that the
4731 * per-partition nvram lock in firmware is only released after the verification
4734 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
4735 /* Result of nvram update completion processing */
4736 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
4737 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
4738 /* enum: Invalid return code; only non-zero values are defined. Defined as
4739 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
4741 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
4742 /* enum: Verify succeeded without any errors. */
4743 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
4744 /* enum: CMS format verification failed due to an internal error. */
4745 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
4746 /* enum: Invalid CMS format in image metadata. */
4747 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
4748 /* enum: Message digest verification failed due to an internal error. */
4749 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
4750 /* enum: Error in message digest calculated over the reflash-header, payload
4751 * and reflash-trailer.
4753 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
4754 /* enum: Signature verification failed due to an internal error. */
4755 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
4756 /* enum: There are no valid signatures in the image. */
4757 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
4758 /* enum: Trusted approvers verification failed due to an internal error. */
4759 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
4760 /* enum: The Trusted approver's list is empty. */
4761 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
4762 /* enum: Signature chain verification failed due to an internal error. */
4763 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
4764 /* enum: The signers of the signatures in the image are not listed in the
4765 * Trusted approver's list.
4767 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
4768 /* enum: The image contains a test-signed certificate, but the adapter accepts
4769 * only production signed images.
4771 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
4772 /* enum: The image has a lower security level than the current firmware. */
4773 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
4776 /***********************************/
4780 * The AFTER_ASSERTION flag is intended to be used when the driver notices an
4781 * assertion failure (at which point it is expected to perform a complete tear
4782 * down and reinitialise), to allow both ports to reset the MC once in an
4785 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
4786 * which means that they will automatically reboot out of the assertion
4787 * handler, so this is in practise an optional operation. It is still
4788 * recommended that drivers execute this to support custom firmwares with
4789 * REBOOT_ON_ASSERT=0.
4791 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
4794 #define MC_CMD_REBOOT 0x3d
4795 #undef MC_CMD_0x3d_PRIVILEGE_CTG
4797 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4799 /* MC_CMD_REBOOT_IN msgrequest */
4800 #define MC_CMD_REBOOT_IN_LEN 4
4801 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
4802 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4
4803 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
4805 /* MC_CMD_REBOOT_OUT msgresponse */
4806 #define MC_CMD_REBOOT_OUT_LEN 0
4809 /***********************************/
4811 * Request scheduler info. Locks required: NONE. Returns: An array of
4812 * (timeslice,maximum overrun), one for each thread, in ascending order of
4815 #define MC_CMD_SCHEDINFO 0x3e
4816 #undef MC_CMD_0x3e_PRIVILEGE_CTG
4818 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4820 /* MC_CMD_SCHEDINFO_IN msgrequest */
4821 #define MC_CMD_SCHEDINFO_IN_LEN 0
4823 /* MC_CMD_SCHEDINFO_OUT msgresponse */
4824 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
4825 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252
4826 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
4827 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
4828 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
4829 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
4830 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
4833 /***********************************/
4834 /* MC_CMD_REBOOT_MODE
4835 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
4836 * mode to the specified value. Returns the old mode.
4838 #define MC_CMD_REBOOT_MODE 0x3f
4839 #undef MC_CMD_0x3f_PRIVILEGE_CTG
4841 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
4843 /* MC_CMD_REBOOT_MODE_IN msgrequest */
4844 #define MC_CMD_REBOOT_MODE_IN_LEN 4
4845 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
4846 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
4848 #define MC_CMD_REBOOT_MODE_NORMAL 0x0
4849 /* enum: Power-on Reset. */
4850 #define MC_CMD_REBOOT_MODE_POR 0x2
4851 /* enum: Snapper. */
4852 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3
4853 /* enum: snapper fake POR */
4854 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
4855 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
4856 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
4858 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
4859 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
4860 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
4861 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
4864 /***********************************/
4865 /* MC_CMD_SENSOR_INFO
4866 * Returns information about every available sensor.
4868 * Each sensor has a single (16bit) value, and a corresponding state. The
4869 * mapping between value and state is nominally determined by the MC, but may
4870 * be implemented using up to 2 ranges per sensor.
4872 * This call returns a mask (32bit) of the sensors that are supported by this
4873 * platform, then an array of sensor information structures, in order of sensor
4874 * type (but without gaps for unimplemented sensors). Each structure defines
4875 * the ranges for the corresponding sensor. An unused range is indicated by
4876 * equal limit values. If one range is used, a value outside that range results
4877 * in STATE_FATAL. If two ranges are used, a value outside the second range
4878 * results in STATE_FATAL while a value outside the first and inside the second
4879 * range results in STATE_WARNING.
4881 * Sensor masks and sensor information arrays are organised into pages. For
4882 * backward compatibility, older host software can only use sensors in page 0.
4883 * Bit 32 in the sensor mask was previously unused, and is no reserved for use
4884 * as the next page flag.
4886 * If the request does not contain a PAGE value then firmware will only return
4887 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
4889 * If the request contains a PAGE value then firmware responds with the sensor
4890 * mask and sensor information array for that page of sensors. In this case bit
4891 * 31 in the mask is set if another page exists.
4893 * Locks required: None Returns: 0
4895 #define MC_CMD_SENSOR_INFO 0x41
4896 #undef MC_CMD_0x41_PRIVILEGE_CTG
4898 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4900 /* MC_CMD_SENSOR_INFO_IN msgrequest */
4901 #define MC_CMD_SENSOR_INFO_IN_LEN 0
4903 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
4904 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
4905 /* Which page of sensors to report.
4907 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
4909 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
4911 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
4912 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
4914 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
4915 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
4916 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
4917 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
4918 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
4919 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
4920 /* enum: Controller temperature: degC */
4921 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
4922 /* enum: Phy common temperature: degC */
4923 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
4924 /* enum: Controller cooling: bool */
4925 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
4926 /* enum: Phy 0 temperature: degC */
4927 #define MC_CMD_SENSOR_PHY0_TEMP 0x3
4928 /* enum: Phy 0 cooling: bool */
4929 #define MC_CMD_SENSOR_PHY0_COOLING 0x4
4930 /* enum: Phy 1 temperature: degC */
4931 #define MC_CMD_SENSOR_PHY1_TEMP 0x5
4932 /* enum: Phy 1 cooling: bool */
4933 #define MC_CMD_SENSOR_PHY1_COOLING 0x6
4934 /* enum: 1.0v power: mV */
4935 #define MC_CMD_SENSOR_IN_1V0 0x7
4936 /* enum: 1.2v power: mV */
4937 #define MC_CMD_SENSOR_IN_1V2 0x8
4938 /* enum: 1.8v power: mV */
4939 #define MC_CMD_SENSOR_IN_1V8 0x9
4940 /* enum: 2.5v power: mV */
4941 #define MC_CMD_SENSOR_IN_2V5 0xa
4942 /* enum: 3.3v power: mV */
4943 #define MC_CMD_SENSOR_IN_3V3 0xb
4944 /* enum: 12v power: mV */
4945 #define MC_CMD_SENSOR_IN_12V0 0xc
4946 /* enum: 1.2v analogue power: mV */
4947 #define MC_CMD_SENSOR_IN_1V2A 0xd
4948 /* enum: reference voltage: mV */
4949 #define MC_CMD_SENSOR_IN_VREF 0xe
4950 /* enum: AOE FPGA power: mV */
4951 #define MC_CMD_SENSOR_OUT_VAOE 0xf
4952 /* enum: AOE FPGA temperature: degC */
4953 #define MC_CMD_SENSOR_AOE_TEMP 0x10
4954 /* enum: AOE FPGA PSU temperature: degC */
4955 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
4956 /* enum: AOE PSU temperature: degC */
4957 #define MC_CMD_SENSOR_PSU_TEMP 0x12
4958 /* enum: Fan 0 speed: RPM */
4959 #define MC_CMD_SENSOR_FAN_0 0x13
4960 /* enum: Fan 1 speed: RPM */
4961 #define MC_CMD_SENSOR_FAN_1 0x14
4962 /* enum: Fan 2 speed: RPM */
4963 #define MC_CMD_SENSOR_FAN_2 0x15
4964 /* enum: Fan 3 speed: RPM */
4965 #define MC_CMD_SENSOR_FAN_3 0x16
4966 /* enum: Fan 4 speed: RPM */
4967 #define MC_CMD_SENSOR_FAN_4 0x17
4968 /* enum: AOE FPGA input power: mV */
4969 #define MC_CMD_SENSOR_IN_VAOE 0x18
4970 /* enum: AOE FPGA current: mA */
4971 #define MC_CMD_SENSOR_OUT_IAOE 0x19
4972 /* enum: AOE FPGA input current: mA */
4973 #define MC_CMD_SENSOR_IN_IAOE 0x1a
4974 /* enum: NIC power consumption: W */
4975 #define MC_CMD_SENSOR_NIC_POWER 0x1b
4976 /* enum: 0.9v power voltage: mV */
4977 #define MC_CMD_SENSOR_IN_0V9 0x1c
4978 /* enum: 0.9v power current: mA */
4979 #define MC_CMD_SENSOR_IN_I0V9 0x1d
4980 /* enum: 1.2v power current: mA */
4981 #define MC_CMD_SENSOR_IN_I1V2 0x1e
4982 /* enum: Not a sensor: reserved for the next page flag */
4983 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
4984 /* enum: 0.9v power voltage (at ADC): mV */
4985 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20
4986 /* enum: Controller temperature 2: degC */
4987 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
4988 /* enum: Voltage regulator internal temperature: degC */
4989 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
4990 /* enum: 0.9V voltage regulator temperature: degC */
4991 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
4992 /* enum: 1.2V voltage regulator temperature: degC */
4993 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
4994 /* enum: controller internal temperature sensor voltage (internal ADC): mV */
4995 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
4996 /* enum: controller internal temperature (internal ADC): degC */
4997 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
4998 /* enum: controller internal temperature sensor voltage (external ADC): mV */
4999 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
5000 /* enum: controller internal temperature (external ADC): degC */
5001 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
5002 /* enum: ambient temperature: degC */
5003 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
5004 /* enum: air flow: bool */
5005 #define MC_CMD_SENSOR_AIRFLOW 0x2a
5006 /* enum: voltage between VSS08D and VSS08D at CSR: mV */
5007 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
5008 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
5009 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
5010 /* enum: Hotpoint temperature: degC */
5011 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
5012 /* enum: Port 0 PHY power switch over-current: bool */
5013 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
5014 /* enum: Port 1 PHY power switch over-current: bool */
5015 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
5016 /* enum: Mop-up microcontroller reference voltage (millivolts) */
5017 #define MC_CMD_SENSOR_MUM_VCC 0x30
5018 /* enum: 0.9v power phase A voltage: mV */
5019 #define MC_CMD_SENSOR_IN_0V9_A 0x31
5020 /* enum: 0.9v power phase A current: mA */
5021 #define MC_CMD_SENSOR_IN_I0V9_A 0x32
5022 /* enum: 0.9V voltage regulator phase A temperature: degC */
5023 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
5024 /* enum: 0.9v power phase B voltage: mV */
5025 #define MC_CMD_SENSOR_IN_0V9_B 0x34
5026 /* enum: 0.9v power phase B current: mA */
5027 #define MC_CMD_SENSOR_IN_I0V9_B 0x35
5028 /* enum: 0.9V voltage regulator phase B temperature: degC */
5029 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
5030 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
5031 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
5032 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */
5033 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
5034 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
5035 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
5036 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */
5037 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
5038 /* enum: CCOM RTS temperature: degC */
5039 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
5040 /* enum: Not a sensor: reserved for the next page flag */
5041 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
5042 /* enum: controller internal temperature sensor voltage on master core
5043 * (internal ADC): mV
5045 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
5046 /* enum: controller internal temperature on master core (internal ADC): degC */
5047 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
5048 /* enum: controller internal temperature sensor voltage on master core
5049 * (external ADC): mV
5051 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
5052 /* enum: controller internal temperature on master core (external ADC): degC */
5053 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
5054 /* enum: controller internal temperature on slave core sensor voltage (internal
5057 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
5058 /* enum: controller internal temperature on slave core (internal ADC): degC */
5059 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
5060 /* enum: controller internal temperature on slave core sensor voltage (external
5063 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
5064 /* enum: controller internal temperature on slave core (external ADC): degC */
5065 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
5066 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */
5067 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49
5068 /* enum: Temperature of SODIMM 0 (if installed): degC */
5069 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
5070 /* enum: Temperature of SODIMM 1 (if installed): degC */
5071 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
5072 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
5073 #define MC_CMD_SENSOR_PHY0_VCC 0x4c
5074 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
5075 #define MC_CMD_SENSOR_PHY1_VCC 0x4d
5076 /* enum: Controller die temperature (TDIODE): degC */
5077 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
5078 /* enum: Board temperature (front): degC */
5079 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
5080 /* enum: Board temperature (back): degC */
5081 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
5082 /* enum: 1.8v power current: mA */
5083 #define MC_CMD_SENSOR_IN_I1V8 0x51
5084 /* enum: 2.5v power current: mA */
5085 #define MC_CMD_SENSOR_IN_I2V5 0x52
5086 /* enum: 3.3v power current: mA */
5087 #define MC_CMD_SENSOR_IN_I3V3 0x53
5088 /* enum: 12v power current: mA */
5089 #define MC_CMD_SENSOR_IN_I12V0 0x54
5090 /* enum: Not a sensor: reserved for the next page flag */
5091 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
5092 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
5093 #define MC_CMD_SENSOR_ENTRY_OFST 4
5094 #define MC_CMD_SENSOR_ENTRY_LEN 8
5095 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
5096 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8
5097 #define MC_CMD_SENSOR_ENTRY_MINNUM 0
5098 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31
5100 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
5101 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
5102 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
5103 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
5104 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
5105 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
5106 /* Enum values, see field(s): */
5107 /* MC_CMD_SENSOR_INFO_OUT */
5108 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
5109 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
5110 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
5111 /* MC_CMD_SENSOR_ENTRY_OFST 4 */
5112 /* MC_CMD_SENSOR_ENTRY_LEN 8 */
5113 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
5114 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
5115 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
5116 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
5118 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
5119 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
5120 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
5121 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
5122 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
5123 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
5124 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
5125 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
5126 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
5127 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
5128 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
5129 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
5130 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
5131 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
5132 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
5133 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
5134 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
5135 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
5138 /***********************************/
5139 /* MC_CMD_READ_SENSORS
5140 * Returns the current reading from each sensor. DMAs an array of sensor
5141 * readings, in order of sensor type (but without gaps for unimplemented
5142 * sensors), into host memory. Each array element is a
5143 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
5145 * If the request does not contain the LENGTH field then only sensors 0 to 30
5146 * are reported, to avoid DMA buffer overflow in older host software. If the
5147 * sensor reading require more space than the LENGTH allows, then return
5150 * The MC will send a SENSOREVT event every time any sensor changes state. The
5151 * driver is responsible for ensuring that it doesn't miss any events. The
5152 * board will function normally if all sensors are in STATE_OK or
5153 * STATE_WARNING. Otherwise the board should not be expected to function.
5155 #define MC_CMD_READ_SENSORS 0x42
5156 #undef MC_CMD_0x42_PRIVILEGE_CTG
5158 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5160 /* MC_CMD_READ_SENSORS_IN msgrequest */
5161 #define MC_CMD_READ_SENSORS_IN_LEN 8
5162 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
5163 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
5164 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
5165 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
5166 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
5168 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
5169 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
5170 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
5171 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
5172 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
5173 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
5174 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
5175 /* Size in bytes of host buffer. */
5176 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
5177 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
5179 /* MC_CMD_READ_SENSORS_OUT msgresponse */
5180 #define MC_CMD_READ_SENSORS_OUT_LEN 0
5182 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
5183 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
5185 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
5186 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
5187 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
5188 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
5189 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
5190 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
5191 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
5192 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
5194 #define MC_CMD_SENSOR_STATE_OK 0x0
5195 /* enum: Breached warning threshold. */
5196 #define MC_CMD_SENSOR_STATE_WARNING 0x1
5197 /* enum: Breached fatal threshold. */
5198 #define MC_CMD_SENSOR_STATE_FATAL 0x2
5199 /* enum: Fault with sensor. */
5200 #define MC_CMD_SENSOR_STATE_BROKEN 0x3
5201 /* enum: Sensor is working but does not currently have a reading. */
5202 #define MC_CMD_SENSOR_STATE_NO_READING 0x4
5203 /* enum: Sensor initialisation failed. */
5204 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
5205 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
5206 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
5207 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
5208 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
5209 /* Enum values, see field(s): */
5210 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
5211 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
5212 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
5215 /***********************************/
5216 /* MC_CMD_GET_PHY_STATE
5217 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
5218 * (e.g. due to missing or corrupted firmware). Locks required: None. Return
5221 #define MC_CMD_GET_PHY_STATE 0x43
5222 #undef MC_CMD_0x43_PRIVILEGE_CTG
5224 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5226 /* MC_CMD_GET_PHY_STATE_IN msgrequest */
5227 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
5229 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */
5230 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
5231 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
5232 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
5234 #define MC_CMD_PHY_STATE_OK 0x1
5236 #define MC_CMD_PHY_STATE_ZOMBIE 0x2
5239 /***********************************/
5240 /* MC_CMD_SETUP_8021QBB
5241 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
5242 * disable 802.Qbb for a given priority.
5244 #define MC_CMD_SETUP_8021QBB 0x44
5246 /* MC_CMD_SETUP_8021QBB_IN msgrequest */
5247 #define MC_CMD_SETUP_8021QBB_IN_LEN 32
5248 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
5249 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
5251 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */
5252 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
5255 /***********************************/
5256 /* MC_CMD_WOL_FILTER_GET
5257 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
5259 #define MC_CMD_WOL_FILTER_GET 0x45
5260 #undef MC_CMD_0x45_PRIVILEGE_CTG
5262 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
5264 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */
5265 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
5267 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
5268 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
5269 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
5270 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
5273 /***********************************/
5274 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
5275 * Add a protocol offload to NIC for lights-out state. Locks required: None.
5276 * Returns: 0, ENOSYS
5278 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
5279 #undef MC_CMD_0x46_PRIVILEGE_CTG
5281 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
5283 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
5284 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
5285 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
5286 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
5287 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
5288 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
5289 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
5290 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
5291 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
5292 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
5293 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
5294 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
5296 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
5297 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
5298 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
5299 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
5300 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
5301 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
5302 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
5303 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
5305 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
5306 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
5307 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
5308 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
5309 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
5310 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
5311 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
5312 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
5313 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
5314 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
5316 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
5317 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
5318 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
5319 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
5322 /***********************************/
5323 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
5324 * Remove a protocol offload from NIC for lights-out state. Locks required:
5325 * None. Returns: 0, ENOSYS
5327 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
5328 #undef MC_CMD_0x47_PRIVILEGE_CTG
5330 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
5332 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
5333 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
5334 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
5335 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
5336 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
5337 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
5339 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
5340 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
5343 /***********************************/
5344 /* MC_CMD_MAC_RESET_RESTORE
5345 * Restore MAC after block reset. Locks required: None. Returns: 0.
5347 #define MC_CMD_MAC_RESET_RESTORE 0x48
5349 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
5350 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
5352 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
5353 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
5356 /***********************************/
5357 /* MC_CMD_TESTASSERT
5358 * Deliberately trigger an assert-detonation in the firmware for testing
5359 * purposes (i.e. to allow tests that the driver copes gracefully). Locks
5360 * required: None Returns: 0
5362 #define MC_CMD_TESTASSERT 0x49
5363 #undef MC_CMD_0x49_PRIVILEGE_CTG
5365 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5367 /* MC_CMD_TESTASSERT_IN msgrequest */
5368 #define MC_CMD_TESTASSERT_IN_LEN 0
5370 /* MC_CMD_TESTASSERT_OUT msgresponse */
5371 #define MC_CMD_TESTASSERT_OUT_LEN 0
5373 /* MC_CMD_TESTASSERT_V2_IN msgrequest */
5374 #define MC_CMD_TESTASSERT_V2_IN_LEN 4
5375 /* How to provoke the assertion */
5376 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
5377 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
5378 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless
5379 * you're testing firmware, this is what you want.
5381 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
5382 /* enum: Assert using assert(0); */
5383 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
5384 /* enum: Deliberately trigger a watchdog */
5385 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
5386 /* enum: Deliberately trigger a trap by loading from an invalid address */
5387 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
5388 /* enum: Deliberately trigger a trap by storing to an invalid address */
5389 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
5390 /* enum: Jump to an invalid address */
5391 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
5393 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */
5394 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0
5397 /***********************************/
5398 /* MC_CMD_WORKAROUND
5399 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
5400 * understand the given workaround number - which should not be treated as a
5401 * hard error by client code. This op does not imply any semantics about each
5402 * workaround, that's between the driver and the mcfw on a per-workaround
5403 * basis. Locks required: None. Returns: 0, EINVAL .
5405 #define MC_CMD_WORKAROUND 0x4a
5406 #undef MC_CMD_0x4a_PRIVILEGE_CTG
5408 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5410 /* MC_CMD_WORKAROUND_IN msgrequest */
5411 #define MC_CMD_WORKAROUND_IN_LEN 8
5412 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
5413 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
5414 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
5415 /* enum: Bug 17230 work around. */
5416 #define MC_CMD_WORKAROUND_BUG17230 0x1
5417 /* enum: Bug 35388 work around (unsafe EVQ writes). */
5418 #define MC_CMD_WORKAROUND_BUG35388 0x2
5419 /* enum: Bug35017 workaround (A64 tables must be identity map) */
5420 #define MC_CMD_WORKAROUND_BUG35017 0x3
5421 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
5422 #define MC_CMD_WORKAROUND_BUG41750 0x4
5423 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
5424 * - before adding code that queries this workaround, remember that there's
5425 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
5426 * and will hence (incorrectly) report that the bug doesn't exist.
5428 #define MC_CMD_WORKAROUND_BUG42008 0x5
5429 /* enum: Bug 26807 features present in firmware (multicast filter chaining)
5430 * This feature cannot be turned on/off while there are any filters already
5431 * present. The behaviour in such case depends on the acting client's privilege
5432 * level. If the client has the admin privilege, then all functions that have
5433 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
5434 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
5436 #define MC_CMD_WORKAROUND_BUG26807 0x6
5437 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
5438 #define MC_CMD_WORKAROUND_BUG61265 0x7
5439 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
5442 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
5443 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
5445 /* MC_CMD_WORKAROUND_OUT msgresponse */
5446 #define MC_CMD_WORKAROUND_OUT_LEN 0
5448 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
5449 * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
5451 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
5452 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
5453 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
5454 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
5455 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
5458 /***********************************/
5459 /* MC_CMD_GET_PHY_MEDIA_INFO
5460 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
5461 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG
5462 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the
5463 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
5464 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
5465 * Anything else: currently undefined. Locks required: None. Return code: 0.
5467 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
5468 #undef MC_CMD_0x4b_PRIVILEGE_CTG
5470 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5472 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
5473 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
5474 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
5475 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
5477 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
5478 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
5479 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
5480 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
5482 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
5483 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
5484 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
5485 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
5486 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
5487 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
5490 /***********************************/
5491 /* MC_CMD_NVRAM_TEST
5492 * Test a particular NVRAM partition for valid contents (where "valid" depends
5493 * on the type of partition).
5495 #define MC_CMD_NVRAM_TEST 0x4c
5496 #undef MC_CMD_0x4c_PRIVILEGE_CTG
5498 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5500 /* MC_CMD_NVRAM_TEST_IN msgrequest */
5501 #define MC_CMD_NVRAM_TEST_IN_LEN 4
5502 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
5503 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
5504 /* Enum values, see field(s): */
5505 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5507 /* MC_CMD_NVRAM_TEST_OUT msgresponse */
5508 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
5509 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
5510 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
5512 #define MC_CMD_NVRAM_TEST_PASS 0x0
5514 #define MC_CMD_NVRAM_TEST_FAIL 0x1
5515 /* enum: Not supported. */
5516 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
5519 /***********************************/
5520 /* MC_CMD_MRSFP_TWEAK
5521 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
5522 * I2C I/O expander bits are always read; if equaliser parameters are supplied,
5523 * they are configured first. Locks required: None. Return code: 0, EINVAL.
5525 #define MC_CMD_MRSFP_TWEAK 0x4d
5527 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
5528 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
5529 /* 0-6 low->high de-emph. */
5530 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
5531 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
5532 /* 0-8 low->high ref.V */
5533 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
5534 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
5535 /* 0-8 0-8 low->high boost */
5536 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
5537 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
5538 /* 0-8 low->high ref.V */
5539 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
5540 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
5542 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
5543 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
5545 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
5546 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
5548 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
5549 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
5551 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
5552 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
5554 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
5555 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
5557 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
5559 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
5562 /***********************************/
5563 /* MC_CMD_SENSOR_SET_LIMS
5564 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
5565 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
5568 #define MC_CMD_SENSOR_SET_LIMS 0x4e
5569 #undef MC_CMD_0x4e_PRIVILEGE_CTG
5571 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
5573 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
5574 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
5575 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
5576 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
5577 /* Enum values, see field(s): */
5578 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
5579 /* interpretation is is sensor-specific. */
5580 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
5581 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
5582 /* interpretation is is sensor-specific. */
5583 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
5584 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
5585 /* interpretation is is sensor-specific. */
5586 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
5587 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
5588 /* interpretation is is sensor-specific. */
5589 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
5590 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
5592 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
5593 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
5596 /***********************************/
5597 /* MC_CMD_GET_RESOURCE_LIMITS
5599 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
5601 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
5602 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
5604 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
5605 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
5606 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
5607 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
5608 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
5609 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
5610 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
5611 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
5612 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
5613 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
5616 /***********************************/
5617 /* MC_CMD_NVRAM_PARTITIONS
5618 * Reads the list of available virtual NVRAM partition types. Locks required:
5619 * none. Returns: 0, EINVAL (bad type).
5621 #define MC_CMD_NVRAM_PARTITIONS 0x51
5622 #undef MC_CMD_0x51_PRIVILEGE_CTG
5624 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5626 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
5627 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
5629 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
5630 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
5631 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
5632 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
5633 /* total number of partitions */
5634 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
5635 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
5636 /* type ID code for each of NUM_PARTITIONS partitions */
5637 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
5638 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
5639 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
5640 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
5643 /***********************************/
5644 /* MC_CMD_NVRAM_METADATA
5645 * Reads soft metadata for a virtual NVRAM partition type. Locks required:
5646 * none. Returns: 0, EINVAL (bad type).
5648 #define MC_CMD_NVRAM_METADATA 0x52
5649 #undef MC_CMD_0x52_PRIVILEGE_CTG
5651 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5653 /* MC_CMD_NVRAM_METADATA_IN msgrequest */
5654 #define MC_CMD_NVRAM_METADATA_IN_LEN 4
5655 /* Partition type ID code */
5656 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
5657 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
5659 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */
5660 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
5661 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
5662 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
5663 /* Partition type ID code */
5664 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
5665 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
5666 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
5667 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
5668 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
5669 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
5670 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
5671 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
5672 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
5673 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
5674 /* Subtype ID code for content of this partition */
5675 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
5676 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
5677 /* 1st component of W.X.Y.Z version number for content of this partition */
5678 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
5679 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
5680 /* 2nd component of W.X.Y.Z version number for content of this partition */
5681 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
5682 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
5683 /* 3rd component of W.X.Y.Z version number for content of this partition */
5684 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
5685 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
5686 /* 4th component of W.X.Y.Z version number for content of this partition */
5687 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
5688 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
5689 /* Zero-terminated string describing the content of this partition */
5690 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
5691 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
5692 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
5693 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
5696 /***********************************/
5697 /* MC_CMD_GET_MAC_ADDRESSES
5698 * Returns the base MAC, count and stride for the requesting function
5700 #define MC_CMD_GET_MAC_ADDRESSES 0x55
5701 #undef MC_CMD_0x55_PRIVILEGE_CTG
5703 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5705 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
5706 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
5708 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
5709 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
5710 /* Base MAC address */
5711 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
5712 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
5714 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
5715 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
5716 /* Number of allocated MAC addresses */
5717 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
5718 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
5719 /* Spacing of allocated MAC addresses */
5720 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
5721 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
5724 /***********************************/
5726 * Perform a CLP related operation
5728 #define MC_CMD_CLP 0x56
5729 #undef MC_CMD_0x56_PRIVILEGE_CTG
5731 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5733 /* MC_CMD_CLP_IN msgrequest */
5734 #define MC_CMD_CLP_IN_LEN 4
5736 #define MC_CMD_CLP_IN_OP_OFST 0
5737 #define MC_CMD_CLP_IN_OP_LEN 4
5738 /* enum: Return to factory default settings */
5739 #define MC_CMD_CLP_OP_DEFAULT 0x1
5740 /* enum: Set MAC address */
5741 #define MC_CMD_CLP_OP_SET_MAC 0x2
5742 /* enum: Get MAC address */
5743 #define MC_CMD_CLP_OP_GET_MAC 0x3
5744 /* enum: Set UEFI/GPXE boot mode */
5745 #define MC_CMD_CLP_OP_SET_BOOT 0x4
5746 /* enum: Get UEFI/GPXE boot mode */
5747 #define MC_CMD_CLP_OP_GET_BOOT 0x5
5749 /* MC_CMD_CLP_OUT msgresponse */
5750 #define MC_CMD_CLP_OUT_LEN 0
5752 /* MC_CMD_CLP_IN_DEFAULT msgrequest */
5753 #define MC_CMD_CLP_IN_DEFAULT_LEN 4
5754 /* MC_CMD_CLP_IN_OP_OFST 0 */
5755 /* MC_CMD_CLP_IN_OP_LEN 4 */
5757 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */
5758 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0
5760 /* MC_CMD_CLP_IN_SET_MAC msgrequest */
5761 #define MC_CMD_CLP_IN_SET_MAC_LEN 12
5762 /* MC_CMD_CLP_IN_OP_OFST 0 */
5763 /* MC_CMD_CLP_IN_OP_LEN 4 */
5764 /* MAC address assigned to port */
5765 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
5766 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
5768 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10
5769 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2
5771 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */
5772 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0
5774 /* MC_CMD_CLP_IN_GET_MAC msgrequest */
5775 #define MC_CMD_CLP_IN_GET_MAC_LEN 4
5776 /* MC_CMD_CLP_IN_OP_OFST 0 */
5777 /* MC_CMD_CLP_IN_OP_LEN 4 */
5779 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */
5780 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8
5781 /* MAC address assigned to port */
5782 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
5783 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6
5785 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6
5786 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2
5788 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */
5789 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5
5790 /* MC_CMD_CLP_IN_OP_OFST 0 */
5791 /* MC_CMD_CLP_IN_OP_LEN 4 */
5793 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
5794 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
5796 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */
5797 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0
5799 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */
5800 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4
5801 /* MC_CMD_CLP_IN_OP_OFST 0 */
5802 /* MC_CMD_CLP_IN_OP_LEN 4 */
5804 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */
5805 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4
5807 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
5808 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
5810 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
5811 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3
5814 /***********************************/
5816 * Perform a MUM operation
5818 #define MC_CMD_MUM 0x57
5819 #undef MC_CMD_0x57_PRIVILEGE_CTG
5821 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
5823 /* MC_CMD_MUM_IN msgrequest */
5824 #define MC_CMD_MUM_IN_LEN 4
5825 #define MC_CMD_MUM_IN_OP_HDR_OFST 0
5826 #define MC_CMD_MUM_IN_OP_HDR_LEN 4
5827 #define MC_CMD_MUM_IN_OP_LBN 0
5828 #define MC_CMD_MUM_IN_OP_WIDTH 8
5829 /* enum: NULL MCDI command to MUM */
5830 #define MC_CMD_MUM_OP_NULL 0x1
5831 /* enum: Get MUM version */
5832 #define MC_CMD_MUM_OP_GET_VERSION 0x2
5833 /* enum: Issue raw I2C command to MUM */
5834 #define MC_CMD_MUM_OP_RAW_CMD 0x3
5835 /* enum: Read from registers on devices connected to MUM. */
5836 #define MC_CMD_MUM_OP_READ 0x4
5837 /* enum: Write to registers on devices connected to MUM. */
5838 #define MC_CMD_MUM_OP_WRITE 0x5
5839 /* enum: Control UART logging. */
5840 #define MC_CMD_MUM_OP_LOG 0x6
5841 /* enum: Operations on MUM GPIO lines */
5842 #define MC_CMD_MUM_OP_GPIO 0x7
5843 /* enum: Get sensor readings from MUM */
5844 #define MC_CMD_MUM_OP_READ_SENSORS 0x8
5845 /* enum: Initiate clock programming on the MUM */
5846 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
5847 /* enum: Initiate FPGA load from flash on the MUM */
5848 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa
5849 /* enum: Request sensor reading from MUM ADC resulting from earlier request via
5852 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
5853 /* enum: Send commands relating to the QSFP ports via the MUM for PHY
5856 #define MC_CMD_MUM_OP_QSFP 0xc
5857 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage
5860 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd
5862 /* MC_CMD_MUM_IN_NULL msgrequest */
5863 #define MC_CMD_MUM_IN_NULL_LEN 4
5864 /* MUM cmd header */
5865 #define MC_CMD_MUM_IN_CMD_OFST 0
5866 #define MC_CMD_MUM_IN_CMD_LEN 4
5868 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */
5869 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4
5870 /* MUM cmd header */
5871 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5872 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5874 /* MC_CMD_MUM_IN_READ msgrequest */
5875 #define MC_CMD_MUM_IN_READ_LEN 16
5876 /* MUM cmd header */
5877 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5878 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5879 /* ID of (device connected to MUM) to read from registers of */
5880 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4
5881 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4
5882 /* enum: Hittite HMC1035 clock generator on Sorrento board */
5883 #define MC_CMD_MUM_DEV_HITTITE 0x1
5884 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
5885 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2
5886 /* 32-bit address to read from */
5887 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8
5888 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4
5889 /* Number of words to read. */
5890 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12
5891 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
5893 /* MC_CMD_MUM_IN_WRITE msgrequest */
5894 #define MC_CMD_MUM_IN_WRITE_LENMIN 16
5895 #define MC_CMD_MUM_IN_WRITE_LENMAX 252
5896 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
5897 /* MUM cmd header */
5898 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5899 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5900 /* ID of (device connected to MUM) to write to registers of */
5901 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
5902 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
5903 /* enum: Hittite HMC1035 clock generator on Sorrento board */
5904 /* MC_CMD_MUM_DEV_HITTITE 0x1 */
5905 /* 32-bit address to write to */
5906 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8
5907 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
5908 /* Words to write */
5909 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12
5910 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
5911 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
5912 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60
5914 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */
5915 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17
5916 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
5917 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
5918 /* MUM cmd header */
5919 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5920 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5921 /* MUM I2C cmd code */
5922 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
5923 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
5924 /* Number of bytes to write */
5925 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8
5926 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
5927 /* Number of bytes to read */
5928 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12
5929 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
5930 /* Bytes to write */
5931 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16
5932 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
5933 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
5934 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236
5936 /* MC_CMD_MUM_IN_LOG msgrequest */
5937 #define MC_CMD_MUM_IN_LOG_LEN 8
5938 /* MUM cmd header */
5939 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5940 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5941 #define MC_CMD_MUM_IN_LOG_OP_OFST 4
5942 #define MC_CMD_MUM_IN_LOG_OP_LEN 4
5943 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
5945 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */
5946 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12
5947 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5948 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5949 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */
5950 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */
5951 /* Enable/disable debug output to UART */
5952 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8
5953 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
5955 /* MC_CMD_MUM_IN_GPIO msgrequest */
5956 #define MC_CMD_MUM_IN_GPIO_LEN 8
5957 /* MUM cmd header */
5958 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5959 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5960 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4
5961 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4
5962 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
5963 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8
5964 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
5965 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
5966 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
5967 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
5968 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
5969 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
5971 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */
5972 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8
5973 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5974 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5975 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
5976 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
5978 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */
5979 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16
5980 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5981 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5982 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
5983 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
5984 /* The first 32-bit word to be written to the GPIO OUT register. */
5985 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8
5986 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
5987 /* The second 32-bit word to be written to the GPIO OUT register. */
5988 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12
5989 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
5991 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */
5992 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8
5993 /* MC_CMD_MUM_IN_CMD_OFST 0 */
5994 /* MC_CMD_MUM_IN_CMD_LEN 4 */
5995 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
5996 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
5998 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */
5999 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16
6000 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6001 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6002 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
6003 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
6004 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
6005 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8
6006 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
6007 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
6008 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12
6009 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
6011 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */
6012 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8
6013 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6014 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6015 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
6016 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
6018 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */
6019 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8
6020 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6021 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6022 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
6023 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
6024 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8
6025 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8
6026 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
6027 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
6028 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
6029 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
6030 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16
6031 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8
6033 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */
6034 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8
6035 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6036 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6037 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
6038 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
6040 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */
6041 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8
6042 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6043 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6044 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
6045 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
6046 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24
6047 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8
6049 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */
6050 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8
6051 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6052 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6053 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
6054 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
6055 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24
6056 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8
6058 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */
6059 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8
6060 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6061 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6062 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
6063 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
6064 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24
6065 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8
6067 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */
6068 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8
6069 /* MUM cmd header */
6070 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6071 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6072 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
6073 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
6074 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
6075 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8
6076 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8
6077 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8
6079 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */
6080 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12
6081 /* MUM cmd header */
6082 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6083 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6084 /* Bit-mask of clocks to be programmed */
6085 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
6086 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
6087 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
6088 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
6089 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
6090 /* Control flags for clock programming */
6091 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8
6092 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
6093 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
6094 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
6095 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
6096 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
6097 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2
6098 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
6100 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */
6101 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8
6102 /* MUM cmd header */
6103 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6104 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6105 /* Enable/Disable FPGA config from flash */
6106 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
6107 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
6109 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */
6110 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
6111 /* MUM cmd header */
6112 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6113 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6115 /* MC_CMD_MUM_IN_QSFP msgrequest */
6116 #define MC_CMD_MUM_IN_QSFP_LEN 12
6117 /* MUM cmd header */
6118 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6119 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6120 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4
6121 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4
6122 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
6123 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
6124 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
6125 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
6126 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
6127 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
6128 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
6129 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
6130 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8
6131 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4
6133 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */
6134 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16
6135 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6136 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6137 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
6138 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
6139 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8
6140 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
6141 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12
6142 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
6144 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */
6145 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24
6146 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6147 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6148 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
6149 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
6150 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8
6151 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
6152 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12
6153 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
6154 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16
6155 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
6156 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20
6157 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
6159 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */
6160 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12
6161 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6162 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6163 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
6164 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
6165 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8
6166 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
6168 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */
6169 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16
6170 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6171 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6172 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
6173 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
6174 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8
6175 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
6176 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12
6177 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
6179 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */
6180 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12
6181 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6182 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6183 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
6184 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
6185 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8
6186 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
6188 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */
6189 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12
6190 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6191 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6192 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
6193 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
6194 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8
6195 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
6197 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */
6198 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
6199 /* MUM cmd header */
6200 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6201 /* MC_CMD_MUM_IN_CMD_LEN 4 */
6203 /* MC_CMD_MUM_OUT msgresponse */
6204 #define MC_CMD_MUM_OUT_LEN 0
6206 /* MC_CMD_MUM_OUT_NULL msgresponse */
6207 #define MC_CMD_MUM_OUT_NULL_LEN 0
6209 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */
6210 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12
6211 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
6212 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
6213 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
6214 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
6215 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
6216 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
6218 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
6219 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
6220 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
6221 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
6223 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
6224 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
6225 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
6226 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252
6228 /* MC_CMD_MUM_OUT_READ msgresponse */
6229 #define MC_CMD_MUM_OUT_READ_LENMIN 4
6230 #define MC_CMD_MUM_OUT_READ_LENMAX 252
6231 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
6232 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
6233 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
6234 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
6235 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63
6237 /* MC_CMD_MUM_OUT_WRITE msgresponse */
6238 #define MC_CMD_MUM_OUT_WRITE_LEN 0
6240 /* MC_CMD_MUM_OUT_LOG msgresponse */
6241 #define MC_CMD_MUM_OUT_LOG_LEN 0
6243 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */
6244 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
6246 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */
6247 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8
6248 /* The first 32-bit word read from the GPIO IN register. */
6249 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
6250 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
6251 /* The second 32-bit word read from the GPIO IN register. */
6252 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
6253 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
6255 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */
6256 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
6258 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */
6259 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8
6260 /* The first 32-bit word read from the GPIO OUT register. */
6261 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
6262 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
6263 /* The second 32-bit word read from the GPIO OUT register. */
6264 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
6265 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
6267 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */
6268 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
6270 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */
6271 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8
6272 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
6273 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
6274 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
6275 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
6277 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */
6278 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
6279 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
6280 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
6282 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */
6283 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
6285 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */
6286 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
6288 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */
6289 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
6291 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */
6292 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
6293 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
6294 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
6295 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
6296 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
6297 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
6298 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63
6299 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
6300 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16
6301 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16
6302 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8
6303 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24
6304 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8
6306 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */
6307 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
6308 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
6309 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
6311 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */
6312 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
6314 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */
6315 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
6316 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
6317 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
6319 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */
6320 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
6322 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */
6323 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8
6324 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
6325 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
6326 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
6327 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
6328 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
6329 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
6330 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
6331 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
6333 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */
6334 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
6335 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
6336 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
6338 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */
6339 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5
6340 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
6341 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
6343 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
6344 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
6345 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
6346 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
6347 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
6348 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248
6350 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */
6351 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8
6352 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
6353 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
6354 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
6355 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
6357 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */
6358 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
6359 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
6360 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
6362 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */
6363 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24
6364 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
6365 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
6366 /* Discrete (soldered) DDR resistor strap info */
6367 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
6368 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
6369 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
6370 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16
6371 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16
6372 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16
6373 /* Number of SODIMM info records */
6374 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
6375 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
6376 /* Array of SODIMM info records */
6377 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
6378 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
6379 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
6380 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
6381 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
6382 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
6383 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
6384 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8
6385 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
6386 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
6387 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */
6388 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
6389 /* enum: Total number of SODIMM banks */
6390 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
6391 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8
6392 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8
6393 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16
6394 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
6395 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20
6396 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
6397 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
6398 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
6399 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
6400 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
6401 /* enum: Values 5-15 are reserved for future usage */
6402 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
6403 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24
6404 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8
6405 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32
6406 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16
6407 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48
6408 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
6409 /* enum: No module present */
6410 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
6411 /* enum: Module present supported and powered on */
6412 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
6413 /* enum: Module present but bad type */
6414 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
6415 /* enum: Module present but incompatible voltage */
6416 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
6417 /* enum: Module present but unknown SPD */
6418 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
6419 /* enum: Module present but slot cannot support it */
6420 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
6421 /* enum: Modules may or may not be present, but cannot establish contact by I2C
6423 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
6424 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
6425 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
6427 /* MC_CMD_RESOURCE_SPECIFIER enum */
6429 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
6431 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe
6433 /* EVB_PORT_ID structuredef */
6434 #define EVB_PORT_ID_LEN 4
6435 #define EVB_PORT_ID_PORT_ID_OFST 0
6436 #define EVB_PORT_ID_PORT_ID_LEN 4
6437 /* enum: An invalid port handle. */
6438 #define EVB_PORT_ID_NULL 0x0
6439 /* enum: The port assigned to this function.. */
6440 #define EVB_PORT_ID_ASSIGNED 0x1000000
6441 /* enum: External network port 0 */
6442 #define EVB_PORT_ID_MAC0 0x2000000
6443 /* enum: External network port 1 */
6444 #define EVB_PORT_ID_MAC1 0x2000001
6445 /* enum: External network port 2 */
6446 #define EVB_PORT_ID_MAC2 0x2000002
6447 /* enum: External network port 3 */
6448 #define EVB_PORT_ID_MAC3 0x2000003
6449 #define EVB_PORT_ID_PORT_ID_LBN 0
6450 #define EVB_PORT_ID_PORT_ID_WIDTH 32
6452 /* EVB_VLAN_TAG structuredef */
6453 #define EVB_VLAN_TAG_LEN 2
6454 /* The VLAN tag value */
6455 #define EVB_VLAN_TAG_VLAN_ID_LBN 0
6456 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12
6457 #define EVB_VLAN_TAG_MODE_LBN 12
6458 #define EVB_VLAN_TAG_MODE_WIDTH 4
6459 /* enum: Insert the VLAN. */
6460 #define EVB_VLAN_TAG_INSERT 0x0
6461 /* enum: Replace the VLAN if already present. */
6462 #define EVB_VLAN_TAG_REPLACE 0x1
6464 /* BUFTBL_ENTRY structuredef */
6465 #define BUFTBL_ENTRY_LEN 12
6467 #define BUFTBL_ENTRY_OID_OFST 0
6468 #define BUFTBL_ENTRY_OID_LEN 2
6469 #define BUFTBL_ENTRY_OID_LBN 0
6470 #define BUFTBL_ENTRY_OID_WIDTH 16
6471 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
6472 #define BUFTBL_ENTRY_PGSZ_OFST 2
6473 #define BUFTBL_ENTRY_PGSZ_LEN 2
6474 #define BUFTBL_ENTRY_PGSZ_LBN 16
6475 #define BUFTBL_ENTRY_PGSZ_WIDTH 16
6476 /* the raw 64-bit address field from the SMC, not adjusted for page size */
6477 #define BUFTBL_ENTRY_RAWADDR_OFST 4
6478 #define BUFTBL_ENTRY_RAWADDR_LEN 8
6479 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
6480 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
6481 #define BUFTBL_ENTRY_RAWADDR_LBN 32
6482 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64
6484 /* NVRAM_PARTITION_TYPE structuredef */
6485 #define NVRAM_PARTITION_TYPE_LEN 2
6486 #define NVRAM_PARTITION_TYPE_ID_OFST 0
6487 #define NVRAM_PARTITION_TYPE_ID_LEN 2
6488 /* enum: Primary MC firmware partition */
6489 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
6490 /* enum: Secondary MC firmware partition */
6491 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
6492 /* enum: Expansion ROM partition */
6493 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
6494 /* enum: Static configuration TLV partition */
6495 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
6496 /* enum: Dynamic configuration TLV partition */
6497 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
6498 /* enum: Expansion ROM configuration data for port 0 */
6499 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
6500 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
6501 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
6502 /* enum: Expansion ROM configuration data for port 1 */
6503 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
6504 /* enum: Expansion ROM configuration data for port 2 */
6505 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
6506 /* enum: Expansion ROM configuration data for port 3 */
6507 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
6508 /* enum: Non-volatile log output partition */
6509 #define NVRAM_PARTITION_TYPE_LOG 0x700
6510 /* enum: Non-volatile log output of second core on dual-core device */
6511 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
6512 /* enum: Device state dump output partition */
6513 #define NVRAM_PARTITION_TYPE_DUMP 0x800
6514 /* enum: Application license key storage partition */
6515 #define NVRAM_PARTITION_TYPE_LICENSE 0x900
6516 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
6517 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
6518 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
6519 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
6520 /* enum: Primary FPGA partition */
6521 #define NVRAM_PARTITION_TYPE_FPGA 0xb00
6522 /* enum: Secondary FPGA partition */
6523 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
6524 /* enum: FC firmware partition */
6525 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
6526 /* enum: FC License partition */
6527 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
6528 /* enum: Non-volatile log output partition for FC */
6529 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
6530 /* enum: MUM firmware partition */
6531 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
6532 /* enum: SUC firmware partition (this is intentionally an alias of
6535 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
6536 /* enum: MUM Non-volatile log output partition. */
6537 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
6538 /* enum: MUM Application table partition. */
6539 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
6540 /* enum: MUM boot rom partition. */
6541 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
6542 /* enum: MUM production signatures & calibration rom partition. */
6543 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
6544 /* enum: MUM user signatures & calibration rom partition. */
6545 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
6546 /* enum: MUM fuses and lockbits partition. */
6547 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
6548 /* enum: UEFI expansion ROM if separate from PXE */
6549 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
6550 /* enum: Used by the expansion ROM for logging */
6551 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
6552 /* enum: Used for XIP code of shmbooted images */
6553 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
6554 /* enum: Spare partition 2 */
6555 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
6556 /* enum: Manufacturing partition. Used during manufacture to pass information
6557 * between XJTAG and Manftest.
6559 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
6560 /* enum: Spare partition 4 */
6561 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
6562 /* enum: Spare partition 5 */
6563 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
6564 /* enum: Partition for reporting MC status. See mc_flash_layout.h
6565 * medford_mc_status_hdr_t for layout on Medford.
6567 #define NVRAM_PARTITION_TYPE_STATUS 0x1600
6568 /* enum: Spare partition 13 */
6569 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
6570 /* enum: Spare partition 14 */
6571 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
6572 /* enum: Spare partition 15 */
6573 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
6574 /* enum: Spare partition 16 */
6575 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
6576 /* enum: Factory defaults for dynamic configuration */
6577 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
6578 /* enum: Factory defaults for expansion ROM configuration */
6579 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
6580 /* enum: Start of reserved value range (firmware may use for any purpose) */
6581 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
6582 /* enum: End of reserved value range (firmware may use for any purpose) */
6583 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
6584 /* enum: Recovery partition map (provided if real map is missing or corrupt) */
6585 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
6586 /* enum: Partition map (real map as stored in flash) */
6587 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
6588 #define NVRAM_PARTITION_TYPE_ID_LBN 0
6589 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16
6591 /* LICENSED_APP_ID structuredef */
6592 #define LICENSED_APP_ID_LEN 4
6593 #define LICENSED_APP_ID_ID_OFST 0
6594 #define LICENSED_APP_ID_ID_LEN 4
6595 /* enum: OpenOnload */
6596 #define LICENSED_APP_ID_ONLOAD 0x1
6597 /* enum: PTP timestamping */
6598 #define LICENSED_APP_ID_PTP 0x2
6599 /* enum: SolarCapture Pro */
6600 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
6601 /* enum: SolarSecure filter engine */
6602 #define LICENSED_APP_ID_SOLARSECURE 0x8
6603 /* enum: Performance monitor */
6604 #define LICENSED_APP_ID_PERF_MONITOR 0x10
6605 /* enum: SolarCapture Live */
6606 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
6607 /* enum: Capture SolarSystem */
6608 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
6609 /* enum: Network Access Control */
6610 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
6611 /* enum: TCP Direct */
6612 #define LICENSED_APP_ID_TCP_DIRECT 0x100
6613 /* enum: Low Latency */
6614 #define LICENSED_APP_ID_LOW_LATENCY 0x200
6615 /* enum: SolarCapture Tap */
6616 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
6617 /* enum: Capture SolarSystem 40G */
6618 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
6619 /* enum: Capture SolarSystem 1G */
6620 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
6621 #define LICENSED_APP_ID_ID_LBN 0
6622 #define LICENSED_APP_ID_ID_WIDTH 32
6624 /* LICENSED_FEATURES structuredef */
6625 #define LICENSED_FEATURES_LEN 8
6626 /* Bitmask of licensed firmware features */
6627 #define LICENSED_FEATURES_MASK_OFST 0
6628 #define LICENSED_FEATURES_MASK_LEN 8
6629 #define LICENSED_FEATURES_MASK_LO_OFST 0
6630 #define LICENSED_FEATURES_MASK_HI_OFST 4
6631 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
6632 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
6633 #define LICENSED_FEATURES_PIO_LBN 1
6634 #define LICENSED_FEATURES_PIO_WIDTH 1
6635 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2
6636 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
6637 #define LICENSED_FEATURES_CLOCK_LBN 3
6638 #define LICENSED_FEATURES_CLOCK_WIDTH 1
6639 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
6640 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
6641 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5
6642 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
6643 #define LICENSED_FEATURES_RX_SNIFF_LBN 6
6644 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1
6645 #define LICENSED_FEATURES_TX_SNIFF_LBN 7
6646 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1
6647 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8
6648 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
6649 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9
6650 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
6651 #define LICENSED_FEATURES_MASK_LBN 0
6652 #define LICENSED_FEATURES_MASK_WIDTH 64
6654 /* LICENSED_V3_APPS structuredef */
6655 #define LICENSED_V3_APPS_LEN 8
6656 /* Bitmask of licensed applications */
6657 #define LICENSED_V3_APPS_MASK_OFST 0
6658 #define LICENSED_V3_APPS_MASK_LEN 8
6659 #define LICENSED_V3_APPS_MASK_LO_OFST 0
6660 #define LICENSED_V3_APPS_MASK_HI_OFST 4
6661 #define LICENSED_V3_APPS_ONLOAD_LBN 0
6662 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1
6663 #define LICENSED_V3_APPS_PTP_LBN 1
6664 #define LICENSED_V3_APPS_PTP_WIDTH 1
6665 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2
6666 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
6667 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3
6668 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
6669 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4
6670 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
6671 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5
6672 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
6673 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6
6674 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
6675 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7
6676 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
6677 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8
6678 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
6679 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9
6680 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
6681 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10
6682 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
6683 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11
6684 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
6685 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12
6686 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
6687 #define LICENSED_V3_APPS_MASK_LBN 0
6688 #define LICENSED_V3_APPS_MASK_WIDTH 64
6690 /* LICENSED_V3_FEATURES structuredef */
6691 #define LICENSED_V3_FEATURES_LEN 8
6692 /* Bitmask of licensed firmware features */
6693 #define LICENSED_V3_FEATURES_MASK_OFST 0
6694 #define LICENSED_V3_FEATURES_MASK_LEN 8
6695 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0
6696 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4
6697 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
6698 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
6699 #define LICENSED_V3_FEATURES_PIO_LBN 1
6700 #define LICENSED_V3_FEATURES_PIO_WIDTH 1
6701 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
6702 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
6703 #define LICENSED_V3_FEATURES_CLOCK_LBN 3
6704 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1
6705 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
6706 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
6707 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
6708 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
6709 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
6710 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
6711 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
6712 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
6713 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
6714 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
6715 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
6716 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
6717 #define LICENSED_V3_FEATURES_MASK_LBN 0
6718 #define LICENSED_V3_FEATURES_MASK_WIDTH 64
6720 /* TX_TIMESTAMP_EVENT structuredef */
6721 #define TX_TIMESTAMP_EVENT_LEN 6
6722 /* lower 16 bits of timestamp data */
6723 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
6724 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2
6725 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
6726 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16
6727 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp
6729 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
6730 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
6731 /* enum: This is a TX completion event, not a timestamp */
6732 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
6733 /* enum: This is the low part of a TX timestamp event */
6734 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
6735 /* enum: This is the high part of a TX timestamp event */
6736 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
6737 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
6738 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
6739 /* upper 16 bits of timestamp data */
6740 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
6741 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2
6742 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32
6743 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16
6745 /* RSS_MODE structuredef */
6746 #define RSS_MODE_LEN 1
6747 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
6748 * be considered as 4 bits selecting which fields are included in the hash. (A
6749 * value 0 effectively disables RSS spreading for the packet type.) The YAML
6750 * generation tools require this structure to be a whole number of bytes wide,
6751 * but only 4 bits are relevant.
6753 #define RSS_MODE_HASH_SELECTOR_OFST 0
6754 #define RSS_MODE_HASH_SELECTOR_LEN 1
6755 #define RSS_MODE_HASH_SRC_ADDR_LBN 0
6756 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1
6757 #define RSS_MODE_HASH_DST_ADDR_LBN 1
6758 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1
6759 #define RSS_MODE_HASH_SRC_PORT_LBN 2
6760 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1
6761 #define RSS_MODE_HASH_DST_PORT_LBN 3
6762 #define RSS_MODE_HASH_DST_PORT_WIDTH 1
6763 #define RSS_MODE_HASH_SELECTOR_LBN 0
6764 #define RSS_MODE_HASH_SELECTOR_WIDTH 8
6766 /* CTPIO_STATS_MAP structuredef */
6767 #define CTPIO_STATS_MAP_LEN 4
6768 /* The (function relative) VI number */
6769 #define CTPIO_STATS_MAP_VI_OFST 0
6770 #define CTPIO_STATS_MAP_VI_LEN 2
6771 #define CTPIO_STATS_MAP_VI_LBN 0
6772 #define CTPIO_STATS_MAP_VI_WIDTH 16
6773 /* The target bucket for the VI */
6774 #define CTPIO_STATS_MAP_BUCKET_OFST 2
6775 #define CTPIO_STATS_MAP_BUCKET_LEN 2
6776 #define CTPIO_STATS_MAP_BUCKET_LBN 16
6777 #define CTPIO_STATS_MAP_BUCKET_WIDTH 16
6780 /***********************************/
6782 * Get a dump of the MCPU registers
6784 #define MC_CMD_READ_REGS 0x50
6785 #undef MC_CMD_0x50_PRIVILEGE_CTG
6787 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
6789 /* MC_CMD_READ_REGS_IN msgrequest */
6790 #define MC_CMD_READ_REGS_IN_LEN 0
6792 /* MC_CMD_READ_REGS_OUT msgresponse */
6793 #define MC_CMD_READ_REGS_OUT_LEN 308
6794 /* Whether the corresponding register entry contains a valid value */
6795 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0
6796 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16
6797 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
6800 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16
6801 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4
6802 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73
6805 /***********************************/
6807 * Set up an event queue according to the supplied parameters. The IN arguments
6808 * end with an address for each 4k of host memory required to back the EVQ.
6810 #define MC_CMD_INIT_EVQ 0x80
6811 #undef MC_CMD_0x80_PRIVILEGE_CTG
6813 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6815 /* MC_CMD_INIT_EVQ_IN msgrequest */
6816 #define MC_CMD_INIT_EVQ_IN_LENMIN 44
6817 #define MC_CMD_INIT_EVQ_IN_LENMAX 548
6818 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
6819 /* Size, in entries */
6820 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
6821 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
6822 /* Desired instance. Must be set to a specific instance, which is a function
6823 * local queue index.
6825 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
6826 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
6827 /* The initial timer value. The load value is ignored if the timer mode is DIS.
6829 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
6830 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
6831 /* The reload value is ignored in one-shot modes */
6832 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
6833 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
6835 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
6836 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
6837 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
6838 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
6839 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
6840 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
6841 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
6842 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
6843 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
6844 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
6845 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
6846 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
6847 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
6848 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
6849 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
6850 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
6851 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
6852 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
6853 /* enum: Disabled */
6854 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
6855 /* enum: Immediate */
6856 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
6857 /* enum: Triggered */
6858 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
6859 /* enum: Hold-off */
6860 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
6861 /* Target EVQ for wakeups if in wakeup mode. */
6862 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
6863 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
6864 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
6865 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
6868 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
6869 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
6870 /* Event Counter Mode. */
6871 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
6872 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
6873 /* enum: Disabled */
6874 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
6875 /* enum: Disabled */
6876 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
6877 /* enum: Disabled */
6878 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
6879 /* enum: Disabled */
6880 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
6881 /* Event queue packet count threshold. */
6882 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
6883 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
6884 /* 64-bit address of 4k of 4k-aligned host memory buffer */
6885 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
6886 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
6887 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
6888 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
6889 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
6890 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
6892 /* MC_CMD_INIT_EVQ_OUT msgresponse */
6893 #define MC_CMD_INIT_EVQ_OUT_LEN 4
6894 /* Only valid if INTRFLAG was true */
6895 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
6896 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
6898 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */
6899 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
6900 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
6901 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
6902 /* Size, in entries */
6903 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
6904 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
6905 /* Desired instance. Must be set to a specific instance, which is a function
6906 * local queue index.
6908 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
6909 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
6910 /* The initial timer value. The load value is ignored if the timer mode is DIS.
6912 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8
6913 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
6914 /* The reload value is ignored in one-shot modes */
6915 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12
6916 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
6918 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
6919 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
6920 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
6921 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
6922 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
6923 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
6924 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
6925 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
6926 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
6927 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
6928 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
6929 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
6930 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
6931 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
6932 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
6933 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
6934 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
6935 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
6936 /* enum: All initialisation flags specified by host. */
6937 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
6938 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
6939 * over-ridden by firmware based on licenses and firmware variant in order to
6940 * provide the lowest latency achievable. See
6941 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
6943 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
6944 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
6945 * over-ridden by firmware based on licenses and firmware variant in order to
6946 * provide the best throughput achievable. See
6947 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
6949 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
6950 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
6951 * firmware based on licenses and firmware variant. See
6952 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
6954 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
6955 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
6956 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
6957 /* enum: Disabled */
6958 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
6959 /* enum: Immediate */
6960 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
6961 /* enum: Triggered */
6962 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
6963 /* enum: Hold-off */
6964 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
6965 /* Target EVQ for wakeups if in wakeup mode. */
6966 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24
6967 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
6968 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
6969 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
6972 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24
6973 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
6974 /* Event Counter Mode. */
6975 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28
6976 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
6977 /* enum: Disabled */
6978 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
6979 /* enum: Disabled */
6980 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
6981 /* enum: Disabled */
6982 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
6983 /* enum: Disabled */
6984 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
6985 /* Event queue packet count threshold. */
6986 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32
6987 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
6988 /* 64-bit address of 4k of 4k-aligned host memory buffer */
6989 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
6990 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
6991 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
6992 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
6993 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
6994 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
6996 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
6997 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8
6998 /* Only valid if INTRFLAG was true */
6999 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
7000 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
7001 /* Actual configuration applied on the card */
7002 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
7003 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
7004 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
7005 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
7006 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
7007 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
7008 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
7009 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
7010 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
7011 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
7013 /* QUEUE_CRC_MODE structuredef */
7014 #define QUEUE_CRC_MODE_LEN 1
7015 #define QUEUE_CRC_MODE_MODE_LBN 0
7016 #define QUEUE_CRC_MODE_MODE_WIDTH 4
7018 #define QUEUE_CRC_MODE_NONE 0x0
7019 /* enum: CRC Fiber channel over ethernet. */
7020 #define QUEUE_CRC_MODE_FCOE 0x1
7021 /* enum: CRC (digest) iSCSI header only. */
7022 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2
7023 /* enum: CRC (digest) iSCSI header and payload. */
7024 #define QUEUE_CRC_MODE_ISCSI 0x3
7025 /* enum: CRC Fiber channel over IP over ethernet. */
7026 #define QUEUE_CRC_MODE_FCOIPOE 0x4
7027 /* enum: CRC MPA. */
7028 #define QUEUE_CRC_MODE_MPA 0x5
7029 #define QUEUE_CRC_MODE_SPARE_LBN 4
7030 #define QUEUE_CRC_MODE_SPARE_WIDTH 4
7033 /***********************************/
7035 * set up a receive queue according to the supplied parameters. The IN
7036 * arguments end with an address for each 4k of host memory required to back
7039 #define MC_CMD_INIT_RXQ 0x81
7040 #undef MC_CMD_0x81_PRIVILEGE_CTG
7042 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7044 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version
7047 #define MC_CMD_INIT_RXQ_IN_LENMIN 36
7048 #define MC_CMD_INIT_RXQ_IN_LENMAX 252
7049 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
7050 /* Size, in entries */
7051 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
7052 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
7053 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
7055 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
7056 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
7057 /* The value to put in the event data. Check hardware spec. for valid range. */
7058 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
7059 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
7060 /* Desired instance. Must be set to a specific instance, which is a function
7061 * local queue index.
7063 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
7064 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
7065 /* There will be more flags here. */
7066 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
7067 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
7068 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
7069 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
7070 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
7071 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
7072 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
7073 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
7074 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
7075 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
7076 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
7077 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
7078 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
7079 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
7080 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
7081 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
7082 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
7083 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
7084 /* Owner ID to use if in buffer mode (zero if physical) */
7085 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
7086 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
7087 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7088 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
7089 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
7090 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7091 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
7092 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
7093 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
7094 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
7095 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
7096 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
7098 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
7101 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544
7102 /* Size, in entries */
7103 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
7104 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
7105 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
7107 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
7108 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
7109 /* The value to put in the event data. Check hardware spec. for valid range. */
7110 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
7111 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
7112 /* Desired instance. Must be set to a specific instance, which is a function
7113 * local queue index.
7115 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
7116 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
7117 /* There will be more flags here. */
7118 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
7119 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
7120 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
7121 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
7122 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
7123 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
7124 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
7125 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
7126 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
7127 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
7128 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
7129 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
7130 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
7131 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
7132 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
7133 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
7134 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
7135 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
7136 /* enum: One packet per descriptor (for normal networking) */
7137 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
7138 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
7139 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
7140 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
7141 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
7142 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
7143 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
7144 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
7145 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
7146 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
7147 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
7148 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
7149 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
7150 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
7151 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
7152 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
7153 /* Owner ID to use if in buffer mode (zero if physical) */
7154 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
7155 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
7156 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7157 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24
7158 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
7159 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7160 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
7161 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
7162 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
7163 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
7164 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
7165 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
7166 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
7167 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
7169 /* MC_CMD_INIT_RXQ_OUT msgresponse */
7170 #define MC_CMD_INIT_RXQ_OUT_LEN 0
7172 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
7173 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
7176 /***********************************/
7179 #define MC_CMD_INIT_TXQ 0x82
7180 #undef MC_CMD_0x82_PRIVILEGE_CTG
7182 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7184 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version
7187 #define MC_CMD_INIT_TXQ_IN_LENMIN 36
7188 #define MC_CMD_INIT_TXQ_IN_LENMAX 252
7189 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
7190 /* Size, in entries */
7191 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
7192 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
7193 /* The EVQ to send events to. This is an index originally specified to
7196 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
7197 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
7198 /* The value to put in the event data. Check hardware spec. for valid range. */
7199 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
7200 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
7201 /* Desired instance. Must be set to a specific instance, which is a function
7202 * local queue index.
7204 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
7205 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
7206 /* There will be more flags here. */
7207 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
7208 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
7209 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
7210 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
7211 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
7212 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
7213 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
7214 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
7215 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
7216 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
7217 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
7218 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
7219 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
7220 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
7221 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
7222 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
7223 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
7224 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
7225 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
7226 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
7227 /* Owner ID to use if in buffer mode (zero if physical) */
7228 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
7229 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
7230 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7231 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
7232 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
7233 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7234 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
7235 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
7236 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
7237 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
7238 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
7239 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
7241 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
7244 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544
7245 /* Size, in entries */
7246 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
7247 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
7248 /* The EVQ to send events to. This is an index originally specified to
7251 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
7252 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
7253 /* The value to put in the event data. Check hardware spec. for valid range. */
7254 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
7255 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
7256 /* Desired instance. Must be set to a specific instance, which is a function
7257 * local queue index.
7259 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
7260 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
7261 /* There will be more flags here. */
7262 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
7263 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
7264 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
7265 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
7266 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
7267 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
7268 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
7269 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
7270 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
7271 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
7272 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
7273 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
7274 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
7275 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
7276 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
7277 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
7278 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
7279 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
7280 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
7281 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
7282 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
7283 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
7284 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13
7285 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
7286 /* Owner ID to use if in buffer mode (zero if physical) */
7287 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
7288 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
7289 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
7290 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24
7291 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
7292 /* 64-bit address of 4k of 4k-aligned host memory buffer */
7293 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
7294 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
7295 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
7296 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
7297 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
7298 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
7299 /* Flags related to Qbb flow control mode. */
7300 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
7301 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
7302 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
7303 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
7304 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
7305 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
7307 /* MC_CMD_INIT_TXQ_OUT msgresponse */
7308 #define MC_CMD_INIT_TXQ_OUT_LEN 0
7311 /***********************************/
7315 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
7316 * or the operation will fail with EBUSY
7318 #define MC_CMD_FINI_EVQ 0x83
7319 #undef MC_CMD_0x83_PRIVILEGE_CTG
7321 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7323 /* MC_CMD_FINI_EVQ_IN msgrequest */
7324 #define MC_CMD_FINI_EVQ_IN_LEN 4
7325 /* Instance of EVQ to destroy. Should be the same instance as that previously
7326 * passed to INIT_EVQ
7328 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
7329 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
7331 /* MC_CMD_FINI_EVQ_OUT msgresponse */
7332 #define MC_CMD_FINI_EVQ_OUT_LEN 0
7335 /***********************************/
7339 #define MC_CMD_FINI_RXQ 0x84
7340 #undef MC_CMD_0x84_PRIVILEGE_CTG
7342 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7344 /* MC_CMD_FINI_RXQ_IN msgrequest */
7345 #define MC_CMD_FINI_RXQ_IN_LEN 4
7346 /* Instance of RXQ to destroy */
7347 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
7348 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
7350 /* MC_CMD_FINI_RXQ_OUT msgresponse */
7351 #define MC_CMD_FINI_RXQ_OUT_LEN 0
7354 /***********************************/
7358 #define MC_CMD_FINI_TXQ 0x85
7359 #undef MC_CMD_0x85_PRIVILEGE_CTG
7361 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7363 /* MC_CMD_FINI_TXQ_IN msgrequest */
7364 #define MC_CMD_FINI_TXQ_IN_LEN 4
7365 /* Instance of TXQ to destroy */
7366 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
7367 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
7369 /* MC_CMD_FINI_TXQ_OUT msgresponse */
7370 #define MC_CMD_FINI_TXQ_OUT_LEN 0
7373 /***********************************/
7374 /* MC_CMD_DRIVER_EVENT
7375 * Generate an event on an EVQ belonging to the function issuing the command.
7377 #define MC_CMD_DRIVER_EVENT 0x86
7378 #undef MC_CMD_0x86_PRIVILEGE_CTG
7380 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7382 /* MC_CMD_DRIVER_EVENT_IN msgrequest */
7383 #define MC_CMD_DRIVER_EVENT_IN_LEN 12
7384 /* Handle of target EVQ */
7385 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
7386 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
7387 /* Bits 0 - 63 of event */
7388 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
7389 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
7390 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
7391 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
7393 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */
7394 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0
7397 /***********************************/
7399 * Execute an arbitrary MCDI command on behalf of a different function, subject
7400 * to security restrictions. The command to be proxied follows immediately
7401 * afterward in the host buffer (or on the UART). This command supercedes
7402 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
7404 #define MC_CMD_PROXY_CMD 0x5b
7405 #undef MC_CMD_0x5b_PRIVILEGE_CTG
7407 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7409 /* MC_CMD_PROXY_CMD_IN msgrequest */
7410 #define MC_CMD_PROXY_CMD_IN_LEN 4
7411 /* The handle of the target function. */
7412 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
7413 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
7414 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
7415 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
7416 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
7417 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
7418 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
7420 /* MC_CMD_PROXY_CMD_OUT msgresponse */
7421 #define MC_CMD_PROXY_CMD_OUT_LEN 0
7423 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to
7424 * manage proxied requests
7426 #define MC_PROXY_STATUS_BUFFER_LEN 16
7427 /* Handle allocated by the firmware for this proxy transaction */
7428 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
7429 #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4
7430 /* enum: An invalid handle. */
7431 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
7432 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
7433 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32
7434 /* The requesting physical function number */
7435 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4
7436 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2
7437 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32
7438 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16
7439 /* The requesting virtual function number. Set to VF_NULL if the target is a
7442 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6
7443 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2
7444 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48
7445 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16
7446 /* The target function RID. */
7447 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8
7448 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2
7449 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64
7450 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16
7451 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */
7452 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10
7453 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2
7454 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80
7455 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16
7456 /* If a request is authorized rather than carried out by the host, this is the
7457 * elevated privilege mask granted to the requesting function.
7459 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12
7460 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4
7461 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96
7462 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32
7465 /***********************************/
7466 /* MC_CMD_PROXY_CONFIGURE
7467 * Enable/disable authorization of MCDI requests from unprivileged functions by
7468 * a designated admin function
7470 #define MC_CMD_PROXY_CONFIGURE 0x58
7471 #undef MC_CMD_0x58_PRIVILEGE_CTG
7473 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7475 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */
7476 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108
7477 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
7478 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4
7479 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
7480 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1
7481 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7482 * of blocks, each of the size REQUEST_BLOCK_SIZE.
7484 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
7485 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8
7486 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
7487 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8
7488 /* Must be a power of 2 */
7489 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12
7490 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
7491 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7492 * of blocks, each of the size REPLY_BLOCK_SIZE.
7494 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16
7495 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8
7496 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16
7497 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20
7498 /* Must be a power of 2 */
7499 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24
7500 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
7501 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7502 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
7503 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
7505 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28
7506 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8
7507 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28
7508 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32
7509 /* Must be a power of 2, or zero if this buffer is not provided */
7510 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36
7511 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
7512 /* Applies to all three buffers */
7513 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40
7514 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4
7515 /* A bit mask defining which MCDI operations may be proxied */
7516 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44
7517 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64
7519 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */
7520 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112
7521 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
7522 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4
7523 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
7524 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1
7525 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7526 * of blocks, each of the size REQUEST_BLOCK_SIZE.
7528 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
7529 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8
7530 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
7531 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8
7532 /* Must be a power of 2 */
7533 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12
7534 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
7535 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7536 * of blocks, each of the size REPLY_BLOCK_SIZE.
7538 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16
7539 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8
7540 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16
7541 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20
7542 /* Must be a power of 2 */
7543 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24
7544 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
7545 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS
7546 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if
7547 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.
7549 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28
7550 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8
7551 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28
7552 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32
7553 /* Must be a power of 2, or zero if this buffer is not provided */
7554 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36
7555 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
7556 /* Applies to all three buffers */
7557 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40
7558 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4
7559 /* A bit mask defining which MCDI operations may be proxied */
7560 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44
7561 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64
7562 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108
7563 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4
7565 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */
7566 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0
7569 /***********************************/
7570 /* MC_CMD_PROXY_COMPLETE
7571 * Tells FW that a requested proxy operation has either been completed (by
7572 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the
7573 * function that enabled proxying/authorization (by using
7574 * MC_CMD_PROXY_CONFIGURE).
7576 #define MC_CMD_PROXY_COMPLETE 0x5f
7577 #undef MC_CMD_0x5f_PRIVILEGE_CTG
7579 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7581 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */
7582 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12
7583 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0
7584 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4
7585 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4
7586 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4
7587 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply
7588 * is stored in the REPLY_BUFF.
7590 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0
7591 /* enum: The operation has been authorized. The originating function may now
7594 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1
7595 /* enum: The operation has been declined. */
7596 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2
7597 /* enum: The authorization failed because the relevant application did not
7600 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3
7601 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8
7602 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4
7604 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */
7605 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0
7608 /***********************************/
7609 /* MC_CMD_ALLOC_BUFTBL_CHUNK
7610 * Allocate a set of buffer table entries using the specified owner ID. This
7611 * operation allocates the required buffer table entries (and fails if it
7612 * cannot do so). The buffer table entries will initially be zeroed.
7614 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
7615 #undef MC_CMD_0x87_PRIVILEGE_CTG
7617 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
7619 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
7620 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
7621 /* Owner ID to use */
7622 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
7623 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
7624 /* Size of buffer table pages to use, in bytes (note that only a few values are
7625 * legal on any specific hardware).
7627 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
7628 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
7630 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
7631 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
7632 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
7633 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
7634 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
7635 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
7636 /* Buffer table IDs for use in DMA descriptors. */
7637 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
7638 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
7641 /***********************************/
7642 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES
7643 * Reprogram a set of buffer table entries in the specified chunk.
7645 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
7646 #undef MC_CMD_0x88_PRIVILEGE_CTG
7648 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
7650 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
7651 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
7652 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
7653 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
7654 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
7655 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
7657 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
7658 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
7660 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
7661 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
7662 /* Buffer table entry address */
7663 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
7664 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
7665 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
7666 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
7667 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
7668 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
7670 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
7671 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
7674 /***********************************/
7675 /* MC_CMD_FREE_BUFTBL_CHUNK
7677 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
7678 #undef MC_CMD_0x89_PRIVILEGE_CTG
7680 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
7682 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
7683 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
7684 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
7685 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
7687 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
7688 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
7691 /***********************************/
7693 * Multiplexed MCDI call for filter operations
7695 #define MC_CMD_FILTER_OP 0x8a
7696 #undef MC_CMD_0x8a_PRIVILEGE_CTG
7698 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7700 /* MC_CMD_FILTER_OP_IN msgrequest */
7701 #define MC_CMD_FILTER_OP_IN_LEN 108
7702 /* identifies the type of operation requested */
7703 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
7704 #define MC_CMD_FILTER_OP_IN_OP_LEN 4
7705 /* enum: single-recipient filter insert */
7706 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
7707 /* enum: single-recipient filter remove */
7708 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
7709 /* enum: multi-recipient filter subscribe */
7710 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
7711 /* enum: multi-recipient filter unsubscribe */
7712 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
7713 /* enum: replace one recipient with another (warning - the filter handle may
7716 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
7717 /* filter handle (for remove / unsubscribe operations) */
7718 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
7719 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
7720 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
7721 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
7722 /* The port ID associated with the v-adaptor which should contain this filter.
7724 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
7725 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
7726 /* fields to include in match criteria */
7727 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
7728 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
7729 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
7730 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
7731 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
7732 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
7733 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
7734 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
7735 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
7736 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
7737 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
7738 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
7739 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
7740 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
7741 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
7742 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
7743 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
7744 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
7745 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
7746 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
7747 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
7748 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
7749 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
7750 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
7751 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
7752 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
7753 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
7754 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
7755 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
7756 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
7757 /* receive destination */
7758 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
7759 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
7760 /* enum: drop packets */
7761 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
7762 /* enum: receive to host */
7763 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
7764 /* enum: receive to MC */
7765 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
7766 /* enum: loop back to TXDP 0 */
7767 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
7768 /* enum: loop back to TXDP 1 */
7769 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
7770 /* receive queue handle (for multiple queue modes, this is the base queue) */
7771 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
7772 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
7774 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
7775 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
7776 /* enum: receive to just the specified queue */
7777 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
7778 /* enum: receive to multiple queues using RSS context */
7779 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
7780 /* enum: receive to multiple queues using .1p mapping */
7781 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
7782 /* enum: install a filter entry that will never match; for test purposes only
7784 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
7785 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
7786 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
7787 * MC_CMD_DOT1P_MAPPING_ALLOC.
7789 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
7790 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
7791 /* transmit domain (reserved; set to 0) */
7792 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
7793 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
7794 /* transmit destination (either set the MAC and/or PM bits for explicit
7795 * control, or set this field to TX_DEST_DEFAULT for sensible default
7798 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
7799 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
7800 /* enum: request default behaviour (based on filter type) */
7801 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
7802 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
7803 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
7804 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
7805 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
7806 /* source MAC address to match (as bytes in network order) */
7807 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
7808 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
7809 /* source port to match (as bytes in network order) */
7810 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
7811 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
7812 /* destination MAC address to match (as bytes in network order) */
7813 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
7814 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
7815 /* destination port to match (as bytes in network order) */
7816 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
7817 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
7818 /* Ethernet type to match (as bytes in network order) */
7819 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
7820 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
7821 /* Inner VLAN tag to match (as bytes in network order) */
7822 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
7823 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
7824 /* Outer VLAN tag to match (as bytes in network order) */
7825 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
7826 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
7827 /* IP protocol to match (in low byte; set high byte to 0) */
7828 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
7829 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
7830 /* Firmware defined register 0 to match (reserved; set to 0) */
7831 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
7832 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
7833 /* Firmware defined register 1 to match (reserved; set to 0) */
7834 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
7835 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
7836 /* source IP address to match (as bytes in network order; set last 12 bytes to
7837 * 0 for IPv4 address)
7839 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
7840 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
7841 /* destination IP address to match (as bytes in network order; set last 12
7842 * bytes to 0 for IPv4 address)
7844 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
7845 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
7847 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to
7848 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is
7849 * supported on Medford only).
7851 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172
7852 /* identifies the type of operation requested */
7853 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
7854 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
7855 /* Enum values, see field(s): */
7856 /* MC_CMD_FILTER_OP_IN/OP */
7857 /* filter handle (for remove / unsubscribe operations) */
7858 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
7859 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
7860 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
7861 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
7862 /* The port ID associated with the v-adaptor which should contain this filter.
7864 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
7865 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
7866 /* fields to include in match criteria */
7867 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
7868 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
7869 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
7870 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
7871 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
7872 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
7873 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
7874 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
7875 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
7876 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
7877 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
7878 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
7879 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
7880 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
7881 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
7882 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
7883 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
7884 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
7885 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
7886 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
7887 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
7888 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
7889 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
7890 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
7891 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
7892 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
7893 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
7894 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
7895 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
7896 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
7897 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
7898 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
7899 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
7900 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
7901 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
7902 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
7903 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
7904 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
7905 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
7906 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
7907 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
7908 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
7909 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
7910 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
7911 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
7912 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
7913 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
7914 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
7915 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
7916 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
7917 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
7918 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
7919 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
7920 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
7921 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
7922 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
7923 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
7924 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
7925 /* receive destination */
7926 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
7927 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
7928 /* enum: drop packets */
7929 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
7930 /* enum: receive to host */
7931 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
7932 /* enum: receive to MC */
7933 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
7934 /* enum: loop back to TXDP 0 */
7935 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
7936 /* enum: loop back to TXDP 1 */
7937 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
7938 /* receive queue handle (for multiple queue modes, this is the base queue) */
7939 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
7940 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
7942 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
7943 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
7944 /* enum: receive to just the specified queue */
7945 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
7946 /* enum: receive to multiple queues using RSS context */
7947 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
7948 /* enum: receive to multiple queues using .1p mapping */
7949 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
7950 /* enum: install a filter entry that will never match; for test purposes only
7952 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
7953 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
7954 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
7955 * MC_CMD_DOT1P_MAPPING_ALLOC.
7957 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32
7958 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
7959 /* transmit domain (reserved; set to 0) */
7960 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36
7961 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
7962 /* transmit destination (either set the MAC and/or PM bits for explicit
7963 * control, or set this field to TX_DEST_DEFAULT for sensible default
7966 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
7967 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
7968 /* enum: request default behaviour (based on filter type) */
7969 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
7970 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
7971 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
7972 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
7973 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
7974 /* source MAC address to match (as bytes in network order) */
7975 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44
7976 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6
7977 /* source port to match (as bytes in network order) */
7978 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50
7979 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2
7980 /* destination MAC address to match (as bytes in network order) */
7981 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52
7982 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6
7983 /* destination port to match (as bytes in network order) */
7984 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58
7985 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2
7986 /* Ethernet type to match (as bytes in network order) */
7987 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60
7988 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2
7989 /* Inner VLAN tag to match (as bytes in network order) */
7990 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62
7991 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2
7992 /* Outer VLAN tag to match (as bytes in network order) */
7993 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64
7994 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2
7995 /* IP protocol to match (in low byte; set high byte to 0) */
7996 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66
7997 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2
7998 /* Firmware defined register 0 to match (reserved; set to 0) */
7999 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68
8000 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
8001 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
8002 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
8003 * VXLAN/NVGRE, or 1 for Geneve)
8005 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
8006 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
8007 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
8008 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
8009 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
8010 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
8011 /* enum: Match VXLAN traffic with this VNI */
8012 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
8013 /* enum: Match Geneve traffic with this VNI */
8014 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
8015 /* enum: Reserved for experimental development use */
8016 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
8017 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
8018 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
8019 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
8020 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
8021 /* enum: Match NVGRE traffic with this VSID */
8022 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
8023 /* source IP address to match (as bytes in network order; set last 12 bytes to
8024 * 0 for IPv4 address)
8026 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76
8027 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16
8028 /* destination IP address to match (as bytes in network order; set last 12
8029 * bytes to 0 for IPv4 address)
8031 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92
8032 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16
8033 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
8036 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108
8037 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6
8038 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
8039 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114
8040 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2
8041 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
8044 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116
8045 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6
8046 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network
8049 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122
8050 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2
8051 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
8053 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124
8054 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2
8055 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
8057 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126
8058 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2
8059 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
8061 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128
8062 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2
8063 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
8066 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130
8067 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2
8068 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
8071 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132
8072 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
8073 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
8076 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136
8077 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
8078 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
8079 * order; set last 12 bytes to 0 for IPv4 address)
8081 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140
8082 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16
8083 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
8084 * order; set last 12 bytes to 0 for IPv4 address)
8086 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
8087 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
8089 /* MC_CMD_FILTER_OP_OUT msgresponse */
8090 #define MC_CMD_FILTER_OP_OUT_LEN 12
8091 /* identifies the type of operation requested */
8092 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
8093 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4
8094 /* Enum values, see field(s): */
8095 /* MC_CMD_FILTER_OP_IN/OP */
8096 /* Returned filter handle (for insert / subscribe operations). Note that these
8097 * handles should be considered opaque to the host, although a value of
8098 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
8100 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
8101 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
8102 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
8103 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
8104 /* enum: guaranteed invalid filter handle (low 32 bits) */
8105 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
8106 /* enum: guaranteed invalid filter handle (high 32 bits) */
8107 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
8109 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
8110 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12
8111 /* identifies the type of operation requested */
8112 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
8113 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
8114 /* Enum values, see field(s): */
8115 /* MC_CMD_FILTER_OP_EXT_IN/OP */
8116 /* Returned filter handle (for insert / subscribe operations). Note that these
8117 * handles should be considered opaque to the host, although a value of
8118 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
8120 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
8121 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
8122 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
8123 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
8124 /* Enum values, see field(s): */
8125 /* MC_CMD_FILTER_OP_OUT/HANDLE */
8128 /***********************************/
8129 /* MC_CMD_GET_PARSER_DISP_INFO
8130 * Get information related to the parser-dispatcher subsystem
8132 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
8133 #undef MC_CMD_0xe4_PRIVILEGE_CTG
8135 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8137 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
8138 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
8139 /* identifies the type of operation requested */
8140 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
8141 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
8142 /* enum: read the list of supported RX filter matches */
8143 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
8144 /* enum: read flags indicating restrictions on filter insertion for the calling
8147 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
8148 /* enum: read properties relating to security rules (Medford-only; for use by
8149 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
8151 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
8152 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE
8153 * encapsulated frames, which follow a different match sequence to normal
8154 * frames (Medford only)
8156 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
8158 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
8159 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
8160 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
8161 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
8162 /* identifies the type of operation requested */
8163 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
8164 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
8165 /* Enum values, see field(s): */
8166 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
8167 /* number of supported match types */
8168 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
8169 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
8170 /* array of supported match types (valid MATCH_FIELDS values for
8171 * MC_CMD_FILTER_OP) sorted in decreasing priority order
8173 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
8174 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
8175 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
8176 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
8178 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */
8179 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8
8180 /* identifies the type of operation requested */
8181 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
8182 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
8183 /* Enum values, see field(s): */
8184 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
8185 /* bitfield of filter insertion restrictions */
8186 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
8187 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
8188 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
8189 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
8191 /* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse:
8192 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO.
8193 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
8194 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
8195 * been used in any released code and may change during development. This note
8196 * will be removed once it is regarded as stable.
8198 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36
8199 /* identifies the type of operation requested */
8200 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0
8201 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_LEN 4
8202 /* Enum values, see field(s): */
8203 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
8204 /* a version number representing the set of rule lookups that are implemented
8205 * by the currently running firmware
8207 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4
8208 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4
8209 /* enum: implements lookup sequences described in SF-114946-SW draft C */
8210 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0
8211 /* the number of nodes in the subnet map */
8212 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8
8213 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4
8214 /* the number of entries in one subnet map node */
8215 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12
8216 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_LEN 4
8217 /* minimum valid value for a subnet ID in a subnet map leaf */
8218 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16
8219 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_LEN 4
8220 /* maximum valid value for a subnet ID in a subnet map leaf */
8221 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20
8222 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_LEN 4
8223 /* the number of entries in the local and remote port range maps */
8224 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24
8225 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_LEN 4
8226 /* minimum valid value for a portrange ID in a port range map leaf */
8227 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28
8228 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_LEN 4
8229 /* maximum valid value for a portrange ID in a port range map leaf */
8230 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32
8231 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4
8234 /***********************************/
8235 /* MC_CMD_PARSER_DISP_RW
8236 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
8237 * Please note that this interface is only of use to debug tools which have
8238 * knowledge of firmware and hardware data structures; nothing here is intended
8239 * for use by normal driver code. Note that although this command is in the
8240 * Admin privilege group, in tamperproof adapters, only read operations are
8243 #define MC_CMD_PARSER_DISP_RW 0xe5
8244 #undef MC_CMD_0xe5_PRIVILEGE_CTG
8246 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8248 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */
8249 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32
8250 /* identifies the target of the operation */
8251 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
8252 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4
8253 /* enum: RX dispatcher CPU */
8254 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
8255 /* enum: TX dispatcher CPU */
8256 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
8257 /* enum: Lookup engine (with original metadata format). Deprecated; used only
8258 * by cmdclient as a fallback for very old Huntington firmware, and not
8259 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA
8262 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
8263 /* enum: Lookup engine (with requested metadata format) */
8264 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
8265 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */
8266 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
8267 /* enum: RX1 dispatcher CPU (only valid for Medford) */
8268 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
8269 /* enum: Miscellaneous other state (only valid for Medford) */
8270 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
8271 /* identifies the type of operation requested */
8272 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
8273 #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
8274 /* enum: Read a word of DICPU DMEM or a LUE entry */
8275 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
8276 /* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on
8277 * tamperproof adapters.
8279 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
8280 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
8281 * permitted on tamperproof adapters.
8283 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
8284 /* data memory address (DICPU targets) or LUE index (LUE targets) */
8285 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
8286 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4
8287 /* selector (for MISC_STATE target) */
8288 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8
8289 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4
8290 /* enum: Port to datapath mapping */
8291 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
8292 /* value to write (for DMEM writes) */
8293 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12
8294 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4
8295 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
8296 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12
8297 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4
8298 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
8299 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16
8300 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4
8301 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */
8302 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12
8303 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4
8304 /* value to write (for LUE writes) */
8305 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12
8306 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20
8308 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */
8309 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52
8310 /* value read (for DMEM reads) */
8311 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
8312 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4
8313 /* value read (for LUE reads) */
8314 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
8315 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20
8316 /* up to 8 32-bit words of additional soft state from the LUE manager (the
8317 * exact content is firmware-dependent and intended only for debug use)
8319 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20
8320 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32
8321 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */
8322 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
8323 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
8324 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
8325 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
8326 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
8329 /***********************************/
8330 /* MC_CMD_GET_PF_COUNT
8331 * Get number of PFs on the device.
8333 #define MC_CMD_GET_PF_COUNT 0xb6
8334 #undef MC_CMD_0xb6_PRIVILEGE_CTG
8336 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8338 /* MC_CMD_GET_PF_COUNT_IN msgrequest */
8339 #define MC_CMD_GET_PF_COUNT_IN_LEN 0
8341 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */
8342 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1
8343 /* Identifies the number of PFs on the device. */
8344 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
8345 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
8348 /***********************************/
8349 /* MC_CMD_SET_PF_COUNT
8350 * Set number of PFs on the device.
8352 #define MC_CMD_SET_PF_COUNT 0xb7
8354 /* MC_CMD_SET_PF_COUNT_IN msgrequest */
8355 #define MC_CMD_SET_PF_COUNT_IN_LEN 4
8356 /* New number of PFs on the device. */
8357 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
8358 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4
8360 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */
8361 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0
8364 /***********************************/
8365 /* MC_CMD_GET_PORT_ASSIGNMENT
8366 * Get port assignment for current PCI function.
8368 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
8369 #undef MC_CMD_0xb8_PRIVILEGE_CTG
8371 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8373 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
8374 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
8376 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
8377 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
8378 /* Identifies the port assignment for this function. */
8379 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
8380 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
8383 /***********************************/
8384 /* MC_CMD_SET_PORT_ASSIGNMENT
8385 * Set port assignment for current PCI function.
8387 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
8388 #undef MC_CMD_0xb9_PRIVILEGE_CTG
8390 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8392 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
8393 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
8394 /* Identifies the port assignment for this function. */
8395 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
8396 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
8398 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
8399 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
8402 /***********************************/
8404 * Allocate VIs for current PCI function.
8406 #define MC_CMD_ALLOC_VIS 0x8b
8407 #undef MC_CMD_0x8b_PRIVILEGE_CTG
8409 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8411 /* MC_CMD_ALLOC_VIS_IN msgrequest */
8412 #define MC_CMD_ALLOC_VIS_IN_LEN 8
8413 /* The minimum number of VIs that is acceptable */
8414 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
8415 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
8416 /* The maximum number of VIs that would be useful */
8417 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
8418 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
8420 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
8421 * Use extended version in new code.
8423 #define MC_CMD_ALLOC_VIS_OUT_LEN 8
8424 /* The number of VIs allocated on this function */
8425 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
8426 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
8427 /* The base absolute VI number allocated to this function. Required to
8428 * correctly interpret wakeup events.
8430 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
8431 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
8433 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */
8434 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12
8435 /* The number of VIs allocated on this function */
8436 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
8437 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
8438 /* The base absolute VI number allocated to this function. Required to
8439 * correctly interpret wakeup events.
8441 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
8442 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
8443 /* Function's port vi_shift value (always 0 on Huntington) */
8444 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8
8445 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
8448 /***********************************/
8450 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
8453 #define MC_CMD_FREE_VIS 0x8c
8454 #undef MC_CMD_0x8c_PRIVILEGE_CTG
8456 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8458 /* MC_CMD_FREE_VIS_IN msgrequest */
8459 #define MC_CMD_FREE_VIS_IN_LEN 0
8461 /* MC_CMD_FREE_VIS_OUT msgresponse */
8462 #define MC_CMD_FREE_VIS_OUT_LEN 0
8465 /***********************************/
8466 /* MC_CMD_GET_SRIOV_CFG
8467 * Get SRIOV config for this PF.
8469 #define MC_CMD_GET_SRIOV_CFG 0xba
8470 #undef MC_CMD_0xba_PRIVILEGE_CTG
8472 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8474 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
8475 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
8477 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
8478 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
8479 /* Number of VFs currently enabled. */
8480 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
8481 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
8482 /* Max number of VFs before sriov stride and offset may need to be changed. */
8483 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
8484 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
8485 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
8486 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
8487 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
8488 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
8489 /* RID offset of first VF from PF. */
8490 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
8491 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
8492 /* RID offset of each subsequent VF from the previous. */
8493 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
8494 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
8497 /***********************************/
8498 /* MC_CMD_SET_SRIOV_CFG
8499 * Set SRIOV config for this PF.
8501 #define MC_CMD_SET_SRIOV_CFG 0xbb
8502 #undef MC_CMD_0xbb_PRIVILEGE_CTG
8504 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8506 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
8507 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20
8508 /* Number of VFs currently enabled. */
8509 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
8510 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
8511 /* Max number of VFs before sriov stride and offset may need to be changed. */
8512 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
8513 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
8514 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
8515 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
8516 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
8517 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
8518 /* RID offset of first VF from PF, or 0 for no change, or
8519 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
8521 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
8522 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
8523 /* RID offset of each subsequent VF from the previous, 0 for no change, or
8524 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
8526 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
8527 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
8529 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
8530 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
8533 /***********************************/
8534 /* MC_CMD_GET_VI_ALLOC_INFO
8535 * Get information about number of VI's and base VI number allocated to this
8538 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
8539 #undef MC_CMD_0x8d_PRIVILEGE_CTG
8541 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8543 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */
8544 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
8546 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */
8547 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12
8548 /* The number of VIs allocated on this function */
8549 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
8550 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
8551 /* The base absolute VI number allocated to this function. Required to
8552 * correctly interpret wakeup events.
8554 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
8555 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
8556 /* Function's port vi_shift value (always 0 on Huntington) */
8557 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8
8558 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
8561 /***********************************/
8562 /* MC_CMD_DUMP_VI_STATE
8563 * For CmdClient use. Dump pertinent information on a specific absolute VI.
8565 #define MC_CMD_DUMP_VI_STATE 0x8e
8566 #undef MC_CMD_0x8e_PRIVILEGE_CTG
8568 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8570 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */
8571 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4
8572 /* The VI number to query. */
8573 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
8574 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
8576 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
8577 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96
8578 /* The PF part of the function owning this VI. */
8579 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
8580 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
8581 /* The VF part of the function owning this VI. */
8582 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2
8583 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2
8584 /* Base of VIs allocated to this function. */
8585 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
8586 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2
8587 /* Count of VIs allocated to the owner function. */
8588 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6
8589 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2
8590 /* Base interrupt vector allocated to this function. */
8591 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8
8592 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2
8593 /* Number of interrupt vectors allocated to this function. */
8594 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10
8595 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2
8596 /* Raw evq ptr table data. */
8597 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
8598 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
8599 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
8600 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
8601 /* Raw evq timer table data. */
8602 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
8603 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
8604 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
8605 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
8606 /* Combined metadata field. */
8607 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
8608 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
8609 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
8610 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
8611 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
8612 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
8613 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
8614 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
8615 /* TXDPCPU raw table data for queue. */
8616 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
8617 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
8618 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
8619 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
8620 /* TXDPCPU raw table data for queue. */
8621 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
8622 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
8623 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
8624 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
8625 /* TXDPCPU raw table data for queue. */
8626 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
8627 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
8628 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
8629 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
8630 /* Combined metadata field. */
8631 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
8632 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
8633 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
8634 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
8635 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
8636 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
8637 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
8638 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
8639 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
8640 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
8641 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
8642 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
8643 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
8644 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
8645 /* RXDPCPU raw table data for queue. */
8646 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
8647 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
8648 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
8649 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
8650 /* RXDPCPU raw table data for queue. */
8651 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
8652 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
8653 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
8654 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
8655 /* Reserved, currently 0. */
8656 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
8657 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
8658 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
8659 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
8660 /* Combined metadata field. */
8661 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
8662 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
8663 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
8664 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
8665 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
8666 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
8667 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
8668 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
8669 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
8670 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
8671 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
8672 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
8675 /***********************************/
8676 /* MC_CMD_ALLOC_PIOBUF
8677 * Allocate a push I/O buffer for later use with a tx queue.
8679 #define MC_CMD_ALLOC_PIOBUF 0x8f
8680 #undef MC_CMD_0x8f_PRIVILEGE_CTG
8682 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
8684 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
8685 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
8687 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
8688 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
8689 /* Handle for allocated push I/O buffer. */
8690 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
8691 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
8694 /***********************************/
8695 /* MC_CMD_FREE_PIOBUF
8696 * Free a push I/O buffer.
8698 #define MC_CMD_FREE_PIOBUF 0x90
8699 #undef MC_CMD_0x90_PRIVILEGE_CTG
8701 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
8703 /* MC_CMD_FREE_PIOBUF_IN msgrequest */
8704 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
8705 /* Handle for allocated push I/O buffer. */
8706 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
8707 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
8709 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */
8710 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
8713 /***********************************/
8714 /* MC_CMD_GET_VI_TLP_PROCESSING
8715 * Get TLP steering and ordering information for a VI.
8717 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
8718 #undef MC_CMD_0xb0_PRIVILEGE_CTG
8720 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8722 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
8723 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
8724 /* VI number to get information for. */
8725 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
8726 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
8728 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */
8729 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
8730 /* Transaction processing steering hint 1 for use with the Rx Queue. */
8731 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
8732 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
8733 /* Transaction processing steering hint 2 for use with the Ev Queue. */
8734 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
8735 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
8736 /* Use Relaxed ordering model for TLPs on this VI. */
8737 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
8738 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
8739 /* Use ID based ordering for TLPs on this VI. */
8740 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
8741 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
8742 /* Set no snoop bit for TLPs on this VI. */
8743 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18
8744 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
8745 /* Enable TPH for TLPs on this VI. */
8746 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
8747 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
8748 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
8749 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
8752 /***********************************/
8753 /* MC_CMD_SET_VI_TLP_PROCESSING
8754 * Set TLP steering and ordering information for a VI.
8756 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
8757 #undef MC_CMD_0xb1_PRIVILEGE_CTG
8759 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8761 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
8762 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
8763 /* VI number to set information for. */
8764 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
8765 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
8766 /* Transaction processing steering hint 1 for use with the Rx Queue. */
8767 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
8768 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
8769 /* Transaction processing steering hint 2 for use with the Ev Queue. */
8770 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5
8771 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
8772 /* Use Relaxed ordering model for TLPs on this VI. */
8773 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
8774 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
8775 /* Use ID based ordering for TLPs on this VI. */
8776 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
8777 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
8778 /* Set the no snoop bit for TLPs on this VI. */
8779 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50
8780 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
8781 /* Enable TPH for TLPs on this VI. */
8782 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
8783 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
8784 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
8785 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
8787 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
8788 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
8791 /***********************************/
8792 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS
8793 * Get global PCIe steering and transaction processing configuration.
8795 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
8796 #undef MC_CMD_0xbc_PRIVILEGE_CTG
8798 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8800 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */
8801 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
8802 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
8803 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
8805 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
8807 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
8809 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
8810 /* enum: TPH Type. */
8811 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
8813 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
8814 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
8815 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
8816 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4
8817 /* Enum values, see field(s): */
8818 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
8819 /* Amalgamated TLP info word. */
8820 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
8821 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4
8822 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
8823 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
8824 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
8825 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
8826 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
8827 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
8828 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
8829 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
8830 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2
8831 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
8832 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
8833 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
8834 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
8835 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
8836 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
8837 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
8838 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
8839 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
8840 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
8841 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
8842 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
8843 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
8844 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
8845 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
8846 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2
8847 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2
8848 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
8849 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2
8850 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6
8851 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2
8852 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
8853 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
8854 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
8855 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
8858 /***********************************/
8859 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS
8860 * Set global PCIe steering and transaction processing configuration.
8862 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
8863 #undef MC_CMD_0xbd_PRIVILEGE_CTG
8865 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8867 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */
8868 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8
8869 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
8870 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
8871 /* Enum values, see field(s): */
8872 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
8873 /* Amalgamated TLP info word. */
8874 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
8875 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4
8876 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
8877 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
8878 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
8879 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
8880 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
8881 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
8882 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2
8883 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
8884 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3
8885 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
8886 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
8887 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
8888 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
8889 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
8890 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2
8891 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
8892 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
8893 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
8894 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2
8895 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2
8896 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
8897 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2
8898 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6
8899 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2
8900 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
8901 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
8902 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
8903 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
8905 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
8906 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
8909 /***********************************/
8910 /* MC_CMD_SATELLITE_DOWNLOAD
8911 * Download a new set of images to the satellite CPUs from the host.
8913 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
8914 #undef MC_CMD_0x91_PRIVILEGE_CTG
8916 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8918 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs
8919 * are subtle, and so downloads must proceed in a number of phases.
8921 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
8923 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
8924 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should
8925 * be a checksum (a simple 32-bit sum) of the transferred data. An individual
8926 * download may be aborted using CHUNK_ID_ABORT.
8928 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
8929 * similar to PHASE_IMEMS.
8931 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
8933 * After any error (a requested abort is not considered to be an error) the
8934 * sequence must be restarted from PHASE_RESET.
8936 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20
8937 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
8938 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
8939 /* Download phase. (Note: the IDLE phase is used internally and is never valid
8940 * in a command from the host.)
8942 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
8943 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4
8944 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
8945 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
8946 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
8947 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
8948 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
8949 /* Target for download. (These match the blob numbers defined in
8950 * mc_flash_layout.h.)
8952 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
8953 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4
8954 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8955 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
8956 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8957 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
8958 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8959 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
8960 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8961 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
8962 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8963 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
8964 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8965 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
8966 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8967 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
8968 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8969 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
8970 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8971 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
8972 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8973 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
8974 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8975 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
8976 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
8977 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
8978 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
8979 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
8980 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
8981 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
8982 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
8983 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
8984 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
8985 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
8986 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
8987 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
8988 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */
8989 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8
8990 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4
8991 /* enum: Last chunk, containing checksum rather than data */
8992 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
8993 /* enum: Abort download of this item */
8994 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
8995 /* Length of this chunk in bytes */
8996 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12
8997 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4
8998 /* Data for this chunk */
8999 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16
9000 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
9001 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
9002 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59
9004 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */
9005 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8
9006 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
9007 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
9008 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4
9009 /* Extra status information */
9010 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
9011 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4
9012 /* enum: Code download OK, completed. */
9013 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
9014 /* enum: Code download aborted as requested. */
9015 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
9016 /* enum: Code download OK so far, send next chunk. */
9017 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
9018 /* enum: Download phases out of sequence */
9019 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
9020 /* enum: Bad target for this phase */
9021 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
9022 /* enum: Chunk ID out of sequence */
9023 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
9024 /* enum: Chunk length zero or too large */
9025 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
9026 /* enum: Checksum was incorrect */
9027 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
9030 /***********************************/
9031 /* MC_CMD_GET_CAPABILITIES
9032 * Get device capabilities.
9034 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to
9035 * reference inherent device capabilities as opposed to current NVRAM config.
9037 #define MC_CMD_GET_CAPABILITIES 0xbe
9038 #undef MC_CMD_0xbe_PRIVILEGE_CTG
9040 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9042 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */
9043 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0
9045 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
9046 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20
9047 /* First word of flags. */
9048 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
9049 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
9050 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3
9051 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
9052 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
9053 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
9054 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5
9055 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
9056 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
9057 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
9058 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7
9059 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
9060 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8
9061 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
9062 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9
9063 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
9064 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
9065 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
9066 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
9067 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
9068 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
9069 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
9070 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13
9071 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
9072 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14
9073 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
9074 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
9075 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
9076 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16
9077 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
9078 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17
9079 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
9080 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18
9081 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
9082 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
9083 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
9084 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
9085 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
9086 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
9087 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
9088 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
9089 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
9090 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
9091 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
9092 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
9093 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
9094 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
9095 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
9096 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
9097 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
9098 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
9099 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
9100 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28
9101 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
9102 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
9103 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
9104 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
9105 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
9106 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31
9107 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
9108 /* RxDPCPU firmware id. */
9109 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
9110 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
9111 /* enum: Standard RXDP firmware */
9112 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
9113 /* enum: Low latency RXDP firmware */
9114 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
9115 /* enum: Packed stream RXDP firmware */
9116 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
9117 /* enum: Rules engine RXDP firmware */
9118 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
9119 /* enum: BIST RXDP firmware */
9120 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
9121 /* enum: RXDP Test firmware image 1 */
9122 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9123 /* enum: RXDP Test firmware image 2 */
9124 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9125 /* enum: RXDP Test firmware image 3 */
9126 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9127 /* enum: RXDP Test firmware image 4 */
9128 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9129 /* enum: RXDP Test firmware image 5 */
9130 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
9131 /* enum: RXDP Test firmware image 6 */
9132 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9133 /* enum: RXDP Test firmware image 7 */
9134 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9135 /* enum: RXDP Test firmware image 8 */
9136 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9137 /* enum: RXDP Test firmware image 9 */
9138 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9139 /* enum: RXDP Test firmware image 10 */
9140 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
9141 /* TxDPCPU firmware id. */
9142 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
9143 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
9144 /* enum: Standard TXDP firmware */
9145 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
9146 /* enum: Low latency TXDP firmware */
9147 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
9148 /* enum: High packet rate TXDP firmware */
9149 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
9150 /* enum: Rules engine TXDP firmware */
9151 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
9152 /* enum: BIST TXDP firmware */
9153 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
9154 /* enum: TXDP Test firmware image 1 */
9155 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9156 /* enum: TXDP Test firmware image 2 */
9157 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9158 /* enum: TXDP CSR bus test firmware */
9159 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
9160 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
9161 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
9162 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
9163 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
9164 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
9165 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
9166 /* enum: reserved value - do not use (may indicate alternative interpretation
9167 * of REV field in future)
9169 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
9170 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9173 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9174 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9175 * (Huntington development only)
9177 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9178 /* enum: Full featured RX PD production firmware */
9179 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9180 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9181 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9182 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9183 * (Huntington development only)
9185 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9186 /* enum: Low latency RX PD production firmware */
9187 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9188 /* enum: Packed stream RX PD production firmware */
9189 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9190 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9191 * tests (Medford development only)
9193 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9194 /* enum: Rules engine RX PD production firmware */
9195 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9196 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9197 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9198 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9199 * encapsulations (Medford development only)
9201 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
9202 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
9203 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
9204 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
9205 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
9206 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
9207 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
9208 /* enum: reserved value - do not use (may indicate alternative interpretation
9209 * of REV field in future)
9211 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
9212 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9215 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
9216 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9217 * (Huntington development only)
9219 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
9220 /* enum: Full featured TX PD production firmware */
9221 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
9222 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9223 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
9224 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
9225 * (Huntington development only)
9227 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9228 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
9229 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
9230 * tests (Medford development only)
9232 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
9233 /* enum: Rules engine TX PD production firmware */
9234 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
9235 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9236 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9237 /* Hardware capabilities of NIC */
9238 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
9239 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
9240 /* Licensed capabilities */
9241 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
9242 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
9244 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */
9245 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
9247 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */
9248 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72
9249 /* First word of flags. */
9250 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
9251 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
9252 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3
9253 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
9254 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
9255 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
9256 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5
9257 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
9258 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
9259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
9260 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7
9261 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
9262 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8
9263 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
9264 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9
9265 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
9266 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
9267 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
9268 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
9269 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
9270 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
9271 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
9272 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13
9273 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
9274 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14
9275 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
9276 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
9277 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
9278 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16
9279 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
9280 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17
9281 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
9282 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18
9283 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
9284 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19
9285 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
9286 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20
9287 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
9288 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21
9289 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
9290 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22
9291 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
9292 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23
9293 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
9294 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24
9295 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
9296 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25
9297 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
9298 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26
9299 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
9300 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27
9301 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
9302 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28
9303 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
9304 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
9305 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
9306 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30
9307 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
9308 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31
9309 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
9310 /* RxDPCPU firmware id. */
9311 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
9312 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2
9313 /* enum: Standard RXDP firmware */
9314 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
9315 /* enum: Low latency RXDP firmware */
9316 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
9317 /* enum: Packed stream RXDP firmware */
9318 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
9319 /* enum: Rules engine RXDP firmware */
9320 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
9321 /* enum: BIST RXDP firmware */
9322 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
9323 /* enum: RXDP Test firmware image 1 */
9324 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9325 /* enum: RXDP Test firmware image 2 */
9326 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9327 /* enum: RXDP Test firmware image 3 */
9328 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9329 /* enum: RXDP Test firmware image 4 */
9330 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9331 /* enum: RXDP Test firmware image 5 */
9332 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
9333 /* enum: RXDP Test firmware image 6 */
9334 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9335 /* enum: RXDP Test firmware image 7 */
9336 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9337 /* enum: RXDP Test firmware image 8 */
9338 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9339 /* enum: RXDP Test firmware image 9 */
9340 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9341 /* enum: RXDP Test firmware image 10 */
9342 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
9343 /* TxDPCPU firmware id. */
9344 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6
9345 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2
9346 /* enum: Standard TXDP firmware */
9347 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
9348 /* enum: Low latency TXDP firmware */
9349 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
9350 /* enum: High packet rate TXDP firmware */
9351 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
9352 /* enum: Rules engine TXDP firmware */
9353 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
9354 /* enum: BIST TXDP firmware */
9355 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
9356 /* enum: TXDP Test firmware image 1 */
9357 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9358 /* enum: TXDP Test firmware image 2 */
9359 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9360 /* enum: TXDP CSR bus test firmware */
9361 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
9362 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
9363 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
9364 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
9365 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12
9366 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12
9367 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
9368 /* enum: reserved value - do not use (may indicate alternative interpretation
9369 * of REV field in future)
9371 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
9372 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9375 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9376 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9377 * (Huntington development only)
9379 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9380 /* enum: Full featured RX PD production firmware */
9381 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9382 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9383 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9384 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9385 * (Huntington development only)
9387 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9388 /* enum: Low latency RX PD production firmware */
9389 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9390 /* enum: Packed stream RX PD production firmware */
9391 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9392 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9393 * tests (Medford development only)
9395 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9396 /* enum: Rules engine RX PD production firmware */
9397 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9398 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9399 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9400 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9401 * encapsulations (Medford development only)
9403 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
9404 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
9405 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
9406 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
9407 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12
9408 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12
9409 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
9410 /* enum: reserved value - do not use (may indicate alternative interpretation
9411 * of REV field in future)
9413 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
9414 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9417 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
9418 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9419 * (Huntington development only)
9421 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
9422 /* enum: Full featured TX PD production firmware */
9423 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
9424 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9425 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
9426 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
9427 * (Huntington development only)
9429 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9430 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
9431 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
9432 * tests (Medford development only)
9434 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
9435 /* enum: Rules engine TX PD production firmware */
9436 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
9437 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9438 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9439 /* Hardware capabilities of NIC */
9440 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12
9441 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
9442 /* Licensed capabilities */
9443 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16
9444 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
9445 /* Second word of flags. Not present on older firmware (check the length). */
9446 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20
9447 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
9448 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
9449 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
9450 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
9451 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
9452 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2
9453 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
9454 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3
9455 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
9456 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
9457 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
9458 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5
9459 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
9460 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
9461 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
9462 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7
9463 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
9464 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8
9465 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
9466 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9
9467 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
9468 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10
9469 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
9470 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11
9471 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
9472 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
9473 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
9474 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13
9475 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
9476 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14
9477 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
9478 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
9479 * on older firmware (check the length).
9481 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
9482 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
9483 /* One byte per PF containing the number of the external port assigned to this
9484 * PF, indexed by PF number. Special values indicate that a PF is either not
9485 * present or not assigned.
9487 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
9488 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
9489 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
9490 /* enum: The caller is not permitted to access information on this PF. */
9491 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
9492 /* enum: PF does not exist. */
9493 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
9494 /* enum: PF does exist but is not assigned to any external port. */
9495 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
9496 /* enum: This value indicates that PF is assigned, but it cannot be expressed
9497 * in this field. It is intended for a possible future situation where a more
9498 * complex scheme of PFs to ports mapping is being used. The future driver
9499 * should look for a new field supporting the new scheme. The current/old
9500 * driver should treat this value as PF_NOT_ASSIGNED.
9502 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
9503 /* One byte per PF containing the number of its VFs, indexed by PF number. A
9504 * special value indicates that a PF is not present.
9506 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42
9507 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
9508 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16
9509 /* enum: The caller is not permitted to access information on this PF. */
9510 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
9511 /* enum: PF does not exist. */
9512 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
9513 /* Number of VIs available for each external port */
9514 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
9515 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
9516 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
9517 /* Size of RX descriptor cache expressed as binary logarithm The actual size
9518 * equals (2 ^ RX_DESC_CACHE_SIZE)
9520 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66
9521 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
9522 /* Size of TX descriptor cache expressed as binary logarithm The actual size
9523 * equals (2 ^ TX_DESC_CACHE_SIZE)
9525 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67
9526 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
9527 /* Total number of available PIO buffers */
9528 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68
9529 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2
9530 /* Size of a single PIO buffer */
9531 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70
9532 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2
9534 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */
9535 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76
9536 /* First word of flags. */
9537 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
9538 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
9539 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3
9540 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
9541 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
9542 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
9543 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5
9544 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
9545 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
9546 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
9547 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7
9548 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
9549 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8
9550 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
9551 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9
9552 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
9553 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
9554 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
9555 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
9556 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
9557 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
9558 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
9559 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13
9560 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
9561 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14
9562 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
9563 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
9564 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
9565 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16
9566 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
9567 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17
9568 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
9569 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18
9570 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
9571 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19
9572 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
9573 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20
9574 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
9575 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21
9576 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
9577 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22
9578 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
9579 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23
9580 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
9581 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24
9582 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
9583 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25
9584 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
9585 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26
9586 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
9587 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27
9588 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
9589 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28
9590 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
9591 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
9592 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
9593 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30
9594 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
9595 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31
9596 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
9597 /* RxDPCPU firmware id. */
9598 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
9599 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2
9600 /* enum: Standard RXDP firmware */
9601 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
9602 /* enum: Low latency RXDP firmware */
9603 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
9604 /* enum: Packed stream RXDP firmware */
9605 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
9606 /* enum: Rules engine RXDP firmware */
9607 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
9608 /* enum: BIST RXDP firmware */
9609 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
9610 /* enum: RXDP Test firmware image 1 */
9611 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9612 /* enum: RXDP Test firmware image 2 */
9613 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9614 /* enum: RXDP Test firmware image 3 */
9615 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9616 /* enum: RXDP Test firmware image 4 */
9617 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9618 /* enum: RXDP Test firmware image 5 */
9619 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
9620 /* enum: RXDP Test firmware image 6 */
9621 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9622 /* enum: RXDP Test firmware image 7 */
9623 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9624 /* enum: RXDP Test firmware image 8 */
9625 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9626 /* enum: RXDP Test firmware image 9 */
9627 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9628 /* enum: RXDP Test firmware image 10 */
9629 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
9630 /* TxDPCPU firmware id. */
9631 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6
9632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2
9633 /* enum: Standard TXDP firmware */
9634 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
9635 /* enum: Low latency TXDP firmware */
9636 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
9637 /* enum: High packet rate TXDP firmware */
9638 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
9639 /* enum: Rules engine TXDP firmware */
9640 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
9641 /* enum: BIST TXDP firmware */
9642 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
9643 /* enum: TXDP Test firmware image 1 */
9644 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9645 /* enum: TXDP Test firmware image 2 */
9646 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9647 /* enum: TXDP CSR bus test firmware */
9648 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
9649 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8
9650 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2
9651 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
9652 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12
9653 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12
9654 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
9655 /* enum: reserved value - do not use (may indicate alternative interpretation
9656 * of REV field in future)
9658 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
9659 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9662 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9663 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9664 * (Huntington development only)
9666 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9667 /* enum: Full featured RX PD production firmware */
9668 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9669 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9670 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9671 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9672 * (Huntington development only)
9674 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9675 /* enum: Low latency RX PD production firmware */
9676 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9677 /* enum: Packed stream RX PD production firmware */
9678 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9679 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9680 * tests (Medford development only)
9682 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9683 /* enum: Rules engine RX PD production firmware */
9684 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9685 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9686 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9687 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9688 * encapsulations (Medford development only)
9690 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
9691 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10
9692 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2
9693 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
9694 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12
9695 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12
9696 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
9697 /* enum: reserved value - do not use (may indicate alternative interpretation
9698 * of REV field in future)
9700 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
9701 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9704 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
9705 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9706 * (Huntington development only)
9708 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
9709 /* enum: Full featured TX PD production firmware */
9710 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
9711 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9712 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
9713 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
9714 * (Huntington development only)
9716 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9717 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
9718 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
9719 * tests (Medford development only)
9721 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
9722 /* enum: Rules engine TX PD production firmware */
9723 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
9724 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9725 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9726 /* Hardware capabilities of NIC */
9727 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12
9728 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
9729 /* Licensed capabilities */
9730 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16
9731 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
9732 /* Second word of flags. Not present on older firmware (check the length). */
9733 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20
9734 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
9735 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
9736 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
9737 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
9738 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
9739 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2
9740 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
9741 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3
9742 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
9743 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
9744 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
9745 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5
9746 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
9747 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
9748 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
9749 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7
9750 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
9751 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8
9752 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
9753 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9
9754 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
9755 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10
9756 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
9757 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11
9758 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
9759 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
9760 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
9761 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13
9762 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
9763 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14
9764 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
9765 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
9766 * on older firmware (check the length).
9768 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
9769 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
9770 /* One byte per PF containing the number of the external port assigned to this
9771 * PF, indexed by PF number. Special values indicate that a PF is either not
9772 * present or not assigned.
9774 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
9775 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
9776 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
9777 /* enum: The caller is not permitted to access information on this PF. */
9778 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
9779 /* enum: PF does not exist. */
9780 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
9781 /* enum: PF does exist but is not assigned to any external port. */
9782 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
9783 /* enum: This value indicates that PF is assigned, but it cannot be expressed
9784 * in this field. It is intended for a possible future situation where a more
9785 * complex scheme of PFs to ports mapping is being used. The future driver
9786 * should look for a new field supporting the new scheme. The current/old
9787 * driver should treat this value as PF_NOT_ASSIGNED.
9789 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
9790 /* One byte per PF containing the number of its VFs, indexed by PF number. A
9791 * special value indicates that a PF is not present.
9793 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42
9794 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
9795 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16
9796 /* enum: The caller is not permitted to access information on this PF. */
9797 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
9798 /* enum: PF does not exist. */
9799 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
9800 /* Number of VIs available for each external port */
9801 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
9802 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
9803 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
9804 /* Size of RX descriptor cache expressed as binary logarithm The actual size
9805 * equals (2 ^ RX_DESC_CACHE_SIZE)
9807 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66
9808 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1
9809 /* Size of TX descriptor cache expressed as binary logarithm The actual size
9810 * equals (2 ^ TX_DESC_CACHE_SIZE)
9812 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67
9813 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1
9814 /* Total number of available PIO buffers */
9815 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68
9816 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2
9817 /* Size of a single PIO buffer */
9818 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70
9819 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2
9820 /* On chips later than Medford the amount of address space assigned to each VI
9821 * is configurable. This is a global setting that the driver must query to
9822 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
9823 * with 8k VI windows.
9825 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72
9826 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1
9827 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
9828 * CTPIO is not mapped.
9830 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
9831 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
9832 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
9833 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
9834 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
9835 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
9836 * (SF-115995-SW) in the present configuration of firmware and port mode.
9838 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
9839 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
9840 /* Number of buffers per adapter that can be used for VFIFO Stuffing
9841 * (SF-115995-SW) in the present configuration of firmware and port mode.
9843 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
9844 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
9846 /* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */
9847 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78
9848 /* First word of flags. */
9849 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
9850 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
9851 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3
9852 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
9853 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
9854 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
9855 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5
9856 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
9857 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
9858 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
9859 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7
9860 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
9861 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8
9862 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
9863 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9
9864 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
9865 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
9866 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
9867 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
9868 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
9869 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
9870 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
9871 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13
9872 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
9873 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14
9874 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
9875 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
9876 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
9877 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16
9878 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
9879 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17
9880 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
9881 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18
9882 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
9883 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19
9884 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
9885 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20
9886 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
9887 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21
9888 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
9889 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22
9890 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
9891 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23
9892 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
9893 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24
9894 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
9895 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25
9896 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
9897 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26
9898 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
9899 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27
9900 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
9901 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28
9902 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
9903 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
9904 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
9905 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30
9906 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
9907 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31
9908 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
9909 /* RxDPCPU firmware id. */
9910 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
9911 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2
9912 /* enum: Standard RXDP firmware */
9913 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
9914 /* enum: Low latency RXDP firmware */
9915 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
9916 /* enum: Packed stream RXDP firmware */
9917 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
9918 /* enum: Rules engine RXDP firmware */
9919 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
9920 /* enum: BIST RXDP firmware */
9921 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
9922 /* enum: RXDP Test firmware image 1 */
9923 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9924 /* enum: RXDP Test firmware image 2 */
9925 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9926 /* enum: RXDP Test firmware image 3 */
9927 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9928 /* enum: RXDP Test firmware image 4 */
9929 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9930 /* enum: RXDP Test firmware image 5 */
9931 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
9932 /* enum: RXDP Test firmware image 6 */
9933 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9934 /* enum: RXDP Test firmware image 7 */
9935 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9936 /* enum: RXDP Test firmware image 8 */
9937 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9938 /* enum: RXDP Test firmware image 9 */
9939 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9940 /* enum: RXDP Test firmware image 10 */
9941 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
9942 /* TxDPCPU firmware id. */
9943 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6
9944 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2
9945 /* enum: Standard TXDP firmware */
9946 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
9947 /* enum: Low latency TXDP firmware */
9948 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
9949 /* enum: High packet rate TXDP firmware */
9950 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
9951 /* enum: Rules engine TXDP firmware */
9952 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
9953 /* enum: BIST TXDP firmware */
9954 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
9955 /* enum: TXDP Test firmware image 1 */
9956 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9957 /* enum: TXDP Test firmware image 2 */
9958 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9959 /* enum: TXDP CSR bus test firmware */
9960 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
9961 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8
9962 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2
9963 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
9964 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12
9965 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12
9966 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
9967 /* enum: reserved value - do not use (may indicate alternative interpretation
9968 * of REV field in future)
9970 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
9971 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9974 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9975 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9976 * (Huntington development only)
9978 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9979 /* enum: Full featured RX PD production firmware */
9980 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9981 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9982 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9983 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9984 * (Huntington development only)
9986 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9987 /* enum: Low latency RX PD production firmware */
9988 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9989 /* enum: Packed stream RX PD production firmware */
9990 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9991 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9992 * tests (Medford development only)
9994 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9995 /* enum: Rules engine RX PD production firmware */
9996 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9997 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9998 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9999 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10000 * encapsulations (Medford development only)
10002 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10003 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10
10004 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2
10005 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
10006 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12
10007 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12
10008 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
10009 /* enum: reserved value - do not use (may indicate alternative interpretation
10010 * of REV field in future)
10012 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
10013 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10014 * development only)
10016 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10017 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10018 * (Huntington development only)
10020 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10021 /* enum: Full featured TX PD production firmware */
10022 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
10023 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10024 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10025 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10026 * (Huntington development only)
10028 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10029 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10030 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10031 * tests (Medford development only)
10033 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10034 /* enum: Rules engine TX PD production firmware */
10035 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10036 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10037 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10038 /* Hardware capabilities of NIC */
10039 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12
10040 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
10041 /* Licensed capabilities */
10042 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16
10043 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
10044 /* Second word of flags. Not present on older firmware (check the length). */
10045 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20
10046 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
10047 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
10048 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
10049 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
10050 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
10051 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2
10052 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
10053 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3
10054 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
10055 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
10056 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
10057 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5
10058 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
10059 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
10060 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
10061 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7
10062 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
10063 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8
10064 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
10065 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9
10066 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
10067 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10
10068 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
10069 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11
10070 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
10071 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
10072 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
10073 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13
10074 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
10075 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14
10076 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
10077 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
10078 * on older firmware (check the length).
10080 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
10081 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
10082 /* One byte per PF containing the number of the external port assigned to this
10083 * PF, indexed by PF number. Special values indicate that a PF is either not
10084 * present or not assigned.
10086 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
10087 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
10088 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
10089 /* enum: The caller is not permitted to access information on this PF. */
10090 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
10091 /* enum: PF does not exist. */
10092 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
10093 /* enum: PF does exist but is not assigned to any external port. */
10094 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
10095 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10096 * in this field. It is intended for a possible future situation where a more
10097 * complex scheme of PFs to ports mapping is being used. The future driver
10098 * should look for a new field supporting the new scheme. The current/old
10099 * driver should treat this value as PF_NOT_ASSIGNED.
10101 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10102 /* One byte per PF containing the number of its VFs, indexed by PF number. A
10103 * special value indicates that a PF is not present.
10105 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42
10106 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
10107 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16
10108 /* enum: The caller is not permitted to access information on this PF. */
10109 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
10110 /* enum: PF does not exist. */
10111 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
10112 /* Number of VIs available for each external port */
10113 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
10114 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
10115 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
10116 /* Size of RX descriptor cache expressed as binary logarithm The actual size
10117 * equals (2 ^ RX_DESC_CACHE_SIZE)
10119 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66
10120 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1
10121 /* Size of TX descriptor cache expressed as binary logarithm The actual size
10122 * equals (2 ^ TX_DESC_CACHE_SIZE)
10124 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67
10125 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1
10126 /* Total number of available PIO buffers */
10127 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68
10128 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2
10129 /* Size of a single PIO buffer */
10130 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70
10131 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2
10132 /* On chips later than Medford the amount of address space assigned to each VI
10133 * is configurable. This is a global setting that the driver must query to
10134 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
10135 * with 8k VI windows.
10137 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72
10138 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1
10139 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
10140 * CTPIO is not mapped.
10142 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
10143 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
10144 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
10145 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
10146 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
10147 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
10148 * (SF-115995-SW) in the present configuration of firmware and port mode.
10150 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
10151 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
10152 /* Number of buffers per adapter that can be used for VFIFO Stuffing
10153 * (SF-115995-SW) in the present configuration of firmware and port mode.
10155 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
10156 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
10157 /* Entry count in the MAC stats array, including the final GENERATION_END
10158 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
10159 * hold at least this many 64-bit stats values, if they wish to receive all
10160 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
10161 * stats array returned will be truncated.
10163 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76
10164 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2
10167 /***********************************/
10169 * Encapsulation for a v2 extended command
10171 #define MC_CMD_V2_EXTN 0x7f
10173 /* MC_CMD_V2_EXTN_IN msgrequest */
10174 #define MC_CMD_V2_EXTN_IN_LEN 4
10175 /* the extended command number */
10176 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
10177 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
10178 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
10179 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
10180 /* the actual length of the encapsulated command (which is not in the v1
10183 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
10184 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
10185 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
10186 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
10187 /* Type of command/response */
10188 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
10189 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
10190 /* enum: MCDI command directed to or response originating from the MC. */
10191 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
10192 /* enum: MCDI command directed to a TSA controller. MCDI responses of this type
10195 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
10198 /***********************************/
10199 /* MC_CMD_TCM_BUCKET_ALLOC
10200 * Allocate a pacer bucket (for qau rp or a snapper test)
10202 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
10203 #undef MC_CMD_0xb2_PRIVILEGE_CTG
10205 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10207 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
10208 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
10210 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
10211 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
10212 /* the bucket id */
10213 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
10214 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4
10217 /***********************************/
10218 /* MC_CMD_TCM_BUCKET_FREE
10219 * Free a pacer bucket
10221 #define MC_CMD_TCM_BUCKET_FREE 0xb3
10222 #undef MC_CMD_0xb3_PRIVILEGE_CTG
10224 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10226 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
10227 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
10228 /* the bucket id */
10229 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
10230 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4
10232 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
10233 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
10236 /***********************************/
10237 /* MC_CMD_TCM_BUCKET_INIT
10238 * Initialise pacer bucket with a given rate
10240 #define MC_CMD_TCM_BUCKET_INIT 0xb4
10241 #undef MC_CMD_0xb4_PRIVILEGE_CTG
10243 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10245 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
10246 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
10247 /* the bucket id */
10248 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
10249 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4
10250 /* the rate in mbps */
10251 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
10252 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4
10254 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */
10255 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12
10256 /* the bucket id */
10257 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0
10258 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4
10259 /* the rate in mbps */
10260 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4
10261 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4
10262 /* the desired maximum fill level */
10263 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8
10264 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4
10266 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
10267 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
10270 /***********************************/
10271 /* MC_CMD_TCM_TXQ_INIT
10272 * Initialise txq in pacer with given options or set options
10274 #define MC_CMD_TCM_TXQ_INIT 0xb5
10275 #undef MC_CMD_0xb5_PRIVILEGE_CTG
10277 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10279 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
10280 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28
10282 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
10283 #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4
10284 /* the static priority associated with the txq */
10285 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
10286 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4
10287 /* bitmask of the priority queues this txq is inserted into when inserted. */
10288 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
10289 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4
10290 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
10291 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
10292 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1
10293 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1
10294 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2
10295 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1
10296 /* the reaction point (RP) bucket */
10297 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
10298 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4
10299 /* an already reserved bucket (typically set to bucket associated with outer
10302 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
10303 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4
10304 /* an already reserved bucket (typically set to bucket associated with inner
10307 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
10308 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4
10309 /* the min bucket (typically for ETS/minimum bandwidth) */
10310 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
10311 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4
10313 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */
10314 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32
10316 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0
10317 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4
10318 /* the static priority associated with the txq */
10319 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4
10320 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4
10321 /* bitmask of the priority queues this txq is inserted into when inserted. */
10322 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8
10323 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4
10324 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
10325 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
10326 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1
10327 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1
10328 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2
10329 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1
10330 /* the reaction point (RP) bucket */
10331 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12
10332 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4
10333 /* an already reserved bucket (typically set to bucket associated with outer
10336 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16
10337 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4
10338 /* an already reserved bucket (typically set to bucket associated with inner
10341 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20
10342 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4
10343 /* the min bucket (typically for ETS/minimum bandwidth) */
10344 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24
10345 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4
10346 /* the static priority associated with the txq */
10347 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28
10348 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4
10350 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
10351 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
10354 /***********************************/
10355 /* MC_CMD_LINK_PIOBUF
10356 * Link a push I/O buffer to a TxQ
10358 #define MC_CMD_LINK_PIOBUF 0x92
10359 #undef MC_CMD_0x92_PRIVILEGE_CTG
10361 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
10363 /* MC_CMD_LINK_PIOBUF_IN msgrequest */
10364 #define MC_CMD_LINK_PIOBUF_IN_LEN 8
10365 /* Handle for allocated push I/O buffer. */
10366 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
10367 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
10368 /* Function Local Instance (VI) number. */
10369 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
10370 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
10372 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */
10373 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0
10376 /***********************************/
10377 /* MC_CMD_UNLINK_PIOBUF
10378 * Unlink a push I/O buffer from a TxQ
10380 #define MC_CMD_UNLINK_PIOBUF 0x93
10381 #undef MC_CMD_0x93_PRIVILEGE_CTG
10383 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
10385 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
10386 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
10387 /* Function Local Instance (VI) number. */
10388 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
10389 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
10391 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
10392 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
10395 /***********************************/
10396 /* MC_CMD_VSWITCH_ALLOC
10397 * allocate and initialise a v-switch.
10399 #define MC_CMD_VSWITCH_ALLOC 0x94
10400 #undef MC_CMD_0x94_PRIVILEGE_CTG
10402 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10404 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
10405 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16
10406 /* The port to connect to the v-switch's upstream port. */
10407 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
10408 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
10409 /* The type of v-switch to create. */
10410 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
10411 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
10413 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
10415 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
10416 /* enum: VEPA (obsolete) */
10417 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
10419 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
10420 /* enum: Snapper specific; semantics TBD */
10421 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
10422 /* Flags controlling v-port creation */
10423 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
10424 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
10425 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
10426 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
10427 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
10428 * this must be one or greated, and the attached v-ports must have exactly this
10429 * number of tags. For other v-switch types, this must be zero of greater, and
10430 * is an upper limit on the number of VLAN tags for attached v-ports. An error
10431 * will be returned if existing configuration means we can't support attached
10432 * v-ports with this number of tags.
10434 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
10435 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
10437 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
10438 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
10441 /***********************************/
10442 /* MC_CMD_VSWITCH_FREE
10443 * de-allocate a v-switch.
10445 #define MC_CMD_VSWITCH_FREE 0x95
10446 #undef MC_CMD_0x95_PRIVILEGE_CTG
10448 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10450 /* MC_CMD_VSWITCH_FREE_IN msgrequest */
10451 #define MC_CMD_VSWITCH_FREE_IN_LEN 4
10452 /* The port to which the v-switch is connected. */
10453 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
10454 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
10456 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */
10457 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0
10460 /***********************************/
10461 /* MC_CMD_VSWITCH_QUERY
10462 * read some config of v-switch. For now this command is an empty placeholder.
10463 * It may be used to check if a v-switch is connected to a given EVB port (if
10464 * not, then the command returns ENOENT).
10466 #define MC_CMD_VSWITCH_QUERY 0x63
10467 #undef MC_CMD_0x63_PRIVILEGE_CTG
10469 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10471 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */
10472 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4
10473 /* The port to which the v-switch is connected. */
10474 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
10475 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
10477 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */
10478 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0
10481 /***********************************/
10482 /* MC_CMD_VPORT_ALLOC
10483 * allocate a v-port.
10485 #define MC_CMD_VPORT_ALLOC 0x96
10486 #undef MC_CMD_0x96_PRIVILEGE_CTG
10488 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10490 /* MC_CMD_VPORT_ALLOC_IN msgrequest */
10491 #define MC_CMD_VPORT_ALLOC_IN_LEN 20
10492 /* The port to which the v-switch is connected. */
10493 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
10494 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
10495 /* The type of the new v-port. */
10496 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
10497 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
10498 /* enum: VLAN (obsolete) */
10499 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
10500 /* enum: VEB (obsolete) */
10501 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
10502 /* enum: VEPA (obsolete) */
10503 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
10504 /* enum: A normal v-port receives packets which match a specified MAC and/or
10507 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
10508 /* enum: An expansion v-port packets traffic which don't match any other
10511 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
10512 /* enum: An test v-port receives packets which match any filters installed by
10513 * its downstream components.
10515 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
10516 /* Flags controlling v-port creation */
10517 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
10518 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
10519 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
10520 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
10521 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
10522 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
10523 /* The number of VLAN tags to insert/remove. An error will be returned if
10524 * incompatible with the number of VLAN tags specified for the upstream
10527 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
10528 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
10529 /* The actual VLAN tags to insert/remove */
10530 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
10531 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
10532 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
10533 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
10534 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
10535 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
10537 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */
10538 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4
10539 /* The handle of the new v-port */
10540 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
10541 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
10544 /***********************************/
10545 /* MC_CMD_VPORT_FREE
10546 * de-allocate a v-port.
10548 #define MC_CMD_VPORT_FREE 0x97
10549 #undef MC_CMD_0x97_PRIVILEGE_CTG
10551 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10553 /* MC_CMD_VPORT_FREE_IN msgrequest */
10554 #define MC_CMD_VPORT_FREE_IN_LEN 4
10555 /* The handle of the v-port */
10556 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
10557 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
10559 /* MC_CMD_VPORT_FREE_OUT msgresponse */
10560 #define MC_CMD_VPORT_FREE_OUT_LEN 0
10563 /***********************************/
10564 /* MC_CMD_VADAPTOR_ALLOC
10565 * allocate a v-adaptor.
10567 #define MC_CMD_VADAPTOR_ALLOC 0x98
10568 #undef MC_CMD_0x98_PRIVILEGE_CTG
10570 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10572 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
10573 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30
10574 /* The port to connect to the v-adaptor's port. */
10575 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
10576 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
10577 /* Flags controlling v-adaptor creation */
10578 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
10579 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
10580 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
10581 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
10582 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
10583 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10584 /* The number of VLAN tags to strip on receive */
10585 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
10586 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
10587 /* The number of VLAN tags to transparently insert/remove. */
10588 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16
10589 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
10590 /* The actual VLAN tags to insert/remove */
10591 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
10592 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
10593 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
10594 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
10595 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
10596 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
10597 /* The MAC address to assign to this v-adaptor */
10598 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
10599 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
10600 /* enum: Derive the MAC address from the upstream port */
10601 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
10603 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
10604 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
10607 /***********************************/
10608 /* MC_CMD_VADAPTOR_FREE
10609 * de-allocate a v-adaptor.
10611 #define MC_CMD_VADAPTOR_FREE 0x99
10612 #undef MC_CMD_0x99_PRIVILEGE_CTG
10614 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10616 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */
10617 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4
10618 /* The port to which the v-adaptor is connected. */
10619 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
10620 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
10622 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
10623 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
10626 /***********************************/
10627 /* MC_CMD_VADAPTOR_SET_MAC
10628 * assign a new MAC address to a v-adaptor.
10630 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
10631 #undef MC_CMD_0x5d_PRIVILEGE_CTG
10633 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10635 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */
10636 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10
10637 /* The port to which the v-adaptor is connected. */
10638 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
10639 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
10640 /* The new MAC address to assign to this v-adaptor */
10641 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
10642 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6
10644 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */
10645 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
10648 /***********************************/
10649 /* MC_CMD_VADAPTOR_GET_MAC
10650 * read the MAC address assigned to a v-adaptor.
10652 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
10653 #undef MC_CMD_0x5e_PRIVILEGE_CTG
10655 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10657 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */
10658 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
10659 /* The port to which the v-adaptor is connected. */
10660 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
10661 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
10663 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */
10664 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6
10665 /* The MAC address assigned to this v-adaptor */
10666 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
10667 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6
10670 /***********************************/
10671 /* MC_CMD_VADAPTOR_QUERY
10672 * read some config of v-adaptor.
10674 #define MC_CMD_VADAPTOR_QUERY 0x61
10675 #undef MC_CMD_0x61_PRIVILEGE_CTG
10677 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10679 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */
10680 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
10681 /* The port to which the v-adaptor is connected. */
10682 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
10683 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
10685 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */
10686 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12
10687 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
10688 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
10689 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
10690 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
10691 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
10692 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
10693 /* The number of VLAN tags that may still be added */
10694 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8
10695 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
10698 /***********************************/
10699 /* MC_CMD_EVB_PORT_ASSIGN
10700 * assign a port to a PCI function.
10702 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
10703 #undef MC_CMD_0x9a_PRIVILEGE_CTG
10705 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10707 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
10708 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
10709 /* The port to assign. */
10710 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
10711 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
10712 /* The target function to modify. */
10713 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
10714 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
10715 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
10716 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
10717 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
10718 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
10720 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
10721 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
10724 /***********************************/
10725 /* MC_CMD_RDWR_A64_REGIONS
10726 * Assign the 64 bit region addresses.
10728 #define MC_CMD_RDWR_A64_REGIONS 0x9b
10729 #undef MC_CMD_0x9b_PRIVILEGE_CTG
10731 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
10733 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */
10734 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17
10735 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
10736 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
10737 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
10738 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
10739 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8
10740 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
10741 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12
10742 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
10743 /* Write enable bits 0-3, set to write, clear to read. */
10744 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128
10745 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
10746 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16
10747 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
10749 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included
10750 * regardless of state of write bits in the request.
10752 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16
10753 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
10754 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
10755 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
10756 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
10757 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8
10758 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
10759 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12
10760 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
10763 /***********************************/
10764 /* MC_CMD_ONLOAD_STACK_ALLOC
10765 * Allocate an Onload stack ID.
10767 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
10768 #undef MC_CMD_0x9c_PRIVILEGE_CTG
10770 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
10772 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */
10773 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
10774 /* The handle of the owning upstream port */
10775 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
10776 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
10778 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */
10779 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
10780 /* The handle of the new Onload stack */
10781 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
10782 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
10785 /***********************************/
10786 /* MC_CMD_ONLOAD_STACK_FREE
10787 * Free an Onload stack ID.
10789 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
10790 #undef MC_CMD_0x9d_PRIVILEGE_CTG
10792 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
10794 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */
10795 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
10796 /* The handle of the Onload stack */
10797 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
10798 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
10800 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */
10801 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
10804 /***********************************/
10805 /* MC_CMD_RSS_CONTEXT_ALLOC
10806 * Allocate an RSS context.
10808 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
10809 #undef MC_CMD_0x9e_PRIVILEGE_CTG
10811 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10813 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
10814 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
10815 /* The handle of the owning upstream port */
10816 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
10817 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
10818 /* The type of context to allocate */
10819 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
10820 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
10821 /* enum: Allocate a context for exclusive use. The key and indirection table
10822 * must be explicitly configured.
10824 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
10825 /* enum: Allocate a context for shared use; this will spread across a range of
10826 * queues, but the key and indirection table are pre-configured and may not be
10827 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
10829 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
10830 /* Number of queues spanned by this context, in the range 1-64; valid offsets
10831 * in the indirection table will be in the range 0 to NUM_QUEUES-1.
10833 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
10834 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
10836 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
10837 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
10838 /* The handle of the new RSS context. This should be considered opaque to the
10839 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
10842 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
10843 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
10844 /* enum: guaranteed invalid RSS context handle value */
10845 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
10848 /***********************************/
10849 /* MC_CMD_RSS_CONTEXT_FREE
10850 * Free an RSS context.
10852 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
10853 #undef MC_CMD_0x9f_PRIVILEGE_CTG
10855 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10857 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
10858 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
10859 /* The handle of the RSS context */
10860 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
10861 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
10863 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
10864 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
10867 /***********************************/
10868 /* MC_CMD_RSS_CONTEXT_SET_KEY
10869 * Set the Toeplitz hash key for an RSS context.
10871 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
10872 #undef MC_CMD_0xa0_PRIVILEGE_CTG
10874 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10876 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
10877 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
10878 /* The handle of the RSS context */
10879 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
10880 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
10881 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
10882 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
10883 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
10885 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
10886 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
10889 /***********************************/
10890 /* MC_CMD_RSS_CONTEXT_GET_KEY
10891 * Get the Toeplitz hash key for an RSS context.
10893 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
10894 #undef MC_CMD_0xa1_PRIVILEGE_CTG
10896 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10898 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
10899 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
10900 /* The handle of the RSS context */
10901 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
10902 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
10904 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
10905 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
10906 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
10907 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
10908 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
10911 /***********************************/
10912 /* MC_CMD_RSS_CONTEXT_SET_TABLE
10913 * Set the indirection table for an RSS context.
10915 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
10916 #undef MC_CMD_0xa2_PRIVILEGE_CTG
10918 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10920 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
10921 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
10922 /* The handle of the RSS context */
10923 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
10924 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
10925 /* The 128-byte indirection table (1 byte per entry) */
10926 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
10927 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
10929 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
10930 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
10933 /***********************************/
10934 /* MC_CMD_RSS_CONTEXT_GET_TABLE
10935 * Get the indirection table for an RSS context.
10937 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
10938 #undef MC_CMD_0xa3_PRIVILEGE_CTG
10940 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10942 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
10943 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
10944 /* The handle of the RSS context */
10945 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
10946 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
10948 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
10949 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
10950 /* The 128-byte indirection table (1 byte per entry) */
10951 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
10952 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
10955 /***********************************/
10956 /* MC_CMD_RSS_CONTEXT_SET_FLAGS
10957 * Set various control flags for an RSS context.
10959 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
10960 #undef MC_CMD_0xe1_PRIVILEGE_CTG
10962 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10964 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
10965 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
10966 /* The handle of the RSS context */
10967 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
10968 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
10969 /* Hash control flags. The _EN bits are always supported, but new modes are
10970 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:
10971 * in this case, the MODE fields may be set to non-zero values, and will take
10972 * effect regardless of the settings of the _EN flags. See the RSS_MODE
10973 * structure for the meaning of the mode bits. Drivers must check the
10974 * capability before trying to set any _MODE fields, as older firmware will
10975 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
10976 * the case where all the _MODE flags are zero, the _EN flags take effect,
10977 * providing backward compatibility for existing drivers. (Setting all _MODE
10978 * *and* all _EN flags to zero is valid, to disable RSS spreading for that
10979 * particular packet type.)
10981 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
10982 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
10983 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
10984 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
10985 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
10986 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
10987 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
10988 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
10989 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
10990 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
10991 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
10992 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
10993 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8
10994 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
10995 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12
10996 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
10997 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16
10998 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
10999 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20
11000 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
11001 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24
11002 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
11003 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28
11004 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
11006 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
11007 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
11010 /***********************************/
11011 /* MC_CMD_RSS_CONTEXT_GET_FLAGS
11012 * Get various control flags for an RSS context.
11014 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
11015 #undef MC_CMD_0xe2_PRIVILEGE_CTG
11017 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11019 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
11020 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
11021 /* The handle of the RSS context */
11022 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
11023 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
11025 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
11026 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
11027 /* Hash control flags. If all _MODE bits are zero (which will always be true
11028 * for older firmware which does not report the ADDITIONAL_RSS_MODES
11029 * capability), the _EN bits report the state. If any _MODE bits are non-zero
11030 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)
11031 * then the _EN bits should be disregarded, although the _MODE flags are
11032 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
11033 * context and in the case where the _EN flags were used in the SET. This
11034 * provides backward compatibility: old drivers will not be attempting to
11035 * derive any meaning from the _MODE bits (and can never set them to any value
11036 * not representable by the _EN bits); new drivers can always determine the
11037 * mode by looking only at the _MODE bits; the value returned by a GET can
11038 * always be used for a SET regardless of old/new driver vs. old/new firmware.
11040 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
11041 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
11042 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
11043 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
11044 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
11045 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
11046 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
11047 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
11048 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
11049 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
11050 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
11051 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
11052 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8
11053 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
11054 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12
11055 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
11056 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16
11057 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
11058 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20
11059 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
11060 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24
11061 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
11062 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28
11063 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
11066 /***********************************/
11067 /* MC_CMD_DOT1P_MAPPING_ALLOC
11068 * Allocate a .1p mapping.
11070 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
11071 #undef MC_CMD_0xa4_PRIVILEGE_CTG
11073 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11075 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */
11076 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8
11077 /* The handle of the owning upstream port */
11078 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11079 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
11080 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed
11081 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
11082 * referenced RSS contexts must span no more than this number.
11084 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
11085 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4
11087 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */
11088 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
11089 /* The handle of the new .1p mapping. This should be considered opaque to the
11090 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
11093 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
11094 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4
11095 /* enum: guaranteed invalid .1p mapping handle value */
11096 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
11099 /***********************************/
11100 /* MC_CMD_DOT1P_MAPPING_FREE
11101 * Free a .1p mapping.
11103 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
11104 #undef MC_CMD_0xa5_PRIVILEGE_CTG
11106 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11108 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */
11109 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
11110 /* The handle of the .1p mapping */
11111 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
11112 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4
11114 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */
11115 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
11118 /***********************************/
11119 /* MC_CMD_DOT1P_MAPPING_SET_TABLE
11120 * Set the mapping table for a .1p mapping.
11122 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
11123 #undef MC_CMD_0xa6_PRIVILEGE_CTG
11125 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11127 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */
11128 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36
11129 /* The handle of the .1p mapping */
11130 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
11131 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
11132 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
11135 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
11136 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32
11138 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */
11139 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
11142 /***********************************/
11143 /* MC_CMD_DOT1P_MAPPING_GET_TABLE
11144 * Get the mapping table for a .1p mapping.
11146 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
11147 #undef MC_CMD_0xa7_PRIVILEGE_CTG
11149 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11151 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */
11152 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
11153 /* The handle of the .1p mapping */
11154 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
11155 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
11157 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */
11158 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36
11159 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
11162 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
11163 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32
11166 /***********************************/
11167 /* MC_CMD_GET_VECTOR_CFG
11168 * Get Interrupt Vector config for this PF.
11170 #define MC_CMD_GET_VECTOR_CFG 0xbf
11171 #undef MC_CMD_0xbf_PRIVILEGE_CTG
11173 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11175 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
11176 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
11178 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
11179 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
11180 /* Base absolute interrupt vector number. */
11181 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
11182 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4
11183 /* Number of interrupt vectors allocate to this PF. */
11184 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
11185 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4
11186 /* Number of interrupt vectors to allocate per VF. */
11187 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
11188 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4
11191 /***********************************/
11192 /* MC_CMD_SET_VECTOR_CFG
11193 * Set Interrupt Vector config for this PF.
11195 #define MC_CMD_SET_VECTOR_CFG 0xc0
11196 #undef MC_CMD_0xc0_PRIVILEGE_CTG
11198 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11200 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
11201 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12
11202 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to
11203 * let the system find a suitable base.
11205 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
11206 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4
11207 /* Number of interrupt vectors allocate to this PF. */
11208 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
11209 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4
11210 /* Number of interrupt vectors to allocate per VF. */
11211 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
11212 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4
11214 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
11215 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
11218 /***********************************/
11219 /* MC_CMD_VPORT_ADD_MAC_ADDRESS
11220 * Add a MAC address to a v-port
11222 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
11223 #undef MC_CMD_0xa8_PRIVILEGE_CTG
11225 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11227 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
11228 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
11229 /* The handle of the v-port */
11230 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
11231 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
11232 /* MAC address to add */
11233 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
11234 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
11236 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
11237 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
11240 /***********************************/
11241 /* MC_CMD_VPORT_DEL_MAC_ADDRESS
11242 * Delete a MAC address from a v-port
11244 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
11245 #undef MC_CMD_0xa9_PRIVILEGE_CTG
11247 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11249 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
11250 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
11251 /* The handle of the v-port */
11252 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
11253 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
11254 /* MAC address to add */
11255 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
11256 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
11258 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
11259 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
11262 /***********************************/
11263 /* MC_CMD_VPORT_GET_MAC_ADDRESSES
11264 * Delete a MAC address from a v-port
11266 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
11267 #undef MC_CMD_0xaa_PRIVILEGE_CTG
11269 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11271 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
11272 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
11273 /* The handle of the v-port */
11274 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
11275 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
11277 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
11278 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
11279 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
11280 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
11281 /* The number of MAC addresses returned */
11282 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
11283 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
11284 /* Array of MAC addresses */
11285 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
11286 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
11287 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
11288 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
11291 /***********************************/
11292 /* MC_CMD_VPORT_RECONFIGURE
11293 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
11294 * has already been passed to another function (v-port's user), then that
11295 * function will be reset before applying the changes.
11297 #define MC_CMD_VPORT_RECONFIGURE 0xeb
11298 #undef MC_CMD_0xeb_PRIVILEGE_CTG
11300 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11302 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */
11303 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44
11304 /* The handle of the v-port */
11305 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
11306 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
11307 /* Flags requesting what should be changed. */
11308 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
11309 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
11310 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
11311 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
11312 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
11313 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
11314 /* The number of VLAN tags to insert/remove. An error will be returned if
11315 * incompatible with the number of VLAN tags specified for the upstream
11318 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8
11319 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
11320 /* The actual VLAN tags to insert/remove */
11321 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12
11322 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
11323 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
11324 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16
11325 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16
11326 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16
11327 /* The number of MAC addresses to add */
11328 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16
11329 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
11330 /* MAC addresses to add */
11331 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20
11332 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6
11333 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
11335 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */
11336 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
11337 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
11338 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
11339 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
11340 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
11343 /***********************************/
11344 /* MC_CMD_EVB_PORT_QUERY
11345 * read some config of v-port.
11347 #define MC_CMD_EVB_PORT_QUERY 0x62
11348 #undef MC_CMD_0x62_PRIVILEGE_CTG
11350 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11352 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */
11353 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4
11354 /* The handle of the v-port */
11355 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
11356 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
11358 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */
11359 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8
11360 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
11361 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
11362 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
11363 /* The number of VLAN tags that may be used on a v-adaptor connected to this
11366 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
11367 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
11370 /***********************************/
11371 /* MC_CMD_DUMP_BUFTBL_ENTRIES
11372 * Dump buffer table entries, mainly for command client debug use. Dumps
11373 * absolute entries, and does not use chunk handles. All entries must be in
11374 * range, and used for q page mapping, Although the latter restriction may be
11375 * lifted in future.
11377 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
11378 #undef MC_CMD_0xab_PRIVILEGE_CTG
11380 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11382 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */
11383 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8
11384 /* Index of the first buffer table entry. */
11385 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
11386 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
11387 /* Number of buffer table entries to dump. */
11388 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
11389 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
11391 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */
11392 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
11393 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
11394 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
11395 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
11396 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
11397 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
11398 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
11399 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21
11402 /***********************************/
11403 /* MC_CMD_SET_RXDP_CONFIG
11404 * Set global RXDP configuration settings
11406 #define MC_CMD_SET_RXDP_CONFIG 0xc1
11407 #undef MC_CMD_0xc1_PRIVILEGE_CTG
11409 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11411 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */
11412 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
11413 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
11414 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4
11415 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
11416 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
11417 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
11418 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2
11419 /* enum: pad to 64 bytes */
11420 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
11421 /* enum: pad to 128 bytes (Medford only) */
11422 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
11423 /* enum: pad to 256 bytes (Medford only) */
11424 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
11426 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */
11427 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
11430 /***********************************/
11431 /* MC_CMD_GET_RXDP_CONFIG
11432 * Get global RXDP configuration settings
11434 #define MC_CMD_GET_RXDP_CONFIG 0xc2
11435 #undef MC_CMD_0xc2_PRIVILEGE_CTG
11437 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11439 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */
11440 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
11442 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */
11443 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
11444 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
11445 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4
11446 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
11447 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
11448 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1
11449 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2
11450 /* Enum values, see field(s): */
11451 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */
11454 /***********************************/
11455 /* MC_CMD_GET_CLOCK
11456 * Return the system and PDCPU clock frequencies.
11458 #define MC_CMD_GET_CLOCK 0xac
11459 #undef MC_CMD_0xac_PRIVILEGE_CTG
11461 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11463 /* MC_CMD_GET_CLOCK_IN msgrequest */
11464 #define MC_CMD_GET_CLOCK_IN_LEN 0
11466 /* MC_CMD_GET_CLOCK_OUT msgresponse */
11467 #define MC_CMD_GET_CLOCK_OUT_LEN 8
11468 /* System frequency, MHz */
11469 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
11470 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
11471 /* DPCPU frequency, MHz */
11472 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
11473 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
11476 /***********************************/
11477 /* MC_CMD_SET_CLOCK
11478 * Control the system and DPCPU clock frequencies. Changes are lost reboot.
11480 #define MC_CMD_SET_CLOCK 0xad
11481 #undef MC_CMD_0xad_PRIVILEGE_CTG
11483 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11485 /* MC_CMD_SET_CLOCK_IN msgrequest */
11486 #define MC_CMD_SET_CLOCK_IN_LEN 28
11487 /* Requested frequency in MHz for system clock domain */
11488 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
11489 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4
11490 /* enum: Leave the system clock domain frequency unchanged */
11491 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
11492 /* Requested frequency in MHz for inter-core clock domain */
11493 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
11494 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4
11495 /* enum: Leave the inter-core clock domain frequency unchanged */
11496 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
11497 /* Requested frequency in MHz for DPCPU clock domain */
11498 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8
11499 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4
11500 /* enum: Leave the DPCPU clock domain frequency unchanged */
11501 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
11502 /* Requested frequency in MHz for PCS clock domain */
11503 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12
11504 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4
11505 /* enum: Leave the PCS clock domain frequency unchanged */
11506 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
11507 /* Requested frequency in MHz for MC clock domain */
11508 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16
11509 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4
11510 /* enum: Leave the MC clock domain frequency unchanged */
11511 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
11512 /* Requested frequency in MHz for rmon clock domain */
11513 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20
11514 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4
11515 /* enum: Leave the rmon clock domain frequency unchanged */
11516 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
11517 /* Requested frequency in MHz for vswitch clock domain */
11518 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24
11519 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4
11520 /* enum: Leave the vswitch clock domain frequency unchanged */
11521 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
11523 /* MC_CMD_SET_CLOCK_OUT msgresponse */
11524 #define MC_CMD_SET_CLOCK_OUT_LEN 28
11525 /* Resulting system frequency in MHz */
11526 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
11527 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4
11528 /* enum: The system clock domain doesn't exist */
11529 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
11530 /* Resulting inter-core frequency in MHz */
11531 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
11532 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4
11533 /* enum: The inter-core clock domain doesn't exist / isn't used */
11534 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
11535 /* Resulting DPCPU frequency in MHz */
11536 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8
11537 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4
11538 /* enum: The dpcpu clock domain doesn't exist */
11539 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
11540 /* Resulting PCS frequency in MHz */
11541 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12
11542 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4
11543 /* enum: The PCS clock domain doesn't exist / isn't controlled */
11544 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
11545 /* Resulting MC frequency in MHz */
11546 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16
11547 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4
11548 /* enum: The MC clock domain doesn't exist / isn't controlled */
11549 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
11550 /* Resulting rmon frequency in MHz */
11551 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20
11552 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4
11553 /* enum: The rmon clock domain doesn't exist / isn't controlled */
11554 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
11555 /* Resulting vswitch frequency in MHz */
11556 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24
11557 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4
11558 /* enum: The vswitch clock domain doesn't exist / isn't controlled */
11559 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
11562 /***********************************/
11563 /* MC_CMD_DPCPU_RPC
11564 * Send an arbitrary DPCPU message.
11566 #define MC_CMD_DPCPU_RPC 0xae
11567 #undef MC_CMD_0xae_PRIVILEGE_CTG
11569 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11571 /* MC_CMD_DPCPU_RPC_IN msgrequest */
11572 #define MC_CMD_DPCPU_RPC_IN_LEN 36
11573 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
11574 #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4
11575 /* enum: RxDPCPU0 */
11576 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
11577 /* enum: TxDPCPU0 */
11578 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
11579 /* enum: TxDPCPU1 */
11580 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
11581 /* enum: RxDPCPU1 (Medford only) */
11582 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
11583 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of
11586 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
11587 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of
11590 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
11591 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
11592 * initialised to zero
11594 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
11595 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
11596 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
11597 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
11598 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
11599 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
11600 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
11601 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
11602 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
11603 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
11604 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
11605 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
11606 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
11607 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
11608 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
11609 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
11610 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16
11611 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48
11612 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16
11613 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16
11614 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
11615 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
11616 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
11617 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
11618 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
11619 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
11620 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
11621 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
11622 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
11623 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
11624 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
11625 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16
11626 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80
11627 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
11628 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
11629 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
11630 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
11631 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
11632 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
11633 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
11634 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
11635 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
11636 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24
11637 /* Register data to write. Only valid in write/write-read. */
11638 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16
11639 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4
11640 /* Register address. */
11641 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20
11642 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4
11644 /* MC_CMD_DPCPU_RPC_OUT msgresponse */
11645 #define MC_CMD_DPCPU_RPC_OUT_LEN 36
11646 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
11647 #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4
11649 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
11650 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32
11651 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32
11652 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16
11653 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48
11654 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16
11655 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12
11656 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24
11657 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12
11658 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4
11659 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16
11660 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4
11661 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20
11662 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4
11663 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24
11664 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4
11667 /***********************************/
11668 /* MC_CMD_TRIGGER_INTERRUPT
11669 * Trigger an interrupt by prodding the BIU.
11671 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
11672 #undef MC_CMD_0xe3_PRIVILEGE_CTG
11674 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11676 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
11677 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
11678 /* Interrupt level relative to base for function. */
11679 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
11680 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
11682 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
11683 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
11686 /***********************************/
11687 /* MC_CMD_SHMBOOT_OP
11688 * Special operations to support (for now) shmboot.
11690 #define MC_CMD_SHMBOOT_OP 0xe6
11691 #undef MC_CMD_0xe6_PRIVILEGE_CTG
11693 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11695 /* MC_CMD_SHMBOOT_OP_IN msgrequest */
11696 #define MC_CMD_SHMBOOT_OP_IN_LEN 4
11697 /* Identifies the operation to perform */
11698 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
11699 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
11700 /* enum: Copy slave_data section to the slave core. (Greenport only) */
11701 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
11703 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */
11704 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0
11707 /***********************************/
11708 /* MC_CMD_CAP_BLK_READ
11709 * Read multiple 64bit words from capture block memory
11711 #define MC_CMD_CAP_BLK_READ 0xe7
11712 #undef MC_CMD_0xe7_PRIVILEGE_CTG
11714 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11716 /* MC_CMD_CAP_BLK_READ_IN msgrequest */
11717 #define MC_CMD_CAP_BLK_READ_IN_LEN 12
11718 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
11719 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4
11720 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
11721 #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4
11722 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8
11723 #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4
11725 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */
11726 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8
11727 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248
11728 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
11729 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
11730 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
11731 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
11732 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
11733 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
11734 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
11737 /***********************************/
11739 * Take a dump of the DUT state
11741 #define MC_CMD_DUMP_DO 0xe8
11742 #undef MC_CMD_0xe8_PRIVILEGE_CTG
11744 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11746 /* MC_CMD_DUMP_DO_IN msgrequest */
11747 #define MC_CMD_DUMP_DO_IN_LEN 52
11748 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
11749 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4
11750 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
11751 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
11752 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
11753 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
11754 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
11755 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
11756 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
11757 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
11758 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
11759 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
11760 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
11761 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
11762 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
11763 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
11764 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
11765 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
11766 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
11767 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
11768 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
11769 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
11770 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
11771 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
11772 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
11773 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
11774 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
11775 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
11776 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
11777 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
11778 /* enum: The uart port this command was received over (if using a uart
11781 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
11782 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
11783 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
11784 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
11785 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
11786 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
11787 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
11788 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
11789 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
11790 /* Enum values, see field(s): */
11791 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
11792 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
11793 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
11794 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
11795 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
11796 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
11797 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
11798 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
11799 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
11800 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
11801 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
11802 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
11803 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
11804 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
11805 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
11806 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
11807 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
11808 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
11809 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
11811 /* MC_CMD_DUMP_DO_OUT msgresponse */
11812 #define MC_CMD_DUMP_DO_OUT_LEN 4
11813 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
11814 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
11817 /***********************************/
11818 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED
11819 * Configure unsolicited dumps
11821 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
11822 #undef MC_CMD_0xe9_PRIVILEGE_CTG
11824 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11826 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */
11827 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52
11828 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
11829 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
11830 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
11831 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
11832 /* Enum values, see field(s): */
11833 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */
11834 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
11835 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
11836 /* Enum values, see field(s): */
11837 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
11838 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
11839 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
11840 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
11841 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
11842 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
11843 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
11844 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
11845 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
11846 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
11847 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
11848 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
11849 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
11850 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
11851 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
11852 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
11853 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
11854 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
11855 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
11856 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28
11857 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
11858 /* Enum values, see field(s): */
11859 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */
11860 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
11861 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
11862 /* Enum values, see field(s): */
11863 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
11864 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
11865 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
11866 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
11867 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
11868 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
11869 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
11870 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
11871 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
11872 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
11873 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
11874 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
11875 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
11876 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
11877 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
11878 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
11879 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
11880 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
11881 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
11884 /***********************************/
11886 * Adjusts power supply parameters. This is a warranty-voiding operation.
11887 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if
11888 * the parameter is out of range.
11890 #define MC_CMD_SET_PSU 0xea
11891 #undef MC_CMD_0xea_PRIVILEGE_CTG
11893 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
11895 /* MC_CMD_SET_PSU_IN msgrequest */
11896 #define MC_CMD_SET_PSU_IN_LEN 12
11897 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0
11898 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4
11899 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
11900 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4
11901 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4
11902 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
11903 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
11904 /* desired value, eg voltage in mV */
11905 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8
11906 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4
11908 /* MC_CMD_SET_PSU_OUT msgresponse */
11909 #define MC_CMD_SET_PSU_OUT_LEN 0
11912 /***********************************/
11913 /* MC_CMD_GET_FUNCTION_INFO
11914 * Get function information. PF and VF number.
11916 #define MC_CMD_GET_FUNCTION_INFO 0xec
11917 #undef MC_CMD_0xec_PRIVILEGE_CTG
11919 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11921 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
11922 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
11924 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
11925 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
11926 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
11927 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
11928 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
11929 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
11932 /***********************************/
11933 /* MC_CMD_ENABLE_OFFLINE_BIST
11934 * Enters offline BIST mode. All queues are torn down, chip enters quiescent
11935 * mode, calling function gets exclusive MCDI ownership. The only way out is
11938 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
11939 #undef MC_CMD_0xed_PRIVILEGE_CTG
11941 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
11943 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
11944 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
11946 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
11947 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
11950 /***********************************/
11951 /* MC_CMD_UART_SEND_DATA
11952 * Send checksummed[sic] block of data over the uart. Response is a placeholder
11953 * should we wish to make this reliable; currently requests are fire-and-
11956 #define MC_CMD_UART_SEND_DATA 0xee
11957 #undef MC_CMD_0xee_PRIVILEGE_CTG
11959 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11961 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */
11962 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16
11963 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252
11964 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
11965 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */
11966 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
11967 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
11968 /* Offset at which to write the data */
11969 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
11970 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4
11971 /* Length of data */
11972 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8
11973 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4
11974 /* Reserved for future use */
11975 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12
11976 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4
11977 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16
11978 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
11979 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
11980 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236
11982 /* MC_CMD_UART_SEND_DATA_IN msgresponse */
11983 #define MC_CMD_UART_SEND_DATA_IN_LEN 0
11986 /***********************************/
11987 /* MC_CMD_UART_RECV_DATA
11988 * Request checksummed[sic] block of data over the uart. Only a placeholder,
11989 * subject to change and not currently implemented.
11991 #define MC_CMD_UART_RECV_DATA 0xef
11992 #undef MC_CMD_0xef_PRIVILEGE_CTG
11994 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11996 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */
11997 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16
11998 /* CRC32 over OFFSET, LENGTH, RESERVED */
11999 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
12000 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4
12001 /* Offset from which to read the data */
12002 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
12003 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4
12004 /* Length of data */
12005 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8
12006 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4
12007 /* Reserved for future use */
12008 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12
12009 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4
12011 /* MC_CMD_UART_RECV_DATA_IN msgresponse */
12012 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16
12013 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252
12014 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
12015 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */
12016 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
12017 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
12018 /* Offset at which to write the data */
12019 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
12020 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4
12021 /* Length of data */
12022 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8
12023 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4
12024 /* Reserved for future use */
12025 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12
12026 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4
12027 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16
12028 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
12029 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
12030 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236
12033 /***********************************/
12034 /* MC_CMD_READ_FUSES
12035 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
12037 #define MC_CMD_READ_FUSES 0xf0
12038 #undef MC_CMD_0xf0_PRIVILEGE_CTG
12040 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
12042 /* MC_CMD_READ_FUSES_IN msgrequest */
12043 #define MC_CMD_READ_FUSES_IN_LEN 8
12044 /* Offset in OTP to read */
12045 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
12046 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
12047 /* Length of data to read in bytes */
12048 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
12049 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
12051 /* MC_CMD_READ_FUSES_OUT msgresponse */
12052 #define MC_CMD_READ_FUSES_OUT_LENMIN 4
12053 #define MC_CMD_READ_FUSES_OUT_LENMAX 252
12054 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
12055 /* Length of returned OTP data in bytes */
12056 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
12057 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
12058 /* Returned data */
12059 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
12060 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1
12061 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
12062 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
12065 /***********************************/
12067 * Get or set KR Serdes RXEQ and TX Driver settings
12069 #define MC_CMD_KR_TUNE 0xf1
12070 #undef MC_CMD_0xf1_PRIVILEGE_CTG
12072 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12074 /* MC_CMD_KR_TUNE_IN msgrequest */
12075 #define MC_CMD_KR_TUNE_IN_LENMIN 4
12076 #define MC_CMD_KR_TUNE_IN_LENMAX 252
12077 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
12078 /* Requested operation */
12079 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
12080 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
12081 /* enum: Get current RXEQ settings */
12082 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
12083 /* enum: Override RXEQ settings */
12084 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
12085 /* enum: Get current TX Driver settings */
12086 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
12087 /* enum: Override TX Driver settings */
12088 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
12089 /* enum: Force KR Serdes reset / recalibration */
12090 #define MC_CMD_KR_TUNE_IN_RECAL 0x4
12091 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
12094 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
12095 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
12096 * caller should call this command repeatedly after starting eye plot, until no
12097 * more data is returned.
12099 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
12100 /* enum: Read Figure Of Merit (eye quality, higher is better). */
12101 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
12102 /* Align the arguments to 32 bits */
12103 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
12104 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
12105 /* Arguments specific to the operation */
12106 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
12107 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
12108 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
12109 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
12111 /* MC_CMD_KR_TUNE_OUT msgresponse */
12112 #define MC_CMD_KR_TUNE_OUT_LEN 0
12114 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */
12115 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
12116 /* Requested operation */
12117 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
12118 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
12119 /* Align the arguments to 32 bits */
12120 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
12121 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
12123 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
12124 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
12125 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
12126 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
12127 /* RXEQ Parameter */
12128 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
12129 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
12130 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
12131 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
12132 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
12133 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
12134 /* enum: Attenuation (0-15, Huntington) */
12135 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
12136 /* enum: CTLE Boost (0-15, Huntington) */
12137 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
12138 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
12139 * positive, Medford - 0-31)
12141 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
12142 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
12143 * positive, Medford - 0-31)
12145 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
12146 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
12147 * positive, Medford - 0-16)
12149 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
12150 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
12151 * positive, Medford - 0-16)
12153 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
12154 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
12155 * positive, Medford - 0-16)
12157 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
12158 /* enum: Edge DFE DLEV (0-128 for Medford) */
12159 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
12160 /* enum: Variable Gain Amplifier (0-15, Medford) */
12161 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
12162 /* enum: CTLE EQ Capacitor (0-15, Medford) */
12163 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
12164 /* enum: CTLE EQ Resistor (0-7, Medford) */
12165 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
12166 /* enum: CTLE gain (0-31, Medford2) */
12167 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
12168 /* enum: CTLE pole (0-31, Medford2) */
12169 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
12170 /* enum: CTLE peaking (0-31, Medford2) */
12171 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
12172 /* enum: DFE Tap1 - even path (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12173 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
12174 /* enum: DFE Tap1 - odd path (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12175 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
12176 /* enum: DFE Tap2 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12177 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
12178 /* enum: DFE Tap3 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12179 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
12180 /* enum: DFE Tap4 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12181 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
12182 /* enum: DFE Tap5 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12183 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
12184 /* enum: DFE Tap6 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12185 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
12186 /* enum: DFE Tap7 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12187 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
12188 /* enum: DFE Tap8 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12189 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
12190 /* enum: DFE Tap9 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12191 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
12192 /* enum: DFE Tap10 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12193 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
12194 /* enum: DFE Tap11 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12195 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
12196 /* enum: DFE Tap12 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */
12197 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
12198 /* enum: I/Q clk offset (Medford2 - 0-5, sign-magnitude (-5 - +5)) */
12199 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
12200 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
12201 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
12202 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
12203 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
12204 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
12205 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
12206 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12207 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
12208 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
12209 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
12210 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
12211 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
12212 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
12213 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
12214 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
12216 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
12217 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
12218 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
12219 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
12220 /* Requested operation */
12221 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
12222 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
12223 /* Align the arguments to 32 bits */
12224 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
12225 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
12226 /* RXEQ Parameter */
12227 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
12228 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
12229 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
12230 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
12231 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
12232 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
12233 /* Enum values, see field(s): */
12234 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
12235 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
12236 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
12237 /* Enum values, see field(s): */
12238 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
12239 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
12240 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
12241 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
12242 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
12243 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
12244 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12245 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
12246 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
12248 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */
12249 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
12251 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */
12252 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
12253 /* Requested operation */
12254 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
12255 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
12256 /* Align the arguments to 32 bits */
12257 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
12258 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
12260 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */
12261 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
12262 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
12263 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
12264 /* TXEQ Parameter */
12265 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
12266 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
12267 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
12268 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
12269 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
12270 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
12271 /* enum: TX Amplitude (Huntington, Medford, Medford2) */
12272 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
12273 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
12274 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
12275 /* enum: De-Emphasis Tap1 Fine */
12276 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
12277 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
12278 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
12279 /* enum: De-Emphasis Tap2 Fine (Huntington) */
12280 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
12281 /* enum: Pre-Emphasis Magnitude (Huntington) */
12282 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
12283 /* enum: Pre-Emphasis Fine (Huntington) */
12284 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
12285 /* enum: TX Slew Rate Coarse control (Huntington) */
12286 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
12287 /* enum: TX Slew Rate Fine control (Huntington) */
12288 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
12289 /* enum: TX Termination Impedance control (Huntington) */
12290 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
12291 /* enum: TX Amplitude Fine control (Medford) */
12292 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
12293 /* enum: Pre-shoot Tap (Medford, Medford2) */
12294 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
12295 /* enum: De-emphasis Tap (Medford, Medford2) */
12296 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
12297 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
12298 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
12299 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
12300 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
12301 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
12302 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
12303 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12304 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
12305 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
12306 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
12307 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
12308 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24
12309 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8
12311 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */
12312 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8
12313 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
12314 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
12315 /* Requested operation */
12316 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
12317 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
12318 /* Align the arguments to 32 bits */
12319 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
12320 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
12321 /* TXEQ Parameter */
12322 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
12323 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
12324 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
12325 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62
12326 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
12327 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8
12328 /* Enum values, see field(s): */
12329 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */
12330 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8
12331 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3
12332 /* Enum values, see field(s): */
12333 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */
12334 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11
12335 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5
12336 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16
12337 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12338 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24
12339 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8
12341 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */
12342 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
12344 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */
12345 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
12346 /* Requested operation */
12347 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
12348 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
12349 /* Align the arguments to 32 bits */
12350 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
12351 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3
12353 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */
12354 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
12356 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */
12357 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8
12358 /* Requested operation */
12359 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
12360 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
12361 /* Align the arguments to 32 bits */
12362 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
12363 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
12364 /* Port-relative lane to scan eye on */
12365 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
12366 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
12368 /* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */
12369 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12
12370 /* Requested operation */
12371 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
12372 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1
12373 /* Align the arguments to 32 bits */
12374 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1
12375 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3
12376 /* Port-relative lane to scan eye on */
12377 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
12378 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
12379 /* Scan duration / cycle count */
12380 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8
12381 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
12383 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */
12384 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
12386 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */
12387 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
12388 /* Requested operation */
12389 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
12390 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
12391 /* Align the arguments to 32 bits */
12392 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
12393 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
12395 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */
12396 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
12397 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
12398 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
12399 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
12400 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
12401 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
12402 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
12404 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */
12405 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8
12406 /* Requested operation */
12407 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
12408 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1
12409 /* Align the arguments to 32 bits */
12410 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1
12411 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3
12412 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
12413 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
12415 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */
12416 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
12417 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
12418 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
12421 /***********************************/
12422 /* MC_CMD_PCIE_TUNE
12423 * Get or set PCIE Serdes RXEQ and TX Driver settings
12425 #define MC_CMD_PCIE_TUNE 0xf2
12426 #undef MC_CMD_0xf2_PRIVILEGE_CTG
12428 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12430 /* MC_CMD_PCIE_TUNE_IN msgrequest */
12431 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4
12432 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252
12433 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
12434 /* Requested operation */
12435 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
12436 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
12437 /* enum: Get current RXEQ settings */
12438 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
12439 /* enum: Override RXEQ settings */
12440 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
12441 /* enum: Get current TX Driver settings */
12442 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
12443 /* enum: Override TX Driver settings */
12444 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
12445 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */
12446 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
12447 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The
12448 * caller should call this command repeatedly after starting eye plot, until no
12449 * more data is returned.
12451 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
12452 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */
12453 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
12454 /* Align the arguments to 32 bits */
12455 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
12456 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3
12457 /* Arguments specific to the operation */
12458 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
12459 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
12460 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
12461 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62
12463 /* MC_CMD_PCIE_TUNE_OUT msgresponse */
12464 #define MC_CMD_PCIE_TUNE_OUT_LEN 0
12466 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */
12467 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
12468 /* Requested operation */
12469 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
12470 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
12471 /* Align the arguments to 32 bits */
12472 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
12473 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
12475 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */
12476 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
12477 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
12478 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
12479 /* RXEQ Parameter */
12480 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
12481 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
12482 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
12483 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
12484 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
12485 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
12486 /* enum: Attenuation (0-15) */
12487 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
12488 /* enum: CTLE Boost (0-15) */
12489 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
12490 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
12491 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
12492 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
12493 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
12494 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
12495 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
12496 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
12497 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
12498 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
12499 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
12500 /* enum: DFE DLev */
12501 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
12502 /* enum: Figure of Merit */
12503 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
12504 /* enum: CTLE EQ Capacitor (HF Gain) */
12505 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
12506 /* enum: CTLE EQ Resistor (DC Gain) */
12507 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
12508 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
12509 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5
12510 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
12511 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
12512 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
12513 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
12514 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
12515 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
12516 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
12517 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
12518 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
12519 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
12520 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
12521 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
12522 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
12523 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
12524 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
12525 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
12526 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
12527 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13
12528 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
12529 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14
12530 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10
12531 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
12532 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
12534 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */
12535 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8
12536 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252
12537 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
12538 /* Requested operation */
12539 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
12540 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
12541 /* Align the arguments to 32 bits */
12542 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1
12543 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3
12544 /* RXEQ Parameter */
12545 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4
12546 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
12547 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
12548 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
12549 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
12550 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
12551 /* Enum values, see field(s): */
12552 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */
12553 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
12554 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5
12555 /* Enum values, see field(s): */
12556 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
12557 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13
12558 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
12559 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14
12560 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2
12561 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
12562 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
12563 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
12564 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
12566 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */
12567 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0
12569 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */
12570 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
12571 /* Requested operation */
12572 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
12573 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
12574 /* Align the arguments to 32 bits */
12575 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
12576 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
12578 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */
12579 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
12580 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
12581 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
12582 /* RXEQ Parameter */
12583 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
12584 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
12585 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
12586 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
12587 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
12588 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
12589 /* enum: TxMargin (PIPE) */
12590 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
12591 /* enum: TxSwing (PIPE) */
12592 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
12593 /* enum: De-emphasis coefficient C(-1) (PIPE) */
12594 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
12595 /* enum: De-emphasis coefficient C(0) (PIPE) */
12596 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
12597 /* enum: De-emphasis coefficient C(+1) (PIPE) */
12598 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
12599 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
12600 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
12601 /* Enum values, see field(s): */
12602 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
12603 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12
12604 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12
12605 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24
12606 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
12608 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */
12609 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8
12610 /* Requested operation */
12611 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
12612 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
12613 /* Align the arguments to 32 bits */
12614 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
12615 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
12616 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
12617 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
12619 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */
12620 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
12622 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */
12623 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
12624 /* Requested operation */
12625 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
12626 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
12627 /* Align the arguments to 32 bits */
12628 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
12629 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
12631 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */
12632 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
12633 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
12634 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
12635 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
12636 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
12637 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
12638 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
12640 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */
12641 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0
12643 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */
12644 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0
12647 /***********************************/
12648 /* MC_CMD_LICENSING
12649 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
12650 * - not used for V3 licensing
12652 #define MC_CMD_LICENSING 0xf3
12653 #undef MC_CMD_0xf3_PRIVILEGE_CTG
12655 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12657 /* MC_CMD_LICENSING_IN msgrequest */
12658 #define MC_CMD_LICENSING_IN_LEN 4
12659 /* identifies the type of operation requested */
12660 #define MC_CMD_LICENSING_IN_OP_OFST 0
12661 #define MC_CMD_LICENSING_IN_OP_LEN 4
12662 /* enum: re-read and apply licenses after a license key partition update; note
12663 * that this operation returns a zero-length response
12665 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
12666 /* enum: report counts of installed licenses */
12667 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
12669 /* MC_CMD_LICENSING_OUT msgresponse */
12670 #define MC_CMD_LICENSING_OUT_LEN 28
12671 /* count of application keys which are valid */
12672 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
12673 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
12674 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
12675 * MC_CMD_FC_OP_LICENSE)
12677 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
12678 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
12679 /* count of application keys which are invalid due to being blacklisted */
12680 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
12681 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
12682 /* count of application keys which are invalid due to being unverifiable */
12683 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
12684 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
12685 /* count of application keys which are invalid due to being for the wrong node
12687 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
12688 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
12689 /* licensing state (for diagnostics; the exact meaning of the bits in this
12690 * field are private to the firmware)
12692 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
12693 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
12694 /* licensing subsystem self-test report (for manftest) */
12695 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
12696 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
12697 /* enum: licensing subsystem self-test failed */
12698 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
12699 /* enum: licensing subsystem self-test passed */
12700 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
12703 /***********************************/
12704 /* MC_CMD_LICENSING_V3
12705 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
12706 * - V3 licensing (Medford)
12708 #define MC_CMD_LICENSING_V3 0xd0
12709 #undef MC_CMD_0xd0_PRIVILEGE_CTG
12711 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12713 /* MC_CMD_LICENSING_V3_IN msgrequest */
12714 #define MC_CMD_LICENSING_V3_IN_LEN 4
12715 /* identifies the type of operation requested */
12716 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0
12717 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4
12718 /* enum: re-read and apply licenses after a license key partition update; note
12719 * that this operation returns a zero-length response
12721 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
12722 /* enum: report counts of installed licenses Returns EAGAIN if license
12723 * processing (updating) has been started but not yet completed.
12725 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
12727 /* MC_CMD_LICENSING_V3_OUT msgresponse */
12728 #define MC_CMD_LICENSING_V3_OUT_LEN 88
12729 /* count of keys which are valid */
12730 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
12731 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
12732 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with
12733 * MC_CMD_FC_OP_LICENSE)
12735 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
12736 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
12737 /* count of keys which are invalid due to being unverifiable */
12738 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8
12739 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
12740 /* count of keys which are invalid due to being for the wrong node */
12741 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12
12742 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
12743 /* licensing state (for diagnostics; the exact meaning of the bits in this
12744 * field are private to the firmware)
12746 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16
12747 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
12748 /* licensing subsystem self-test report (for manftest) */
12749 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20
12750 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
12751 /* enum: licensing subsystem self-test failed */
12752 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
12753 /* enum: licensing subsystem self-test passed */
12754 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
12755 /* bitmask of licensed applications */
12756 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
12757 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
12758 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
12759 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
12760 /* reserved for future use */
12761 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
12762 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
12763 /* bitmask of licensed features */
12764 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
12765 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
12766 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
12767 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
12768 /* reserved for future use */
12769 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
12770 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
12773 /***********************************/
12774 /* MC_CMD_LICENSING_GET_ID_V3
12775 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license
12776 * partition - V3 licensing (Medford)
12778 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
12779 #undef MC_CMD_0xd1_PRIVILEGE_CTG
12781 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12783 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */
12784 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
12786 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */
12787 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8
12788 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252
12789 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
12790 /* type of license (eg 3) */
12791 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
12792 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
12793 /* length of the license ID (in bytes) */
12794 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
12795 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
12796 /* the unique license ID of the adapter */
12797 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8
12798 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
12799 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
12800 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244
12803 /***********************************/
12804 /* MC_CMD_MC2MC_PROXY
12805 * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
12806 * This will fail on a single-core system.
12808 #define MC_CMD_MC2MC_PROXY 0xf4
12809 #undef MC_CMD_0xf4_PRIVILEGE_CTG
12811 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12813 /* MC_CMD_MC2MC_PROXY_IN msgrequest */
12814 #define MC_CMD_MC2MC_PROXY_IN_LEN 0
12816 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */
12817 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0
12820 /***********************************/
12821 /* MC_CMD_GET_LICENSED_APP_STATE
12822 * Query the state of an individual licensed application. (Note that the actual
12823 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation
12824 * or a reboot of the MC.) Not used for V3 licensing
12826 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
12827 #undef MC_CMD_0xf5_PRIVILEGE_CTG
12829 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12831 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */
12832 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
12833 /* application ID to query (LICENSED_APP_ID_xxx) */
12834 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
12835 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
12837 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */
12838 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
12839 /* state of this application */
12840 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
12841 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
12842 /* enum: no (or invalid) license is present for the application */
12843 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
12844 /* enum: a valid license is present for the application */
12845 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
12848 /***********************************/
12849 /* MC_CMD_GET_LICENSED_V3_APP_STATE
12850 * Query the state of an individual licensed application. (Note that the actual
12851 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
12852 * operation or a reboot of the MC.) Used for V3 licensing (Medford)
12854 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
12855 #undef MC_CMD_0xd2_PRIVILEGE_CTG
12857 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12859 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */
12860 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8
12861 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit
12864 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
12865 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
12866 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
12867 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
12869 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
12870 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
12871 /* state of this application */
12872 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
12873 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
12874 /* enum: no (or invalid) license is present for the application */
12875 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
12876 /* enum: a valid license is present for the application */
12877 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
12880 /***********************************/
12881 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES
12882 * Query the state of an one or more licensed features. (Note that the actual
12883 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
12884 * operation or a reboot of the MC.) Used for V3 licensing (Medford)
12886 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
12887 #undef MC_CMD_0xd3_PRIVILEGE_CTG
12889 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12891 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */
12892 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8
12893 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or
12896 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
12897 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
12898 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
12899 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
12901 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
12902 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
12903 /* states of these features - bit set for licensed, clear for not licensed */
12904 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
12905 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
12906 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
12907 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
12910 /***********************************/
12911 /* MC_CMD_LICENSED_APP_OP
12912 * Perform an action for an individual licensed application - not used for V3
12915 #define MC_CMD_LICENSED_APP_OP 0xf6
12916 #undef MC_CMD_0xf6_PRIVILEGE_CTG
12918 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12920 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */
12921 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8
12922 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
12923 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
12924 /* application ID */
12925 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
12926 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
12927 /* the type of operation requested */
12928 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
12929 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
12930 /* enum: validate application */
12931 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
12932 /* enum: mask application */
12933 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
12934 /* arguments specific to this particular operation */
12935 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8
12936 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
12937 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
12938 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61
12940 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */
12941 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
12942 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
12943 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
12944 /* result specific to this particular operation */
12945 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
12946 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
12947 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
12948 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63
12950 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */
12951 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72
12952 /* application ID */
12953 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
12954 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
12955 /* the type of operation requested */
12956 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
12957 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
12958 /* validation challenge */
12959 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8
12960 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64
12962 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */
12963 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68
12964 /* feature expiry (time_t) */
12965 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
12966 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
12967 /* validation response */
12968 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
12969 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64
12971 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */
12972 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12
12973 /* application ID */
12974 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
12975 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
12976 /* the type of operation requested */
12977 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
12978 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
12980 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8
12981 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
12983 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */
12984 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
12987 /***********************************/
12988 /* MC_CMD_LICENSED_V3_VALIDATE_APP
12989 * Perform validation for an individual licensed application - V3 licensing
12992 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
12993 #undef MC_CMD_0xd4_PRIVILEGE_CTG
12995 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12997 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */
12998 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56
12999 /* challenge for validation (384 bits) */
13000 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
13001 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48
13002 /* application ID expressed as a single bit mask */
13003 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
13004 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
13005 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
13006 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
13008 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
13009 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116
13010 /* validation response to challenge in the form of ECDSA signature consisting
13011 * of two 384-bit integers, r and s, in big-endian order. The signature signs a
13012 * SHA-384 digest of a message constructed from the concatenation of the input
13013 * message and the remaining fields of this output message, e.g. challenge[48
13014 * bytes] ... expiry_time[4 bytes] ...
13016 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
13017 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96
13018 /* application expiry time */
13019 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96
13020 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
13021 /* application expiry units */
13022 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100
13023 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
13024 /* enum: expiry units are accounting units */
13025 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
13026 /* enum: expiry units are calendar days */
13027 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
13028 /* base MAC address of the NIC stored in NVRAM (note that this is a constant
13029 * value for a given NIC regardless which function is calling, effectively this
13030 * is PF0 base MAC address)
13032 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104
13033 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6
13034 /* MAC address of v-adaptor associated with the client. If no such v-adapator
13035 * exists, then the field is filled with 0xFF.
13037 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110
13038 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6
13041 /***********************************/
13042 /* MC_CMD_LICENSED_V3_MASK_FEATURES
13043 * Mask features - V3 licensing (Medford)
13045 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
13046 #undef MC_CMD_0xd5_PRIVILEGE_CTG
13048 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13050 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */
13051 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12
13052 /* mask to be applied to features to be changed */
13053 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
13054 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
13055 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
13056 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
13057 /* whether to turn on or turn off the masked features */
13058 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
13059 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
13060 /* enum: turn the features off */
13061 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
13062 /* enum: turn the features back on */
13063 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
13065 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */
13066 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
13069 /***********************************/
13070 /* MC_CMD_LICENSING_V3_TEMPORARY
13071 * Perform operations to support installation of a single temporary license in
13072 * the adapter, in addition to those found in the licensing partition. See
13073 * SF-116124-SW for an overview of how this could be used. The license is
13074 * stored in MC persistent data and so will survive a MC reboot, but will be
13075 * erased when the adapter is power cycled
13077 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
13078 #undef MC_CMD_0xd6_PRIVILEGE_CTG
13080 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13082 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */
13083 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
13084 /* operation code */
13085 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
13086 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
13087 /* enum: install a new license, overwriting any existing temporary license.
13088 * This is an asynchronous operation owing to the time taken to validate an
13091 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
13092 /* enum: clear the license immediately rather than waiting for the next power
13095 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
13096 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET
13099 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
13101 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */
13102 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164
13103 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
13104 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
13105 /* ECDSA license and signature */
13106 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
13107 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160
13109 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */
13110 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
13111 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
13112 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
13114 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */
13115 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
13116 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
13117 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
13119 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */
13120 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12
13122 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
13123 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
13124 /* enum: finished validating and installing license */
13125 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
13126 /* enum: license validation and installation in progress */
13127 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
13128 /* enum: licensing error. More specific error messages are not provided to
13129 * avoid exposing details of the licensing system to the client
13131 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
13132 /* bitmask of licensed features */
13133 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
13134 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
13135 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
13136 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
13139 /***********************************/
13140 /* MC_CMD_SET_PORT_SNIFF_CONFIG
13141 * Configure RX port sniffing for the physical port associated with the calling
13142 * function. Only a privileged function may change the port sniffing
13143 * configuration. A copy of all traffic delivered to the host (non-promiscuous
13144 * mode) or all traffic arriving at the port (promiscuous mode) may be
13145 * delivered to a specific queue, or a set of queues with RSS.
13147 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
13148 #undef MC_CMD_0xf7_PRIVILEGE_CTG
13150 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13152 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */
13153 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16
13154 /* configuration flags */
13155 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
13156 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
13157 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
13158 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
13159 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
13160 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
13161 /* receive queue handle (for RSS mode, this is the base queue) */
13162 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
13163 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
13165 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
13166 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
13167 /* enum: receive to just the specified queue */
13168 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
13169 /* enum: receive to multiple queues using RSS context */
13170 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
13171 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
13172 * that these handles should be considered opaque to the host, although a value
13173 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
13175 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
13176 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
13178 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */
13179 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
13182 /***********************************/
13183 /* MC_CMD_GET_PORT_SNIFF_CONFIG
13184 * Obtain the current RX port sniffing configuration for the physical port
13185 * associated with the calling function. Only a privileged function may read
13186 * the configuration.
13188 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
13189 #undef MC_CMD_0xf8_PRIVILEGE_CTG
13191 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13193 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */
13194 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
13196 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */
13197 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16
13198 /* configuration flags */
13199 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
13200 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
13201 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
13202 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
13203 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
13204 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
13205 /* receiving queue handle (for RSS mode, this is the base queue) */
13206 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
13207 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
13209 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
13210 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
13211 /* enum: receiving to just the specified queue */
13212 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
13213 /* enum: receiving to multiple queues using RSS context */
13214 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
13215 /* RSS context (for RX_MODE_RSS) */
13216 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
13217 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
13220 /***********************************/
13221 /* MC_CMD_SET_PARSER_DISP_CONFIG
13222 * Change configuration related to the parser-dispatcher subsystem.
13224 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
13225 #undef MC_CMD_0xf9_PRIVILEGE_CTG
13227 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13229 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */
13230 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12
13231 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
13232 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
13233 /* the type of configuration setting to change */
13234 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
13235 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
13236 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
13237 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)
13239 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
13240 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
13241 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single
13244 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
13245 /* handle for the entity to update: queue handle, EVB port ID, etc. depending
13246 * on the type of configuration setting being changed
13248 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
13249 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
13250 /* new value: the details depend on the type of configuration setting being
13253 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8
13254 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
13255 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
13256 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61
13258 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */
13259 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
13262 /***********************************/
13263 /* MC_CMD_GET_PARSER_DISP_CONFIG
13264 * Read configuration related to the parser-dispatcher subsystem.
13266 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
13267 #undef MC_CMD_0xfa_PRIVILEGE_CTG
13269 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13271 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */
13272 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8
13273 /* the type of configuration setting to read */
13274 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
13275 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
13276 /* Enum values, see field(s): */
13277 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */
13278 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on
13279 * the type of configuration setting being read
13281 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
13282 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
13284 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */
13285 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
13286 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252
13287 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
13288 /* current value: the details depend on the type of configuration setting being
13291 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
13292 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
13293 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
13294 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63
13297 /***********************************/
13298 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG
13299 * Configure TX port sniffing for the physical port associated with the calling
13300 * function. Only a privileged function may change the port sniffing
13301 * configuration. A copy of all traffic transmitted through the port may be
13302 * delivered to a specific queue, or a set of queues with RSS. Note that these
13303 * packets are delivered with transmit timestamps in the packet prefix, not
13304 * receive timestamps, so it is likely that the queue(s) will need to be
13305 * dedicated as TX sniff receivers.
13307 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
13308 #undef MC_CMD_0xfb_PRIVILEGE_CTG
13310 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13312 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
13313 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16
13314 /* configuration flags */
13315 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
13316 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
13317 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
13318 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
13319 /* receive queue handle (for RSS mode, this is the base queue) */
13320 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
13321 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
13323 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
13324 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
13325 /* enum: receive to just the specified queue */
13326 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
13327 /* enum: receive to multiple queues using RSS context */
13328 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
13329 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
13330 * that these handles should be considered opaque to the host, although a value
13331 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
13333 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
13334 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
13336 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
13337 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0
13340 /***********************************/
13341 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG
13342 * Obtain the current TX port sniffing configuration for the physical port
13343 * associated with the calling function. Only a privileged function may read
13344 * the configuration.
13346 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
13347 #undef MC_CMD_0xfc_PRIVILEGE_CTG
13349 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13351 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
13352 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
13354 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */
13355 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16
13356 /* configuration flags */
13357 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
13358 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
13359 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
13360 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
13361 /* receiving queue handle (for RSS mode, this is the base queue) */
13362 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
13363 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
13365 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
13366 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
13367 /* enum: receiving to just the specified queue */
13368 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
13369 /* enum: receiving to multiple queues using RSS context */
13370 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
13371 /* RSS context (for RX_MODE_RSS) */
13372 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
13373 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
13376 /***********************************/
13377 /* MC_CMD_RMON_STATS_RX_ERRORS
13378 * Per queue rx error stats.
13380 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
13381 #undef MC_CMD_0xfe_PRIVILEGE_CTG
13383 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13385 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */
13386 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8
13387 /* The rx queue to get stats for. */
13388 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0
13389 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4
13390 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
13391 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4
13392 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
13393 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1
13395 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */
13396 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16
13397 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0
13398 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4
13399 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4
13400 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4
13401 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8
13402 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4
13403 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12
13404 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4
13407 /***********************************/
13408 /* MC_CMD_GET_PCIE_RESOURCE_INFO
13409 * Find out about available PCIE resources
13411 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
13412 #undef MC_CMD_0xfd_PRIVILEGE_CTG
13414 #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13416 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */
13417 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0
13419 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */
13420 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28
13421 /* The maximum number of PFs the device can expose */
13422 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0
13423 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4
13424 /* The maximum number of VFs the device can expose in total */
13425 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4
13426 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4
13427 /* The maximum number of MSI-X vectors the device can provide in total */
13428 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8
13429 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4
13430 /* the number of MSI-X vectors the device will allocate by default to each PF
13432 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12
13433 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4
13434 /* the number of MSI-X vectors the device will allocate by default to each VF
13436 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16
13437 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4
13438 /* the maximum number of MSI-X vectors the device can allocate to any one PF */
13439 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20
13440 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4
13441 /* the maximum number of MSI-X vectors the device can allocate to any one VF */
13442 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24
13443 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4
13446 /***********************************/
13447 /* MC_CMD_GET_PORT_MODES
13448 * Find out about available port modes
13450 #define MC_CMD_GET_PORT_MODES 0xff
13451 #undef MC_CMD_0xff_PRIVILEGE_CTG
13453 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13455 /* MC_CMD_GET_PORT_MODES_IN msgrequest */
13456 #define MC_CMD_GET_PORT_MODES_IN_LEN 0
13458 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */
13459 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12
13460 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */
13461 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
13462 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
13463 /* Default (canonical) board mode */
13464 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
13465 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
13466 /* Current board mode */
13467 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8
13468 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
13471 /***********************************/
13473 * Sample voltages on the ATB
13475 #define MC_CMD_READ_ATB 0x100
13476 #undef MC_CMD_0x100_PRIVILEGE_CTG
13478 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13480 /* MC_CMD_READ_ATB_IN msgrequest */
13481 #define MC_CMD_READ_ATB_IN_LEN 16
13482 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
13483 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4
13484 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
13485 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
13486 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
13487 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
13488 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4
13489 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8
13490 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4
13491 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12
13492 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4
13494 /* MC_CMD_READ_ATB_OUT msgresponse */
13495 #define MC_CMD_READ_ATB_OUT_LEN 4
13496 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0
13497 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4
13500 /***********************************/
13501 /* MC_CMD_GET_WORKAROUNDS
13502 * Read the list of all implemented and all currently enabled workarounds. The
13503 * enums here must correspond with those in MC_CMD_WORKAROUND.
13505 #define MC_CMD_GET_WORKAROUNDS 0x59
13506 #undef MC_CMD_0x59_PRIVILEGE_CTG
13508 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13510 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
13511 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
13512 /* Each workaround is represented by a single bit according to the enums below.
13514 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
13515 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
13516 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
13517 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
13518 /* enum: Bug 17230 work around. */
13519 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
13520 /* enum: Bug 35388 work around (unsafe EVQ writes). */
13521 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
13522 /* enum: Bug35017 workaround (A64 tables must be identity map) */
13523 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
13524 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
13525 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
13526 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
13527 * - before adding code that queries this workaround, remember that there's
13528 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
13529 * and will hence (incorrectly) report that the bug doesn't exist.
13531 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
13532 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */
13533 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
13534 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
13535 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
13538 /***********************************/
13539 /* MC_CMD_PRIVILEGE_MASK
13540 * Read/set privileges of an arbitrary PCIe function
13542 #define MC_CMD_PRIVILEGE_MASK 0x5a
13543 #undef MC_CMD_0x5a_PRIVILEGE_CTG
13545 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13547 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */
13548 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8
13549 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
13552 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
13553 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
13554 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
13555 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
13556 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
13557 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
13558 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
13559 /* New privilege mask to be set. The mask will only be changed if the MSB is
13562 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
13563 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
13564 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
13565 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
13566 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
13567 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
13568 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
13569 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
13570 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
13571 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
13572 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
13573 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
13574 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
13575 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
13576 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
13579 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
13580 /* enum: Privilege that allows a Function to change the MAC address configured
13581 * in its associated vAdapter/vPort.
13583 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
13584 /* enum: Privilege that allows a Function to install filters that specify VLANs
13585 * that are not in the permit list for the associated vPort. This privilege is
13586 * primarily to support ESX where vPorts are created that restrict traffic to
13587 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.
13589 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
13590 /* enum: Privilege for insecure commands. Commands that belong to this group
13591 * are not permitted on secure adapters regardless of the privilege mask.
13593 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
13594 /* enum: Set this bit to indicate that a new privilege mask is to be set,
13595 * otherwise the command will only read the existing mask.
13597 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
13599 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */
13600 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
13601 /* For an admin function, always all the privileges are reported. */
13602 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
13603 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
13606 /***********************************/
13607 /* MC_CMD_LINK_STATE_MODE
13608 * Read/set link state mode of a VF
13610 #define MC_CMD_LINK_STATE_MODE 0x5c
13611 #undef MC_CMD_0x5c_PRIVILEGE_CTG
13613 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13615 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */
13616 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8
13617 /* The target function to have its link state mode read or set, must be a VF
13618 * e.g. VF 1,3 = 0x00030001
13620 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
13621 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
13622 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
13623 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
13624 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
13625 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
13626 /* New link state mode to be set */
13627 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
13628 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
13629 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
13630 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
13631 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
13632 /* enum: Use this value to just read the existing setting without modifying it.
13634 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
13636 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
13637 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
13638 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
13639 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
13642 /***********************************/
13643 /* MC_CMD_GET_SNAPSHOT_LENGTH
13644 * Obtain the current range of allowable values for the SNAPSHOT_LENGTH
13645 * parameter to MC_CMD_INIT_RXQ.
13647 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
13648 #undef MC_CMD_0x101_PRIVILEGE_CTG
13650 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13652 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */
13653 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0
13655 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */
13656 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8
13657 /* Minimum acceptable snapshot length. */
13658 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0
13659 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4
13660 /* Maximum acceptable snapshot length. */
13661 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4
13662 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4
13665 /***********************************/
13666 /* MC_CMD_FUSE_DIAGS
13667 * Additional fuse diagnostics
13669 #define MC_CMD_FUSE_DIAGS 0x102
13670 #undef MC_CMD_0x102_PRIVILEGE_CTG
13672 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13674 /* MC_CMD_FUSE_DIAGS_IN msgrequest */
13675 #define MC_CMD_FUSE_DIAGS_IN_LEN 0
13677 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */
13678 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48
13679 /* Total number of mismatched bits between pairs in area 0 */
13680 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
13681 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
13682 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
13683 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
13684 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
13685 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
13686 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8
13687 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
13688 /* Checksum of data after logical OR of pairs in area 0 */
13689 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12
13690 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
13691 /* Total number of mismatched bits between pairs in area 1 */
13692 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16
13693 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
13694 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */
13695 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20
13696 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
13697 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */
13698 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24
13699 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
13700 /* Checksum of data after logical OR of pairs in area 1 */
13701 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28
13702 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
13703 /* Total number of mismatched bits between pairs in area 2 */
13704 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32
13705 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
13706 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */
13707 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36
13708 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
13709 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */
13710 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40
13711 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
13712 /* Checksum of data after logical OR of pairs in area 2 */
13713 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44
13714 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
13717 /***********************************/
13718 /* MC_CMD_PRIVILEGE_MODIFY
13719 * Modify the privileges of a set of PCIe functions. Note that this operation
13720 * only effects non-admin functions unless the admin privilege itself is
13721 * included in one of the masks provided.
13723 #define MC_CMD_PRIVILEGE_MODIFY 0x60
13724 #undef MC_CMD_0x60_PRIVILEGE_CTG
13726 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13728 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */
13729 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16
13730 /* The groups of functions to have their privilege masks modified. */
13731 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
13732 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
13733 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
13734 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
13735 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
13736 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
13737 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
13738 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
13739 /* For VFS_OF_PF specify the PF, for ONE specify the target function */
13740 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
13741 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
13742 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
13743 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16
13744 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16
13745 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16
13746 /* Privileges to be added to the target functions. For privilege definitions
13747 * refer to the command MC_CMD_PRIVILEGE_MASK
13749 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8
13750 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
13751 /* Privileges to be removed from the target functions. For privilege
13752 * definitions refer to the command MC_CMD_PRIVILEGE_MASK
13754 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12
13755 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
13757 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */
13758 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
13761 /***********************************/
13762 /* MC_CMD_XPM_READ_BYTES
13765 #define MC_CMD_XPM_READ_BYTES 0x103
13766 #undef MC_CMD_0x103_PRIVILEGE_CTG
13768 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
13770 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */
13771 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8
13772 /* Start address (byte) */
13773 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0
13774 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4
13775 /* Count (bytes) */
13776 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4
13777 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4
13779 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */
13780 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
13781 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252
13782 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
13784 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
13785 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
13786 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
13787 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252
13790 /***********************************/
13791 /* MC_CMD_XPM_WRITE_BYTES
13794 #define MC_CMD_XPM_WRITE_BYTES 0x104
13795 #undef MC_CMD_0x104_PRIVILEGE_CTG
13797 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13799 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */
13800 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8
13801 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252
13802 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
13803 /* Start address (byte) */
13804 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
13805 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
13806 /* Count (bytes) */
13807 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4
13808 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4
13810 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8
13811 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1
13812 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
13813 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244
13815 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */
13816 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
13819 /***********************************/
13820 /* MC_CMD_XPM_READ_SECTOR
13823 #define MC_CMD_XPM_READ_SECTOR 0x105
13824 #undef MC_CMD_0x105_PRIVILEGE_CTG
13826 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13828 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */
13829 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8
13831 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0
13832 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4
13834 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4
13835 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4
13837 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */
13838 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
13839 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36
13840 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
13842 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
13843 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
13844 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
13845 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
13846 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
13847 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
13848 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
13850 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
13851 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
13852 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
13853 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32
13856 /***********************************/
13857 /* MC_CMD_XPM_WRITE_SECTOR
13860 #define MC_CMD_XPM_WRITE_SECTOR 0x106
13861 #undef MC_CMD_0x106_PRIVILEGE_CTG
13863 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13865 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */
13866 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12
13867 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44
13868 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
13869 /* If writing fails due to an uncorrectable error, try up to RETRIES following
13870 * sectors (or until no more space available). If 0, only one write attempt is
13871 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
13874 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0
13875 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1
13876 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1
13877 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3
13879 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4
13880 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4
13881 /* Enum values, see field(s): */
13882 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */
13884 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8
13885 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4
13887 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12
13888 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1
13889 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
13890 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32
13892 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */
13893 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
13894 /* New sector index */
13895 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0
13896 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4
13899 /***********************************/
13900 /* MC_CMD_XPM_INVALIDATE_SECTOR
13901 * Invalidate XPM sector
13903 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
13904 #undef MC_CMD_0x107_PRIVILEGE_CTG
13906 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13908 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */
13909 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4
13911 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0
13912 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4
13914 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */
13915 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0
13918 /***********************************/
13919 /* MC_CMD_XPM_BLANK_CHECK
13920 * Blank-check XPM memory and report bad locations
13922 #define MC_CMD_XPM_BLANK_CHECK 0x108
13923 #undef MC_CMD_0x108_PRIVILEGE_CTG
13925 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13927 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */
13928 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8
13929 /* Start address (byte) */
13930 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0
13931 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4
13932 /* Count (bytes) */
13933 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4
13934 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4
13936 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */
13937 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
13938 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252
13939 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
13940 /* Total number of bad (non-blank) locations */
13941 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
13942 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
13943 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit
13944 * into MCDI response)
13946 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4
13947 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2
13948 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
13949 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124
13952 /***********************************/
13953 /* MC_CMD_XPM_REPAIR
13954 * Blank-check and repair XPM memory
13956 #define MC_CMD_XPM_REPAIR 0x109
13957 #undef MC_CMD_0x109_PRIVILEGE_CTG
13959 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13961 /* MC_CMD_XPM_REPAIR_IN msgrequest */
13962 #define MC_CMD_XPM_REPAIR_IN_LEN 8
13963 /* Start address (byte) */
13964 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0
13965 #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4
13966 /* Count (bytes) */
13967 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4
13968 #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4
13970 /* MC_CMD_XPM_REPAIR_OUT msgresponse */
13971 #define MC_CMD_XPM_REPAIR_OUT_LEN 0
13974 /***********************************/
13975 /* MC_CMD_XPM_DECODER_TEST
13976 * Test XPM memory address decoders for gross manufacturing defects. Can only
13977 * be performed on an unprogrammed part.
13979 #define MC_CMD_XPM_DECODER_TEST 0x10a
13980 #undef MC_CMD_0x10a_PRIVILEGE_CTG
13982 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
13984 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */
13985 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0
13987 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */
13988 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0
13991 /***********************************/
13992 /* MC_CMD_XPM_WRITE_TEST
13993 * XPM memory write test. Test XPM write logic for gross manufacturing defects
13994 * by writing to a dedicated test row. There are 16 locations in the test row
13995 * and the test can only be performed on locations that have not been
13996 * previously used (i.e. can be run at most 16 times). The test will pick the
13997 * first available location to use, or fail with ENOSPC if none left.
13999 #define MC_CMD_XPM_WRITE_TEST 0x10b
14000 #undef MC_CMD_0x10b_PRIVILEGE_CTG
14002 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE
14004 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */
14005 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0
14007 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */
14008 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0
14011 /***********************************/
14012 /* MC_CMD_EXEC_SIGNED
14013 * Check the CMAC of the contents of IMEM and DMEM against the value supplied
14014 * and if correct begin execution from the start of IMEM. The caller supplies a
14015 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC
14016 * computation runs from the start of IMEM, and from the start of DMEM + 16k,
14017 * to match flash booting. The command will respond with EINVAL if the CMAC
14018 * does match, otherwise it will respond with success before it jumps to IMEM.
14020 #define MC_CMD_EXEC_SIGNED 0x10c
14021 #undef MC_CMD_0x10c_PRIVILEGE_CTG
14023 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14025 /* MC_CMD_EXEC_SIGNED_IN msgrequest */
14026 #define MC_CMD_EXEC_SIGNED_IN_LEN 28
14027 /* the length of code to include in the CMAC */
14028 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0
14029 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4
14030 /* the length of date to include in the CMAC */
14031 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4
14032 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4
14033 /* the XPM sector containing the key to use */
14034 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8
14035 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4
14036 /* the expected CMAC value */
14037 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12
14038 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16
14040 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */
14041 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0
14044 /***********************************/
14045 /* MC_CMD_PREPARE_SIGNED
14046 * Prepare to upload a signed image. This will scrub the specified length of
14047 * the data region, which must be at least as large as the DATALEN supplied to
14048 * MC_CMD_EXEC_SIGNED.
14050 #define MC_CMD_PREPARE_SIGNED 0x10d
14051 #undef MC_CMD_0x10d_PRIVILEGE_CTG
14053 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14055 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */
14056 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4
14057 /* the length of data area to clear */
14058 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0
14059 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4
14061 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */
14062 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0
14065 /***********************************/
14066 /* MC_CMD_SET_SECURITY_RULE
14067 * Set blacklist and/or whitelist action for a particular match criteria.
14068 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
14069 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14070 * been used in any released code and may change during development. This note
14071 * will be removed once it is regarded as stable.
14073 #define MC_CMD_SET_SECURITY_RULE 0x10f
14074 #undef MC_CMD_0x10f_PRIVILEGE_CTG
14076 #define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14078 /* MC_CMD_SET_SECURITY_RULE_IN msgrequest */
14079 #define MC_CMD_SET_SECURITY_RULE_IN_LEN 92
14080 /* fields to include in match criteria */
14081 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0
14082 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_LEN 4
14083 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0
14084 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1
14085 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1
14086 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1
14087 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2
14088 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1
14089 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3
14090 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1
14091 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4
14092 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1
14093 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5
14094 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1
14095 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6
14096 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1
14097 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7
14098 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1
14099 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8
14100 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1
14101 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9
14102 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1
14103 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10
14104 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1
14105 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11
14106 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1
14107 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12
14108 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1
14109 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13
14110 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1
14111 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14
14112 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1
14113 /* remote MAC address to match (as bytes in network order) */
14114 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4
14115 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6
14116 /* remote port to match (as bytes in network order) */
14117 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10
14118 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2
14119 /* local MAC address to match (as bytes in network order) */
14120 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12
14121 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6
14122 /* local port to match (as bytes in network order) */
14123 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18
14124 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2
14125 /* Ethernet type to match (as bytes in network order) */
14126 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20
14127 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2
14128 /* Inner VLAN tag to match (as bytes in network order) */
14129 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22
14130 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2
14131 /* Outer VLAN tag to match (as bytes in network order) */
14132 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24
14133 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2
14134 /* IP protocol to match (in low byte; set high byte to 0) */
14135 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26
14136 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2
14137 /* Physical port to match (as little-endian 32-bit value) */
14138 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28
14139 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_LEN 4
14140 /* Reserved; set to 0 */
14141 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32
14142 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_LEN 4
14143 /* remote IP address to match (as bytes in network order; set last 12 bytes to
14144 * 0 for IPv4 address)
14146 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36
14147 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16
14148 /* local IP address to match (as bytes in network order; set last 12 bytes to 0
14149 * for IPv4 address)
14151 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52
14152 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16
14153 /* remote subnet ID to match (as little-endian 32-bit value); note that remote
14154 * subnets are matched by mapping the remote IP address to a "subnet ID" via a
14155 * data structure which must already have been configured using
14156 * MC_CMD_SUBNET_MAP_SET_NODE appropriately
14158 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68
14159 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_LEN 4
14160 /* remote portrange ID to match (as little-endian 32-bit value); note that
14161 * remote port ranges are matched by mapping the remote port to a "portrange
14162 * ID" via a data structure which must already have been configured using
14163 * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE
14165 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72
14166 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_LEN 4
14167 /* local portrange ID to match (as little-endian 32-bit value); note that local
14168 * port ranges are matched by mapping the local port to a "portrange ID" via a
14169 * data structure which must already have been configured using
14170 * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE
14172 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76
14173 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_LEN 4
14174 /* set the action for transmitted packets matching this rule */
14175 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80
14176 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_LEN 4
14177 /* enum: make no decision */
14178 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0
14179 /* enum: decide to accept the packet */
14180 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1
14181 /* enum: decide to drop the packet */
14182 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2
14183 /* enum: inform the TSA controller about some sample of packets matching this
14184 * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with
14185 * either the WHITELIST or BLACKLIST action
14187 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_SAMPLE 0x4
14188 /* enum: do not change the current TX action */
14189 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff
14190 /* set the action for received packets matching this rule */
14191 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84
14192 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_LEN 4
14193 /* enum: make no decision */
14194 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0
14195 /* enum: decide to accept the packet */
14196 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1
14197 /* enum: decide to drop the packet */
14198 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2
14199 /* enum: inform the TSA controller about some sample of packets matching this
14200 * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with
14201 * either the WHITELIST or BLACKLIST action
14203 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_SAMPLE 0x4
14204 /* enum: do not change the current RX action */
14205 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff
14206 /* counter ID to associate with this rule; IDs are allocated using
14207 * MC_CMD_SECURITY_RULE_COUNTER_ALLOC
14209 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88
14210 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_LEN 4
14211 /* enum: special value for the null counter ID */
14212 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0
14213 /* enum: special value to tell the MC to allocate an available counter */
14214 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_SW_AUTO 0xeeeeeeee
14215 /* enum: special value to request use of hardware counter (Medford2 only) */
14216 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_HW 0xffffffff
14218 /* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */
14219 #define MC_CMD_SET_SECURITY_RULE_OUT_LEN 32
14220 /* new reference count for uses of counter ID */
14221 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0
14222 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_LEN 4
14223 /* constructed match bits for this rule (as a tracing aid only) */
14224 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4
14225 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12
14226 /* constructed discriminator bits for this rule (as a tracing aid only) */
14227 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16
14228 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_LEN 4
14229 /* base location for probes for this rule (as a tracing aid only) */
14230 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20
14231 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_LEN 4
14232 /* step for probes for this rule (as a tracing aid only) */
14233 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24
14234 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_LEN 4
14235 /* ID for reading back the counter */
14236 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_OFST 28
14237 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_LEN 4
14240 /***********************************/
14241 /* MC_CMD_RESET_SECURITY_RULES
14242 * Reset all blacklist and whitelist actions for a particular physical port, or
14243 * all ports. (Medford-only; for use by SolarSecure apps, not directly by
14244 * drivers. See SF-114946-SW.) NOTE - this message definition is provisional.
14245 * It has not yet been used in any released code and may change during
14246 * development. This note will be removed once it is regarded as stable.
14248 #define MC_CMD_RESET_SECURITY_RULES 0x110
14249 #undef MC_CMD_0x110_PRIVILEGE_CTG
14251 #define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14253 /* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */
14254 #define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4
14255 /* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */
14256 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0
14257 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_LEN 4
14258 /* enum: special value to reset all physical ports */
14259 #define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff
14261 /* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */
14262 #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0
14265 /***********************************/
14266 /* MC_CMD_GET_SECURITY_RULESET_VERSION
14267 * Return a large hash value representing a "version" of the complete set of
14268 * currently active blacklist / whitelist rules and associated data structures.
14269 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
14270 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14271 * been used in any released code and may change during development. This note
14272 * will be removed once it is regarded as stable.
14274 #define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111
14275 #undef MC_CMD_0x111_PRIVILEGE_CTG
14277 #define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14279 /* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */
14280 #define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0
14282 /* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */
14283 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1
14284 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252
14285 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num))
14286 /* Opaque hash value; length may vary depending on the hash scheme used */
14287 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0
14288 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1
14289 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1
14290 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252
14293 /***********************************/
14294 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC
14295 * Allocate counters for use with blacklist / whitelist rules. (Medford-only;
14296 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.)
14297 * NOTE - this message definition is provisional. It has not yet been used in
14298 * any released code and may change during development. This note will be
14299 * removed once it is regarded as stable.
14301 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112
14302 #undef MC_CMD_0x112_PRIVILEGE_CTG
14304 #define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14306 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */
14307 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4
14308 /* the number of new counter IDs to request */
14309 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0
14310 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_LEN 4
14312 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */
14313 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4
14314 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252
14315 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num))
14316 /* the number of new counter IDs allocated (may be less than the number
14317 * requested if resources are unavailable)
14319 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0
14320 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_LEN 4
14321 /* new counter ID(s) */
14322 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4
14323 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4
14324 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0
14325 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62
14328 /***********************************/
14329 /* MC_CMD_SECURITY_RULE_COUNTER_FREE
14330 * Allocate counters for use with blacklist / whitelist rules. (Medford-only;
14331 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.)
14332 * NOTE - this message definition is provisional. It has not yet been used in
14333 * any released code and may change during development. This note will be
14334 * removed once it is regarded as stable.
14336 #define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113
14337 #undef MC_CMD_0x113_PRIVILEGE_CTG
14339 #define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14341 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */
14342 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4
14343 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252
14344 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num))
14345 /* the number of counter IDs to free */
14346 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0
14347 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_LEN 4
14348 /* the counter ID(s) to free */
14349 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4
14350 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4
14351 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0
14352 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62
14354 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */
14355 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0
14358 /***********************************/
14359 /* MC_CMD_SUBNET_MAP_SET_NODE
14360 * Atomically update a trie node in the map of subnets to subnet IDs. The
14361 * constants in the descriptions of the fields of this message may be retrieved
14362 * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford-
14363 * only; for use by SolarSecure apps, not directly by drivers. See
14364 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14365 * been used in any released code and may change during development. This note
14366 * will be removed once it is regarded as stable.
14368 #define MC_CMD_SUBNET_MAP_SET_NODE 0x114
14369 #undef MC_CMD_0x114_PRIVILEGE_CTG
14371 #define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14373 /* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */
14374 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6
14375 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252
14376 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num))
14377 /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */
14378 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0
14379 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_LEN 4
14380 /* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer
14381 * to the next node, expressed as an offset in the trie memory (i.e. node ID
14382 * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range
14383 * SUBNET_ID_MIN .. SUBNET_ID_MAX
14385 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4
14386 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2
14387 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1
14388 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124
14390 /* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */
14391 #define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0
14393 /* PORTRANGE_TREE_ENTRY structuredef */
14394 #define PORTRANGE_TREE_ENTRY_LEN 4
14395 /* key for branch nodes (<= key takes left branch, > key takes right branch),
14396 * or magic value for leaf nodes
14398 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0
14399 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2
14400 #define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */
14401 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0
14402 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16
14403 /* final portrange ID for leaf nodes (don't care for branch nodes) */
14404 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2
14405 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2
14406 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16
14407 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16
14410 /***********************************/
14411 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE
14412 * Atomically update the entire tree mapping remote port ranges to portrange
14413 * IDs. The constants in the descriptions of the fields of this message may be
14414 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO.
14415 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
14416 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14417 * been used in any released code and may change during development. This note
14418 * will be removed once it is regarded as stable.
14420 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115
14421 #undef MC_CMD_0x115_PRIVILEGE_CTG
14423 #define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14425 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */
14426 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4
14427 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252
14428 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))
14429 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a
14430 * PORTRANGE_TREE_ENTRY
14432 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0
14433 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4
14434 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1
14435 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63
14437 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */
14438 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0
14441 /***********************************/
14442 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE
14443 * Atomically update the entire tree mapping remote port ranges to portrange
14444 * IDs. The constants in the descriptions of the fields of this message may be
14445 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO.
14446 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
14447 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
14448 * been used in any released code and may change during development. This note
14449 * will be removed once it is regarded as stable.
14451 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116
14452 #undef MC_CMD_0x116_PRIVILEGE_CTG
14454 #define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14456 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */
14457 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4
14458 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252
14459 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))
14460 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a
14461 * PORTRANGE_TREE_ENTRY
14463 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0
14464 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4
14465 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1
14466 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63
14468 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */
14469 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0
14471 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */
14472 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
14473 /* UDP port (the standard ports are named below but any port may be used) */
14474 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
14475 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2
14476 /* enum: the IANA allocated UDP port for VXLAN */
14477 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
14478 /* enum: the IANA allocated UDP port for Geneve */
14479 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
14480 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
14481 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16
14482 /* tunnel encapsulation protocol (only those named below are supported) */
14483 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2
14484 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2
14485 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
14486 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
14487 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */
14488 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
14489 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16
14490 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16
14493 /***********************************/
14494 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS
14495 * Configure UDP ports for tunnel encapsulation hardware acceleration. The
14496 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
14497 * encapsulation PDUs and filter them using the tunnel encapsulation filter
14498 * chain rather than the standard filter chain. Note that this command can
14499 * cause all functions to see a reset. (Available on Medford only.)
14501 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
14502 #undef MC_CMD_0x117_PRIVILEGE_CTG
14504 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14506 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
14507 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
14508 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
14509 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
14511 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
14512 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
14513 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
14514 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
14515 /* The number of entries in the ENTRIES array */
14516 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2
14517 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2
14518 /* Entries defining the UDP port to protocol mapping, each laid out as a
14519 * TUNNEL_ENCAP_UDP_PORT_ENTRY
14521 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
14522 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
14523 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
14524 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
14526 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
14527 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
14529 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
14530 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
14531 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
14532 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
14535 /***********************************/
14536 /* MC_CMD_RX_BALANCING
14537 * Configure a port upconverter to distribute the packets on both RX engines.
14538 * Packets are distributed based on a table with the destination vFIFO. The
14539 * index of the table is a hash of source and destination of IPV4 and VLAN
14542 #define MC_CMD_RX_BALANCING 0x118
14543 #undef MC_CMD_0x118_PRIVILEGE_CTG
14545 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14547 /* MC_CMD_RX_BALANCING_IN msgrequest */
14548 #define MC_CMD_RX_BALANCING_IN_LEN 16
14549 /* The RX port whose upconverter table will be modified */
14550 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0
14551 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4
14552 /* The VLAN priority associated to the table index and vFIFO */
14553 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4
14554 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4
14555 /* The resulting bit of SRC^DST for indexing the table */
14556 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8
14557 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4
14558 /* The RX engine to which the vFIFO in the table entry will point to */
14559 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12
14560 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4
14562 /* MC_CMD_RX_BALANCING_OUT msgresponse */
14563 #define MC_CMD_RX_BALANCING_OUT_LEN 0
14566 /***********************************/
14568 * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more
14569 * info in respect to the binding protocol. This MCDI command is only available
14570 * over a TLS secure connection between the TSAN and TSAC, and is not available
14571 * to host software. Note- The messages definitions that do comprise this MCDI
14572 * command deemed as provisional. This MCDI command has not yet been used in
14573 * any released code and may change during development. This note will be
14574 * removed once it is regarded as stable.
14576 #define MC_CMD_TSA_BIND 0x119
14577 #undef MC_CMD_0x119_PRIVILEGE_CTG
14579 #define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14581 /* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */
14582 #define MC_CMD_TSA_BIND_IN_LEN 4
14583 #define MC_CMD_TSA_BIND_IN_OP_OFST 0
14584 #define MC_CMD_TSA_BIND_IN_OP_LEN 4
14585 /* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for
14586 * the network adapter. More specifically, TSAN ID equals the MAC address of
14587 * the network adapter. TSAN ID is used as part of the TSAN authentication
14588 * protocol. Refer to SF-114946-SW for more information.
14590 #define MC_CMD_TSA_BIND_OP_GET_ID 0x1
14591 /* enum: Get a binding ticket from the TSAN. The binding ticket is used as part
14592 * of the binding procedure to authorize the binding of an adapter to a TSAID.
14593 * Refer to SF-114946-SW for more information.
14595 #define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2
14596 /* enum: Opcode associated with the propagation of a private key that TSAN uses
14597 * as part of post-binding authentication procedure. More specifically, TSAN
14598 * uses this key for a signing operation. TSAC uses the counterpart public key
14599 * to verify the signature. Note - The post-binding authentication occurs when
14600 * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to
14601 * SF-114946-SW for more information.
14603 #define MC_CMD_TSA_BIND_OP_SET_KEY 0x3
14604 /* enum: Request an unbinding operation. Note- TSAN clears the binding ticket
14605 * from the Nvram section. Deprecated. Use MC_CMD_TSA_BIND_OP_UNBIND_EXT opcode
14606 * as indicated below.
14608 #define MC_CMD_TSA_BIND_OP_UNBIND 0x4
14609 /* enum: Opcode associated with the propagation of the unbinding ticket data
14610 * blob. The latest SF-115479-TC spec requires a more secure unbinding
14611 * procedure based on unbinding ticket. Note- The previous unbind operation
14612 * based on MC_CMD_TSA_BIND_OP_UNBIND remains in place but now deprecated.
14614 #define MC_CMD_TSA_BIND_OP_UNBIND_EXT 0x5
14615 /* enum: Opcode associated with the propagation of the unbinding secret token.
14616 * TSAN persists the unbinding secret token. Refer to SF-115479-TC for more
14619 #define MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN 0x6
14620 /* enum: Request a decommissioning operation. This is to force unbinding the
14621 * adapter. Note- This type of operation comes handy when keys other attributes
14622 * get corrupted at the database level on the controller side and not able to
14623 * unbind the adapter as part of a normal unbind procedure. Note- Refer to
14624 * SF-115479-TC for more information.
14626 #define MC_CMD_TSA_BIND_OP_DECOMMISSION 0x7
14627 /* enum: Request a certificate. */
14628 #define MC_CMD_TSA_BIND_OP_GET_CERTIFICATE 0x8
14630 /* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */
14631 #define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20
14632 /* The operation requested. */
14633 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0
14634 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_LEN 4
14635 /* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates
14636 * the nonce every time as part of the TSAN post-binding authentication
14637 * procedure when the TSAN-TSAC connection terminates and TSAN does need to re-
14638 * connect to the TSAC. Refer to SF-114946-SW for more information.
14640 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4
14641 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16
14643 /* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */
14644 #define MC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4
14645 /* The operation requested. */
14646 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0
14647 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_LEN 4
14649 /* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */
14650 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5
14651 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252
14652 #define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num))
14653 /* The operation requested. */
14654 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0
14655 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_LEN 4
14656 /* This data blob contains the private key generated by the TSAC. TSAN uses
14657 * this key for a signing operation. Note- This private key is used in
14658 * conjunction with the post-binding TSAN authentication procedure that occurs
14659 * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer
14660 * to SF-114946-SW for more information.
14662 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4
14663 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1
14664 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1
14665 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248
14667 /* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure
14668 * Deprecated. Use MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest as indicated below.
14670 #define MC_CMD_TSA_BIND_IN_UNBIND_LEN 10
14671 /* The operation requested. */
14672 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0
14673 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_LEN 4
14674 /* TSAN unique identifier for the network adapter */
14675 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4
14676 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6
14678 /* MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest: Asks for the un-binding procedure
14680 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMIN 93
14681 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMAX 252
14682 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LEN(num) (92+1*(num))
14683 /* The operation requested. */
14684 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_OFST 0
14685 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_LEN 4
14686 /* TSAN unique identifier for the network adapter */
14687 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_OFST 4
14688 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_LEN 6
14689 /* Align the arguments to 32 bits */
14690 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_OFST 10
14691 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_LEN 2
14692 /* This attribute identifies the TSA infrastructure domain. The length of the
14693 * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max
14694 * length. Note- The TSAID is the Organizational Unit Name filed as part of the
14695 * root and server certificates.
14697 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_OFST 12
14698 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_LEN 1
14699 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_NUM 64
14700 /* Unbinding secret token. The adapter validates this unbinding token by
14701 * comparing it against the one stored on the adapter as part of the
14702 * MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest. Refer to SF-115479-TC for
14703 * more information.
14705 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_OFST 76
14706 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_LEN 16
14707 /* This is the signature of the above mentioned fields- TSANID, TSAID and
14708 * UNBINDTOKEN. As per current requirements, the SIG opaque data blob contains
14709 * ECDSA ECC-384 based signature. The ECC curve is secp384r1. The signature is
14710 * also ASN-1 encoded. Note- The signature is verified based on the public key
14711 * stored into the root certificate that is provisioned on the adapter side.
14712 * This key is known as the PUKtsaid. Refer to SF-115479-TC for more
14715 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_OFST 92
14716 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_LEN 1
14717 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MINNUM 1
14718 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MAXNUM 160
14720 /* MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest */
14721 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_LEN 20
14722 /* The operation requested. */
14723 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_OFST 0
14724 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_LEN 4
14725 /* Unbinding secret token. TSAN persists the unbinding secret token. Refer to
14726 * SF-115479-TC for more information.
14728 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_OFST 4
14729 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_LEN 16
14730 /* enum: There are situations when the binding process does not complete
14731 * successfully due to key, other attributes corruption at the database level
14732 * (Controller). Adapter can't connect to the controller anymore. To recover,
14733 * make usage of the decommission command that forces the adapter into
14736 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_ADAPTER_BINDING_FAILURE 0x1
14738 /* MC_CMD_TSA_BIND_IN_DECOMMISSION msgrequest: Asks for the decommissioning
14741 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMIN 109
14742 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMAX 252
14743 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LEN(num) (108+1*(num))
14744 /* This is the signature of the above mentioned fields- TSAID, USER and REASON.
14745 * As per current requirements, the SIG opaque data blob contains ECDSA ECC-384
14746 * based signature. The ECC curve is secp384r1. The signature is also ASN-1
14747 * encoded . Note- The signature is verified based on the public key stored
14748 * into the root certificate that is provisioned on the adapter side. This key
14749 * is known as the PUKtsaid. Refer to SF-115479-TC for more information.
14751 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_OFST 108
14752 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_LEN 1
14753 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MINNUM 1
14754 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MAXNUM 144
14755 /* The operation requested. */
14756 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_OFST 0
14757 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_LEN 4
14758 /* This attribute identifies the TSA infrastructure domain. The length of the
14759 * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max
14760 * length. Note- The TSAID is the Organizational Unit Name filed as part of the
14761 * root and server certificates.
14763 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_OFST 4
14764 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_LEN 1
14765 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_NUM 64
14766 /* User ID that comes, as an example, from the Controller. Note- The 33 byte
14767 * length of this attribute is max length of the linux user name plus null
14770 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_OFST 68
14771 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_LEN 1
14772 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_NUM 33
14773 /* Align the arguments to 32 bits */
14774 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_OFST 101
14775 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_LEN 3
14776 /* Reason of why decommissioning happens Note- The list of reasons, defined as
14777 * part of the enumeration below, can be extended.
14779 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_OFST 104
14780 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_LEN 4
14782 /* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE msgrequest: Request a certificate. */
14783 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_LEN 8
14784 /* The operation requested, must be MC_CMD_TSA_BIND_OP_GET_CERTIFICATE. */
14785 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_OFST 0
14786 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_LEN 4
14787 /* Type of the certificate to be retrieved. */
14788 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_OFST 4
14789 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_LEN 4
14790 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_UNUSED 0x0 /* enum */
14791 /* enum: Adapter Authentication Certificate (AAC). The AAC is used by the
14792 * controller to verify the authenticity of the adapter.
14794 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AAC 0x1
14795 /* enum: Adapter Authentication Signing Certificate (AASC). The AASC is used by
14796 * the controller to verify the validity of AAC.
14798 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AASC 0x2
14800 /* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */
14801 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15
14802 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252
14803 #define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num))
14804 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_ID that is sent back to
14807 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0
14808 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_LEN 4
14809 /* Rules engine type. Note- The rules engine type allows TSAC to further
14810 * identify the connected endpoint (e.g. TSAN, NIC Emulator) type and take the
14811 * proper action accordingly. As an example, TSAC uses the rules engine type to
14812 * select the SF key that differs in the case of TSAN vs. NIC Emulator.
14814 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_OFST 4
14815 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_LEN 4
14816 /* enum: Hardware rules engine. */
14817 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1
14818 /* enum: Nic emulator rules engine. */
14819 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_NEMU 0x2
14821 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_SSFE 0x3
14822 /* TSAN unique identifier for the network adapter */
14823 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 8
14824 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6
14825 /* The signature data blob. The signature is computed against the message
14826 * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC
14827 * for more information also in respect to the private keys that are used to
14828 * sign the message based on TSAN pre/post-binding authentication procedure.
14830 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 14
14831 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1
14832 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1
14833 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 238
14835 /* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */
14836 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5
14837 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252
14838 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num))
14839 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_TICKET that is sent back
14842 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0
14843 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_LEN 4
14844 /* The ticket represents the data blob construct that TSAN sends to TSAC as
14845 * part of the binding protocol. From the TSAN perspective the ticket is an
14846 * opaque construct. For more info refer to SF-115479-TC.
14848 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4
14849 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1
14850 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1
14851 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248
14853 /* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */
14854 #define MC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4
14855 /* The protocol operation code MC_CMD_TSA_BIND_OP_SET_KEY that is sent back to
14858 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0
14859 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_LEN 4
14861 /* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse: Response to insecure unbind request.
14863 #define MC_CMD_TSA_BIND_OUT_UNBIND_LEN 8
14864 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
14865 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0
14866 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_LEN 4
14867 /* Extra status information */
14868 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4
14869 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_LEN 4
14870 /* enum: Unbind successful. */
14871 #define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0
14872 /* enum: TSANID mismatch */
14873 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1
14874 /* enum: Unable to remove the binding ticket from persistent storage. */
14875 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2
14876 /* enum: TSAN is not bound to a binding ticket. */
14877 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3
14879 /* MC_CMD_TSA_BIND_OUT_UNBIND_EXT msgresponse: Response to secure unbind
14880 * request. (Note! This has same fields as insecure unbind response but is a
14881 * response to a different command.)
14883 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_LEN 8
14884 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
14885 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_OFST 0
14886 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_LEN 4
14887 /* Extra status information */
14888 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_OFST 4
14889 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_LEN 4
14890 /* enum: Unbind successful. */
14891 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_OK_UNBOUND 0x0
14892 /* enum: TSANID mismatch */
14893 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TSANID 0x1
14894 /* enum: Unable to remove the binding ticket from persistent storage. */
14895 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_REMOVE_TICKET 0x2
14896 /* enum: TSAN is not bound to a binding ticket. */
14897 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_NOT_BOUND 0x3
14898 /* enum: Invalid unbind token */
14899 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TOKEN 0x4
14900 /* enum: Invalid signature */
14901 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_SIGNATURE 0x5
14903 /* MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN msgresponse */
14904 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_LEN 4
14905 /* The protocol operation code MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN that is sent
14906 * back to the caller.
14908 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_OFST 0
14909 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_LEN 4
14911 /* MC_CMD_TSA_BIND_OUT_DECOMMISSION msgresponse */
14912 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_LEN 4
14913 /* The protocol operation code MC_CMD_TSA_BIND_OP_DECOMMISSION that is sent
14914 * back to the caller.
14916 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_OFST 0
14917 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_LEN 4
14919 /* MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE msgresponse */
14920 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMIN 9
14921 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMAX 252
14922 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LEN(num) (8+1*(num))
14923 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_CERTIFICATE that is sent
14924 * back to the caller.
14926 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_OFST 0
14927 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_LEN 4
14928 /* Type of the certificate. */
14929 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_OFST 4
14930 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_LEN 4
14931 /* Enum values, see field(s): */
14932 /* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE/TYPE */
14933 /* The certificate data. */
14934 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_OFST 8
14935 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_LEN 1
14936 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MINNUM 1
14937 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MAXNUM 244
14940 /***********************************/
14941 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE
14942 * Manage the persistent NVRAM cache of security rules created with
14943 * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated
14944 * as rules are added or removed; the active ruleset must be explicitly
14945 * committed to the cache. The cache may also be explicitly invalidated,
14946 * without affecting the currently active ruleset. When the cache is valid, it
14947 * will be loaded at power on or MC reboot, instead of the default ruleset.
14948 * Rollback of the currently active ruleset to the cached version (when it is
14949 * valid) is also supported. (Medford-only; for use by SolarSecure apps, not
14950 * directly by drivers. See SF-114946-SW.) NOTE - this message definition is
14951 * provisional. It has not yet been used in any released code and may change
14952 * during development. This note will be removed once it is regarded as stable.
14954 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a
14955 #undef MC_CMD_0x11a_PRIVILEGE_CTG
14957 #define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
14959 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */
14960 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4
14961 /* the operation to perform */
14962 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0
14963 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_LEN 4
14964 /* enum: reports the ruleset version that is cached in persistent storage but
14965 * performs no other action
14967 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0
14968 /* enum: rolls back the active state to the cached version. (May fail with
14969 * ENOENT if there is no valid cached version.)
14971 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1
14972 /* enum: commits the active state to the persistent cache */
14973 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2
14974 /* enum: invalidates the persistent cache without affecting the active state */
14975 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3
14977 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */
14978 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5
14979 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252
14980 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num))
14981 /* indicates whether the persistent cache is valid (after completion of the
14982 * requested operation in the case of rollback, commit, or invalidate)
14984 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0
14985 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_LEN 4
14986 /* enum: persistent cache is invalid (the VERSION field will be empty in this
14989 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0
14990 /* enum: persistent cache is valid */
14991 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1
14992 /* cached ruleset version (after completion of the requested operation, in the
14993 * case of rollback, commit, or invalidate) as an opaque hash value in the same
14994 * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION
14996 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4
14997 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1
14998 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1
14999 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248
15002 /***********************************/
15003 /* MC_CMD_NVRAM_PRIVATE_APPEND
15004 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST
15005 * if the tag is already present.
15007 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
15008 #undef MC_CMD_0x11c_PRIVILEGE_CTG
15010 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15012 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */
15013 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9
15014 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252
15015 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
15016 /* The tag to be appended */
15017 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
15018 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
15019 /* The length of the data */
15020 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4
15021 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4
15022 /* The data to be contained in the TLV structure */
15023 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8
15024 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1
15025 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1
15026 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244
15028 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */
15029 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
15032 /***********************************/
15033 /* MC_CMD_XPM_VERIFY_CONTENTS
15034 * Verify that the contents of the XPM memory is correct (Medford only). This
15035 * is used during manufacture to check that the XPM memory has been programmed
15036 * correctly at ATE.
15038 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
15039 #undef MC_CMD_0x11b_PRIVILEGE_CTG
15041 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15043 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */
15044 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4
15045 /* Data type to be checked */
15046 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0
15047 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4
15049 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */
15050 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12
15051 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252
15052 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
15053 /* Number of sectors found (test builds only) */
15054 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
15055 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
15056 /* Number of bytes found (test builds only) */
15057 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4
15058 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4
15059 /* Length of signature */
15060 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8
15061 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4
15063 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12
15064 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1
15065 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
15066 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240
15069 /***********************************/
15070 /* MC_CMD_SET_EVQ_TMR
15071 * Update the timer load, timer reload and timer mode values for a given EVQ.
15072 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will
15073 * be rounded up to the granularity supported by the hardware, then truncated
15074 * to the range supported by the hardware. The resulting value after the
15075 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS
15076 * and TMR_RELOAD_ACT_NS).
15078 #define MC_CMD_SET_EVQ_TMR 0x120
15079 #undef MC_CMD_0x120_PRIVILEGE_CTG
15081 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15083 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */
15084 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16
15085 /* Function-relative queue instance */
15086 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
15087 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
15088 /* Requested value for timer load (in nanoseconds) */
15089 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
15090 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
15091 /* Requested value for timer reload (in nanoseconds) */
15092 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8
15093 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
15094 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */
15095 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12
15096 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
15097 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
15098 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
15099 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
15100 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
15102 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */
15103 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8
15104 /* Actual value for timer load (in nanoseconds) */
15105 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
15106 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
15107 /* Actual value for timer reload (in nanoseconds) */
15108 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
15109 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
15112 /***********************************/
15113 /* MC_CMD_GET_EVQ_TMR_PROPERTIES
15114 * Query properties about the event queue timers.
15116 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
15117 #undef MC_CMD_0x122_PRIVILEGE_CTG
15119 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15121 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */
15122 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
15124 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */
15125 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36
15126 /* Reserved for future use. */
15127 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
15128 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
15129 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in
15130 * nanoseconds) for each increment of the timer load/reload count. The
15131 * requested duration of a timer is this value multiplied by the timer
15132 * load/reload count.
15134 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
15135 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
15136 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value
15137 * allowed for timer load/reload counts.
15139 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8
15140 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
15141 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a
15142 * multiple of this step size will be rounded in an implementation defined
15145 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12
15146 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
15147 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only
15148 * meaningful if MC_CMD_SET_EVQ_TMR is implemented.
15150 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16
15151 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
15152 /* Timer durations requested via MCDI that are not a multiple of this step size
15153 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented.
15155 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20
15156 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
15157 /* For timers updated using the bug35388 workaround, this is the time interval
15158 * (in nanoseconds) for each increment of the timer load/reload count. The
15159 * requested duration of a timer is this value multiplied by the timer
15160 * load/reload count. This field is only meaningful if the bug35388 workaround
15163 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24
15164 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
15165 /* For timers updated using the bug35388 workaround, this is the maximum value
15166 * allowed for timer load/reload counts. This field is only meaningful if the
15167 * bug35388 workaround is enabled.
15169 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28
15170 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
15171 /* For timers updated using the bug35388 workaround, timer load/reload counts
15172 * not a multiple of this step size will be rounded in an implementation
15173 * defined manner. This field is only meaningful if the bug35388 workaround is
15176 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32
15177 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
15180 /***********************************/
15181 /* MC_CMD_ALLOCATE_TX_VFIFO_CP
15182 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the
15183 * non used switch buffers.
15185 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
15186 #undef MC_CMD_0x11d_PRIVILEGE_CTG
15188 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15190 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
15191 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
15192 /* Desired instance. Must be set to a specific instance, which is a function
15193 * local queue index.
15195 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
15196 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
15197 /* Will the common pool be used as TX_vFIFO_ULL (1) */
15198 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
15199 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4
15200 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
15201 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */
15202 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
15203 /* Number of buffers to reserve for the common pool */
15204 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8
15205 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4
15206 /* TX datapath to which the Common Pool is connected to. */
15207 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12
15208 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4
15209 /* enum: Extracts information from function */
15210 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
15211 /* Network port or RX Engine to which the common pool connects. */
15212 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16
15213 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4
15214 /* enum: Extracts information from function */
15215 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
15216 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
15217 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
15218 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
15219 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
15220 /* enum: To enable Switch loopback with Rx engine 0 */
15221 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
15222 /* enum: To enable Switch loopback with Rx engine 1 */
15223 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
15225 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */
15226 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
15227 /* ID of the common pool allocated */
15228 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0
15229 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4
15232 /***********************************/
15233 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO
15234 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the
15235 * previously allocated common pools.
15237 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
15238 #undef MC_CMD_0x11e_PRIVILEGE_CTG
15240 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15242 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */
15243 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20
15244 /* Common pool previously allocated to which the new vFIFO will be associated
15246 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0
15247 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4
15248 /* Port or RX engine to associate the vFIFO egress */
15249 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
15250 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4
15251 /* enum: Extracts information from common pool */
15252 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
15253 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
15254 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
15255 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
15256 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
15257 /* enum: To enable Switch loopback with Rx engine 0 */
15258 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
15259 /* enum: To enable Switch loopback with Rx engine 1 */
15260 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
15261 /* Minimum number of buffers that the pool must have */
15262 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8
15263 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4
15264 /* enum: Do not check the space available */
15265 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
15266 /* Will the vFIFO be used as TX_vFIFO_ULL */
15267 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12
15268 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4
15269 /* Network priority of the vFIFO,if applicable */
15270 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16
15271 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4
15272 /* enum: Search for the lowest unused priority */
15273 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
15275 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */
15276 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8
15277 /* Short vFIFO ID */
15278 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0
15279 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4
15280 /* Network priority of the vFIFO */
15281 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4
15282 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4
15285 /***********************************/
15286 /* MC_CMD_TEARDOWN_TX_VFIFO_VF
15287 * This interface clears the configuration of the given vFIFO and leaves it
15288 * ready to be re-used.
15290 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
15291 #undef MC_CMD_0x11f_PRIVILEGE_CTG
15293 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15295 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */
15296 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
15297 /* Short vFIFO ID */
15298 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0
15299 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4
15301 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */
15302 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0
15305 /***********************************/
15306 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP
15307 * This interface clears the configuration of the given common pool and leaves
15308 * it ready to be re-used.
15310 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
15311 #undef MC_CMD_0x121_PRIVILEGE_CTG
15313 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15315 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */
15316 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
15317 /* Common pool ID given when pool allocated */
15318 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0
15319 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4
15321 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */
15322 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0
15325 /***********************************/
15327 * This request causes the NIC to generate a new per-NIC key and program it
15328 * into the write-once memory. During the process all flash partitions that are
15329 * protected with a CMAC are verified with the old per-NIC key and then signed
15330 * with the new per-NIC key. If the NIC has already reached its rekey limit the
15331 * REKEY op will return MC_CMD_ERR_ERANGE. The REKEY op may block until
15332 * completion or it may return 0 and continue processing, therefore the caller
15333 * must poll at least once to confirm that the rekeying has completed. The POLL
15334 * operation returns MC_CMD_ERR_EBUSY if the rekey process is still running
15335 * otherwise it will return the result of the last completed rekey operation,
15336 * or 0 if there has not been a previous rekey.
15338 #define MC_CMD_REKEY 0x123
15339 #undef MC_CMD_0x123_PRIVILEGE_CTG
15341 #define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15343 /* MC_CMD_REKEY_IN msgrequest */
15344 #define MC_CMD_REKEY_IN_LEN 4
15345 /* the type of operation requested */
15346 #define MC_CMD_REKEY_IN_OP_OFST 0
15347 #define MC_CMD_REKEY_IN_OP_LEN 4
15348 /* enum: Start the rekeying operation */
15349 #define MC_CMD_REKEY_IN_OP_REKEY 0x0
15350 /* enum: Poll for completion of the rekeying operation */
15351 #define MC_CMD_REKEY_IN_OP_POLL 0x1
15353 /* MC_CMD_REKEY_OUT msgresponse */
15354 #define MC_CMD_REKEY_OUT_LEN 0
15357 /***********************************/
15358 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS
15359 * This interface allows the host to find out how many common pool buffers are
15360 * not yet assigned.
15362 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
15363 #undef MC_CMD_0x124_PRIVILEGE_CTG
15365 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15367 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */
15368 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
15370 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */
15371 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8
15372 /* Available buffers for the ENG to NET vFIFOs. */
15373 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0
15374 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4
15375 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */
15376 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4
15377 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4
15380 /***********************************/
15381 /* MC_CMD_SET_SECURITY_FUSES
15382 * Change the security level of the adapter by setting bits in the write-once
15383 * memory. The firmware maps each flag in the message to a set of one or more
15384 * hardware-defined or software-defined bits and sets these bits in the write-
15385 * once memory. For Medford the hardware-defined bits are defined in
15386 * SF-112079-PS 5.3, the software-defined bits are defined in xpm.h. Returns 0
15387 * if all of the required bits were set and returns MC_CMD_ERR_EIO if any of
15388 * the required bits were not set.
15390 #define MC_CMD_SET_SECURITY_FUSES 0x126
15391 #undef MC_CMD_0x126_PRIVILEGE_CTG
15393 #define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15395 /* MC_CMD_SET_SECURITY_FUSES_IN msgrequest */
15396 #define MC_CMD_SET_SECURITY_FUSES_IN_LEN 4
15397 /* Flags specifying what type of security features are being set */
15398 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0
15399 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_LEN 4
15400 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0
15401 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1
15402 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1
15403 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1
15404 #define MC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_LBN 31
15405 #define MC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_WIDTH 1
15407 /* MC_CMD_SET_SECURITY_FUSES_OUT msgresponse */
15408 #define MC_CMD_SET_SECURITY_FUSES_OUT_LEN 0
15410 /* MC_CMD_SET_SECURITY_FUSES_V2_OUT msgresponse */
15411 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_LEN 4
15412 /* Flags specifying which security features are enforced on the NIC after the
15413 * flags in the request have been applied. See
15414 * MC_CMD_SET_SECURITY_FUSES_IN/FLAGS for flag definitions.
15416 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_OFST 0
15417 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_LEN 4
15420 /***********************************/
15422 * Messages sent from TSA adapter to TSA controller. This command is only valid
15423 * when the MCDI header has MESSAGE_TYPE set to MCDI_MESSAGE_TYPE_TSA. This
15424 * command is not sent by the driver to the MC; it is sent from the MC to a TSA
15425 * controller, being treated more like an alert message rather than a command;
15426 * hence the MC does not expect a response in return. Doxbox reference
15429 #define MC_CMD_TSA_INFO 0x127
15430 #undef MC_CMD_0x127_PRIVILEGE_CTG
15432 #define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15434 /* MC_CMD_TSA_INFO_IN msgrequest */
15435 #define MC_CMD_TSA_INFO_IN_LEN 4
15436 #define MC_CMD_TSA_INFO_IN_OP_HDR_OFST 0
15437 #define MC_CMD_TSA_INFO_IN_OP_HDR_LEN 4
15438 #define MC_CMD_TSA_INFO_IN_OP_LBN 0
15439 #define MC_CMD_TSA_INFO_IN_OP_WIDTH 16
15440 /* enum: Information about recently discovered local IP address of the adapter
15442 #define MC_CMD_TSA_INFO_OP_LOCAL_IP 0x1
15443 /* enum: Information about a sampled packet that either - did not match any
15444 * black/white-list filters and was allowed by the default filter or - did not
15445 * match any black/white-list filters and was denied by the default filter
15447 #define MC_CMD_TSA_INFO_OP_PKT_SAMPLE 0x2
15449 /* MC_CMD_TSA_INFO_IN_LOCAL_IP msgrequest:
15451 * The TSA controller maintains a list of IP addresses valid for each port of a
15452 * TSA adapter. The TSA controller requires information from the adapter
15453 * inorder to learn new IP addresses assigned to a physical port and to
15454 * identify those that are no longer assigned to the physical port. For this
15455 * purpose, the TSA adapter snoops ARP replys, gratuitous ARP requests and ARP
15456 * probe packets seen on each physical port. This definition describes the
15457 * format of the notification message sent from a TSA adapter to a TSA
15458 * controller related to any information related to a change in IP address
15459 * assignment for a port. Doxbox reference SF-117371.
15461 * There may be a possibility of combining multiple notifications in a single
15462 * message in future. When that happens, a new flag can be defined using the
15463 * reserved bits to describe the extended format of this notification.
15465 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_LEN 18
15466 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_OFST 0
15467 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_LEN 4
15468 /* Additional metadata describing the IP address information such as source of
15469 * information retrieval, type of IP address, physical port number.
15471 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_OFST 4
15472 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_LEN 4
15473 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_LBN 0
15474 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_WIDTH 8
15475 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_LBN 8
15476 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_WIDTH 8
15477 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_LBN 16
15478 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_WIDTH 8
15479 /* enum: ARP reply sent out of the physical port */
15480 #define MC_CMD_TSA_INFO_IP_REASON_TX_ARP 0x0
15481 /* enum: ARP probe packet received on the physical port */
15482 #define MC_CMD_TSA_INFO_IP_REASON_RX_ARP_PROBE 0x1
15483 /* enum: Gratuitous ARP packet received on the physical port */
15484 #define MC_CMD_TSA_INFO_IP_REASON_RX_GRATUITOUS_ARP 0x2
15485 /* enum: DHCP ACK packet received on the physical port */
15486 #define MC_CMD_TSA_INFO_IP_REASON_RX_DHCP_ACK 0x3
15487 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_LBN 24
15488 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_WIDTH 1
15489 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_LBN 25
15490 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_WIDTH 7
15491 /* IPV4 address retrieved from the sampled packets. This field is relevant only
15492 * when META_IPV4 is set to 1.
15494 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_OFST 8
15495 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_LEN 4
15496 /* Target MAC address retrieved from the sampled packet. */
15497 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_OFST 12
15498 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_LEN 1
15499 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_NUM 6
15501 /* MC_CMD_TSA_INFO_IN_PKT_SAMPLE msgrequest:
15503 * It is desireable for the TSA controller to learn the traffic pattern of
15504 * packets seen at the network port being monitored. In order to learn about
15505 * the traffic pattern, the TSA controller may want to sample packets seen at
15506 * the network port. Based on the packet samples that the TSA controller
15507 * receives from the adapter, the controller may choose to configure additional
15508 * black-list or white-list rules to allow or block packets as required.
15510 * Although the entire sampled packet as seen on the network port is available
15511 * to the MC the length of sampled packet sent to controller is restricted by
15512 * MCDI payload size. Besides, the TSA controller does not require the entire
15513 * packet to make decisions about filter updates. Hence the packet sample being
15514 * passed to the controller is truncated to 128 bytes. This length is large
15515 * enough to hold the ethernet header, IP header and maximum length of
15516 * supported L4 protocol headers (IPv4 only, but can hold IPv6 header too, if
15517 * required in future).
15519 * The intention is that any future changes to this message format that are not
15520 * backwards compatible will be defined with a new operation code.
15522 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_LEN 136
15523 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_OFST 0
15524 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_LEN 4
15525 /* Additional metadata describing the sampled packet */
15526 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_OFST 4
15527 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_LEN 4
15528 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_LBN 0
15529 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_WIDTH 8
15530 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_LBN 8
15531 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_WIDTH 1
15532 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_LBN 9
15533 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_WIDTH 7
15534 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_LBN 16
15535 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_WIDTH 4
15536 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_LBN 16
15537 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_WIDTH 1
15538 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_LBN 17
15539 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_WIDTH 1
15540 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_LBN 18
15541 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_WIDTH 1
15542 /* 128-byte raw prefix of the sampled packet which includes the ethernet
15543 * header, IP header and L4 protocol header (only IPv4 supported initially).
15544 * This provides the controller enough information about the packet sample to
15545 * report traffic patterns seen on a network port and to make decisions
15546 * concerning rule-set updates.
15548 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_OFST 8
15549 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_LEN 1
15550 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_NUM 128
15552 /* MC_CMD_TSA_INFO_OUT msgresponse */
15553 #define MC_CMD_TSA_INFO_OUT_LEN 0
15556 /***********************************/
15557 /* MC_CMD_HOST_INFO
15558 * Commands to appply or retrieve host-related information from an adapter.
15559 * Doxbox reference SF-117371-SW
15561 #define MC_CMD_HOST_INFO 0x128
15562 #undef MC_CMD_0x128_PRIVILEGE_CTG
15564 #define MC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15566 /* MC_CMD_HOST_INFO_IN msgrequest */
15567 #define MC_CMD_HOST_INFO_IN_LEN 4
15568 /* sub-operation code info */
15569 #define MC_CMD_HOST_INFO_IN_OP_HDR_OFST 0
15570 #define MC_CMD_HOST_INFO_IN_OP_HDR_LEN 4
15571 #define MC_CMD_HOST_INFO_IN_OP_LBN 0
15572 #define MC_CMD_HOST_INFO_IN_OP_WIDTH 16
15573 /* enum: Read a 16-byte unique host identifier from the adapter. This UUID
15574 * helps to identify the host that an adapter is plugged into. This identifier
15575 * is ideally the system UUID retrieved and set by the UEFI driver. If the UEFI
15576 * driver is unable to extract the system UUID, it would still set a random
15577 * 16-byte value into each supported SF adapter plugged into it. Host UUIDs may
15578 * change if the system is power-cycled, however, they persist across adapter
15579 * resets. If the host UUID was not set on an adapter, due to an unsupported
15580 * version of UEFI driver, then this command returns an error. Doxbox reference
15581 * - SF-117371-SW section 'Host UUID'.
15583 #define MC_CMD_HOST_INFO_OP_GET_UUID 0x0
15584 /* enum: Set a 16-byte unique host identifier on the adapter to identify the
15585 * host that the adapter is plugged into. See MC_CMD_HOST_INFO_OP_GET_UUID for
15588 #define MC_CMD_HOST_INFO_OP_SET_UUID 0x1
15590 /* MC_CMD_HOST_INFO_IN_GET_UUID msgrequest */
15591 #define MC_CMD_HOST_INFO_IN_GET_UUID_LEN 4
15592 /* sub-operation code info */
15593 #define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_OFST 0
15594 #define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_LEN 4
15596 /* MC_CMD_HOST_INFO_OUT_GET_UUID msgresponse */
15597 #define MC_CMD_HOST_INFO_OUT_GET_UUID_LEN 16
15598 /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID
15599 * for further details.
15601 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_OFST 0
15602 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_LEN 1
15603 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_NUM 16
15605 /* MC_CMD_HOST_INFO_IN_SET_UUID msgrequest */
15606 #define MC_CMD_HOST_INFO_IN_SET_UUID_LEN 20
15607 /* sub-operation code info */
15608 #define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_OFST 0
15609 #define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_LEN 4
15610 /* 16-byte host UUID set on the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID for
15613 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_OFST 4
15614 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_LEN 1
15615 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_NUM 16
15617 /* MC_CMD_HOST_INFO_OUT_SET_UUID msgresponse */
15618 #define MC_CMD_HOST_INFO_OUT_SET_UUID_LEN 0
15621 /***********************************/
15622 /* MC_CMD_TSAN_INFO
15623 * Get TSA adapter information. TSA controllers query each TSA adapter to learn
15624 * some configuration parameters of each adapter. Doxbox reference SF-117371-SW
15625 * section 'Adapter Information'
15627 #define MC_CMD_TSAN_INFO 0x129
15628 #undef MC_CMD_0x129_PRIVILEGE_CTG
15630 #define MC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15632 /* MC_CMD_TSAN_INFO_IN msgrequest */
15633 #define MC_CMD_TSAN_INFO_IN_LEN 4
15634 /* sub-operation code info */
15635 #define MC_CMD_TSAN_INFO_IN_OP_HDR_OFST 0
15636 #define MC_CMD_TSAN_INFO_IN_OP_HDR_LEN 4
15637 #define MC_CMD_TSAN_INFO_IN_OP_LBN 0
15638 #define MC_CMD_TSAN_INFO_IN_OP_WIDTH 16
15639 /* enum: Read configuration parameters and IDs that uniquely identify an
15640 * adapter. The parameters include - host identification, adapter
15641 * identification string and number of physical ports on the adapter.
15643 #define MC_CMD_TSAN_INFO_OP_GET_CFG 0x0
15645 /* MC_CMD_TSAN_INFO_IN_GET_CFG msgrequest */
15646 #define MC_CMD_TSAN_INFO_IN_GET_CFG_LEN 4
15647 /* sub-operation code info */
15648 #define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_OFST 0
15649 #define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_LEN 4
15651 /* MC_CMD_TSAN_INFO_OUT_GET_CFG msgresponse */
15652 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_LEN 26
15653 /* Information about the configuration parameters returned in this response. */
15654 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_OFST 0
15655 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_LEN 4
15656 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_LBN 0
15657 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_WIDTH 16
15658 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_LBN 0
15659 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_WIDTH 1
15660 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_LBN 16
15661 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_WIDTH 8
15662 /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID
15663 * for further details.
15665 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_OFST 4
15666 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_LEN 1
15667 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_NUM 16
15668 /* A unique identifier per adapter. The base MAC address of the card is used
15669 * for this purpose.
15671 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_OFST 20
15672 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_LEN 1
15673 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_NUM 6
15676 /***********************************/
15677 /* MC_CMD_TSA_STATISTICS
15678 * TSA adapter statistics operations.
15680 #define MC_CMD_TSA_STATISTICS 0x130
15681 #undef MC_CMD_0x130_PRIVILEGE_CTG
15683 #define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15685 /* MC_CMD_TSA_STATISTICS_IN msgrequest */
15686 #define MC_CMD_TSA_STATISTICS_IN_LEN 4
15687 /* TSA statistics sub-operation code */
15688 #define MC_CMD_TSA_STATISTICS_IN_OP_CODE_OFST 0
15689 #define MC_CMD_TSA_STATISTICS_IN_OP_CODE_LEN 4
15690 /* enum: Get the configuration parameters that describe the TSA statistics
15691 * layout on the adapter.
15693 #define MC_CMD_TSA_STATISTICS_OP_GET_CONFIG 0x0
15694 /* enum: Read and/or clear TSA statistics counters. */
15695 #define MC_CMD_TSA_STATISTICS_OP_READ_CLEAR 0x1
15697 /* MC_CMD_TSA_STATISTICS_IN_GET_CONFIG msgrequest */
15698 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_LEN 4
15699 /* TSA statistics sub-operation code */
15700 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_OFST 0
15701 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_LEN 4
15703 /* MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG msgresponse */
15704 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_LEN 8
15705 /* Maximum number of TSA statistics counters in each direction of dataflow
15706 * supported on the card. Note that the statistics counters are always
15707 * allocated in pairs, i.e. a counter ID is associated with one Tx and one Rx
15710 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_OFST 0
15711 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_LEN 4
15712 /* Width of each statistics counter (represented in bits). This gives an
15713 * indication of wrap point to the user.
15715 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_OFST 4
15716 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_LEN 4
15718 /* MC_CMD_TSA_STATISTICS_IN_READ_CLEAR msgrequest */
15719 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMIN 20
15720 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMAX 252
15721 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LEN(num) (16+4*(num))
15722 /* TSA statistics sub-operation code */
15723 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_OFST 0
15724 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_LEN 4
15725 /* Parameters describing the statistics operation */
15726 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_OFST 4
15727 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_LEN 4
15728 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_LBN 0
15729 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_WIDTH 1
15730 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_LBN 1
15731 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_WIDTH 1
15732 /* Counter ID list specification type */
15733 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_OFST 8
15734 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_LEN 4
15735 /* enum: The statistics counters are specified as an unordered list of
15736 * individual counter ID.
15738 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LIST 0x0
15739 /* enum: The statistics counters are specified as a range of consecutive
15742 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_RANGE 0x1
15743 /* Number of statistics counters */
15744 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_OFST 12
15745 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_LEN 4
15746 /* Counter IDs to be read/cleared. When mode is set to LIST, this entry holds a
15747 * list of counter IDs to be operated on. When mode is set to RANGE, this entry
15748 * holds a single counter ID representing the start of the range of counter IDs
15749 * to be operated on.
15751 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_OFST 16
15752 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_LEN 4
15753 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MINNUM 1
15754 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MAXNUM 59
15756 /* MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR msgresponse */
15757 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMIN 24
15758 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMAX 248
15759 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LEN(num) (8+16*(num))
15760 /* Number of statistics counters returned in this response */
15761 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_OFST 0
15762 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_LEN 4
15763 /* MC_TSA_STATISTICS_ENTRY Note that this field is expected to start at a
15764 * 64-bit aligned offset
15766 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_OFST 8
15767 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_LEN 16
15768 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MINNUM 1
15769 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MAXNUM 15
15771 /* MC_TSA_STATISTICS_ENTRY structuredef */
15772 #define MC_TSA_STATISTICS_ENTRY_LEN 16
15773 /* Tx statistics counter */
15774 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0
15775 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8
15776 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0
15777 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4
15778 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0
15779 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64
15780 /* Rx statistics counter */
15781 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8
15782 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8
15783 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8
15784 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12
15785 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64
15786 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64
15789 /***********************************/
15790 /* MC_CMD_ERASE_INITIAL_NIC_SECRET
15791 * This request causes the NIC to find the initial NIC secret (programmed
15792 * during ATE) in XPM memory and if and only if the NIC has already been
15793 * rekeyed with MC_CMD_REKEY, erase it. This is used by manftest after
15794 * installing TSA binding certificates. See SF-117631-TC.
15796 #define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131
15797 #undef MC_CMD_0x131_PRIVILEGE_CTG
15799 #define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15801 /* MC_CMD_ERASE_INITIAL_NIC_SECRET_IN msgrequest */
15802 #define MC_CMD_ERASE_INITIAL_NIC_SECRET_IN_LEN 0
15804 /* MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT msgresponse */
15805 #define MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT_LEN 0
15808 /***********************************/
15809 /* MC_CMD_TSA_CONFIG
15810 * TSA adapter configuration operations. This command is used to prepare the
15811 * NIC for TSA binding.
15813 #define MC_CMD_TSA_CONFIG 0x64
15814 #undef MC_CMD_0x64_PRIVILEGE_CTG
15816 #define MC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15818 /* MC_CMD_TSA_CONFIG_IN msgrequest */
15819 #define MC_CMD_TSA_CONFIG_IN_LEN 4
15820 /* TSA configuration sub-operation code */
15821 #define MC_CMD_TSA_CONFIG_IN_OP_OFST 0
15822 #define MC_CMD_TSA_CONFIG_IN_OP_LEN 4
15823 /* enum: Append a single item to the tsa_config partition. Items will be
15824 * encrypted unless they are declared as non-sensitive. Returns
15825 * MC_CMD_ERR_EEXIST if the tag is already present.
15827 #define MC_CMD_TSA_CONFIG_OP_APPEND 0x1
15828 /* enum: Reset the tsa_config partition to a clean state. */
15829 #define MC_CMD_TSA_CONFIG_OP_RESET 0x2
15830 /* enum: Read back a configured item from tsa_config partition. Returns
15831 * MC_CMD_ERR_ENOENT if the item doesn't exist, or MC_CMD_ERR_EPERM if the item
15832 * is declared as sensitive (i.e. is encrypted).
15834 #define MC_CMD_TSA_CONFIG_OP_READ 0x3
15836 /* MC_CMD_TSA_CONFIG_IN_APPEND msgrequest */
15837 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENMIN 12
15838 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENMAX 252
15839 #define MC_CMD_TSA_CONFIG_IN_APPEND_LEN(num) (12+1*(num))
15840 /* TSA configuration sub-operation code. The value shall be
15841 * MC_CMD_TSA_CONFIG_OP_APPEND.
15843 #define MC_CMD_TSA_CONFIG_IN_APPEND_OP_OFST 0
15844 #define MC_CMD_TSA_CONFIG_IN_APPEND_OP_LEN 4
15845 /* The tag to be appended */
15846 #define MC_CMD_TSA_CONFIG_IN_APPEND_TAG_OFST 4
15847 #define MC_CMD_TSA_CONFIG_IN_APPEND_TAG_LEN 4
15848 /* The length of the data in bytes */
15849 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_OFST 8
15850 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_LEN 4
15851 /* The item data */
15852 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_OFST 12
15853 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_LEN 1
15854 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MINNUM 0
15855 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MAXNUM 240
15857 /* MC_CMD_TSA_CONFIG_OUT_APPEND msgresponse */
15858 #define MC_CMD_TSA_CONFIG_OUT_APPEND_LEN 0
15860 /* MC_CMD_TSA_CONFIG_IN_RESET msgrequest */
15861 #define MC_CMD_TSA_CONFIG_IN_RESET_LEN 4
15862 /* TSA configuration sub-operation code. The value shall be
15863 * MC_CMD_TSA_CONFIG_OP_RESET.
15865 #define MC_CMD_TSA_CONFIG_IN_RESET_OP_OFST 0
15866 #define MC_CMD_TSA_CONFIG_IN_RESET_OP_LEN 4
15868 /* MC_CMD_TSA_CONFIG_OUT_RESET msgresponse */
15869 #define MC_CMD_TSA_CONFIG_OUT_RESET_LEN 0
15871 /* MC_CMD_TSA_CONFIG_IN_READ msgrequest */
15872 #define MC_CMD_TSA_CONFIG_IN_READ_LEN 8
15873 /* TSA configuration sub-operation code. The value shall be
15874 * MC_CMD_TSA_CONFIG_OP_READ.
15876 #define MC_CMD_TSA_CONFIG_IN_READ_OP_OFST 0
15877 #define MC_CMD_TSA_CONFIG_IN_READ_OP_LEN 4
15878 /* The tag to be read */
15879 #define MC_CMD_TSA_CONFIG_IN_READ_TAG_OFST 4
15880 #define MC_CMD_TSA_CONFIG_IN_READ_TAG_LEN 4
15882 /* MC_CMD_TSA_CONFIG_OUT_READ msgresponse */
15883 #define MC_CMD_TSA_CONFIG_OUT_READ_LENMIN 8
15884 #define MC_CMD_TSA_CONFIG_OUT_READ_LENMAX 252
15885 #define MC_CMD_TSA_CONFIG_OUT_READ_LEN(num) (8+1*(num))
15886 /* The tag that was read */
15887 #define MC_CMD_TSA_CONFIG_OUT_READ_TAG_OFST 0
15888 #define MC_CMD_TSA_CONFIG_OUT_READ_TAG_LEN 4
15889 /* The length of the data in bytes */
15890 #define MC_CMD_TSA_CONFIG_OUT_READ_LENGTH_OFST 4
15891 #define MC_CMD_TSA_CONFIG_OUT_READ_LENGTH_LEN 4
15892 /* The data of the item. */
15893 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_OFST 8
15894 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_LEN 1
15895 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MINNUM 0
15896 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MAXNUM 244
15898 /* MC_TSA_IPV4_ITEM structuredef */
15899 #define MC_TSA_IPV4_ITEM_LEN 8
15900 /* Additional metadata describing the IP address information such as the
15901 * physical port number the address is being used on. Unused space in this
15902 * field is reserved for future expansion.
15904 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_OFST 0
15905 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LEN 4
15906 #define MC_TSA_IPV4_ITEM_PORT_IDX_LBN 0
15907 #define MC_TSA_IPV4_ITEM_PORT_IDX_WIDTH 8
15908 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LBN 0
15909 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_WIDTH 32
15910 /* The IPv4 address in little endian byte order. */
15911 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_OFST 4
15912 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_LEN 4
15913 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_LBN 32
15914 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_WIDTH 32
15917 /***********************************/
15918 /* MC_CMD_TSA_IPADDR
15919 * TSA operations relating to the monitoring and expiry of local IP addresses
15920 * discovered by the controller. These commands are sent from a TSA controller
15921 * to a TSA adapter.
15923 #define MC_CMD_TSA_IPADDR 0x65
15924 #undef MC_CMD_0x65_PRIVILEGE_CTG
15926 #define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15928 /* MC_CMD_TSA_IPADDR_IN msgrequest */
15929 #define MC_CMD_TSA_IPADDR_IN_LEN 4
15930 /* Header containing information to identify which sub-operation of this
15931 * command to perform. The header contains a 16-bit op-code. Unused space in
15932 * this field is reserved for future expansion.
15934 #define MC_CMD_TSA_IPADDR_IN_OP_HDR_OFST 0
15935 #define MC_CMD_TSA_IPADDR_IN_OP_HDR_LEN 4
15936 #define MC_CMD_TSA_IPADDR_IN_OP_LBN 0
15937 #define MC_CMD_TSA_IPADDR_IN_OP_WIDTH 16
15938 /* enum: Request that the adapter verifies that the IPv4 addresses supplied are
15939 * still in use by the host by sending ARP probes to the host. The MC does not
15940 * wait for a response to the probes and sends an MCDI response to the
15941 * controller once the probes have been sent to the host. The response to the
15942 * probes (if there are any) will be forwarded to the controller using
15943 * MC_CMD_TSA_INFO alerts.
15945 #define MC_CMD_TSA_IPADDR_OP_VALIDATE_IPV4 0x1
15946 /* enum: Notify the adapter that one or more IPv4 addresses are no longer valid
15947 * for the host of the adapter. The adapter should remove the IPv4 addresses
15948 * from its local cache.
15950 #define MC_CMD_TSA_IPADDR_OP_REMOVE_IPV4 0x2
15952 /* MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4 msgrequest */
15953 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMIN 16
15954 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMAX 248
15955 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LEN(num) (8+8*(num))
15956 /* Header containing information to identify which sub-operation of this
15957 * command to perform. The header contains a 16-bit op-code. Unused space in
15958 * this field is reserved for future expansion.
15960 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_OFST 0
15961 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_LEN 4
15962 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_LBN 0
15963 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_WIDTH 16
15964 /* Number of IPv4 addresses to validate. */
15965 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_OFST 4
15966 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_LEN 4
15967 /* The IPv4 addresses to validate, in struct MC_TSA_IPV4_ITEM format. */
15968 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8
15969 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8
15970 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8
15971 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12
15972 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1
15973 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30
15975 /* MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4 msgresponse */
15976 #define MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4_LEN 0
15978 /* MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4 msgrequest */
15979 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMIN 16
15980 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMAX 248
15981 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LEN(num) (8+8*(num))
15982 /* Header containing information to identify which sub-operation of this
15983 * command to perform. The header contains a 16-bit op-code. Unused space in
15984 * this field is reserved for future expansion.
15986 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_OFST 0
15987 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_LEN 4
15988 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_LBN 0
15989 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_WIDTH 16
15990 /* Number of IPv4 addresses to remove. */
15991 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_OFST 4
15992 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_LEN 4
15993 /* The IPv4 addresses that have expired, in struct MC_TSA_IPV4_ITEM format. */
15994 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8
15995 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8
15996 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8
15997 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12
15998 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1
15999 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30
16001 /* MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4 msgresponse */
16002 #define MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4_LEN 0
16005 /***********************************/
16006 /* MC_CMD_SECURE_NIC_INFO
16007 * Get secure NIC information. While many of the features reported by these
16008 * commands are related to TSA, they must be supported in firmware where TSA is
16011 #define MC_CMD_SECURE_NIC_INFO 0x132
16012 #undef MC_CMD_0x132_PRIVILEGE_CTG
16014 #define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16016 /* MC_CMD_SECURE_NIC_INFO_IN msgrequest */
16017 #define MC_CMD_SECURE_NIC_INFO_IN_LEN 4
16018 /* sub-operation code info */
16019 #define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_OFST 0
16020 #define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_LEN 4
16021 #define MC_CMD_SECURE_NIC_INFO_IN_OP_LBN 0
16022 #define MC_CMD_SECURE_NIC_INFO_IN_OP_WIDTH 16
16023 /* enum: Get the status of various security settings, all signed along with a
16024 * challenge chosen by the host.
16026 #define MC_CMD_SECURE_NIC_INFO_OP_STATUS 0x0
16028 /* MC_CMD_SECURE_NIC_INFO_IN_STATUS msgrequest */
16029 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_LEN 24
16030 /* sub-operation code, must be MC_CMD_SECURE_NIC_INFO_OP_STATUS */
16031 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_OFST 0
16032 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_LEN 4
16033 /* Type of key to be used to sign response. */
16034 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_OFST 4
16035 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_LEN 4
16036 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_UNUSED 0x0 /* enum */
16037 /* enum: Solarflare adapter authentication key, installed by Manftest. */
16038 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_SF_ADAPTER_AUTH 0x1
16039 /* enum: TSA binding key, installed after adapter is bound to a TSA controller.
16040 * This is not supported in firmware which does not support TSA.
16042 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_TSA_BINDING 0x2
16043 /* enum: Customer adapter authentication key. Installed by the customer in the
16044 * field, but otherwise similar to the Solarflare adapter authentication key.
16046 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CUSTOMER_ADAPTER_AUTH 0x3
16047 /* Random challenge generated by the host. */
16048 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_OFST 8
16049 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_LEN 16
16051 /* MC_CMD_SECURE_NIC_INFO_OUT_STATUS msgresponse */
16052 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_LEN 420
16053 /* Length of the signature in MSG_SIGNATURE. */
16054 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_OFST 0
16055 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_LEN 4
16056 /* Signature over the message, starting at MESSAGE_TYPE and continuing to the
16057 * end of the MCDI response, allowing the message format to be extended. The
16058 * signature uses ECDSA 384 encoding in ASN.1 format. It has variable length,
16059 * with a maximum of 384 bytes.
16061 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_OFST 4
16062 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN 384
16063 /* Enum value indicating the type of response. This protects against chosen
16064 * message attacks. The enum values are random rather than sequential to make
16065 * it unlikely that values will be reused should other commands in a different
16066 * namespace need to create signed messages.
16068 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_OFST 388
16069 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_LEN 4
16070 /* enum: Message type value for the response to a
16071 * MC_CMD_SECURE_NIC_INFO_IN_STATUS message.
16073 #define MC_CMD_SECURE_NIC_INFO_STATUS 0xdb4
16074 /* The challenge provided by the host in the MC_CMD_SECURE_NIC_INFO_IN_STATUS
16077 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_OFST 392
16078 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_LEN 16
16079 /* The first 32 bits of XPM memory, which include security and flag bits, die
16080 * ID and chip ID revision. The meaning of these bits is defined in
16081 * mc/include/mc/xpm.h in the firmwaresrc repository.
16083 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_OFST 408
16084 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_LEN 4
16085 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_OFST 412
16086 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_LEN 2
16087 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_OFST 414
16088 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_LEN 2
16089 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_OFST 416
16090 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_LEN 2
16091 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_OFST 418
16092 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_LEN 2
16095 /***********************************/
16097 * A simple ping-pong command just to test the adapter<>controller MCDI
16098 * communication channel. This command makes not changes to the TSA adapter's
16099 * internal state. It is used by the controller just to verify that the MCDI
16100 * communication channel is working fine. This command takes no additonal
16101 * parameters in request or response.
16103 #define MC_CMD_TSA_TEST 0x125
16104 #undef MC_CMD_0x125_PRIVILEGE_CTG
16106 #define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16108 /* MC_CMD_TSA_TEST_IN msgrequest */
16109 #define MC_CMD_TSA_TEST_IN_LEN 0
16111 /* MC_CMD_TSA_TEST_OUT msgresponse */
16112 #define MC_CMD_TSA_TEST_OUT_LEN 0
16115 /***********************************/
16116 /* MC_CMD_TSA_RULESET_OVERRIDE
16117 * Override TSA ruleset that is currently active on the adapter. This operation
16118 * does not modify the ruleset itself. This operation provides a mechanism to
16119 * apply an allow-all or deny-all operation on all packets, thereby completely
16120 * ignoring the rule-set configured on the adapter. The main purpose of this
16121 * operation is to provide a deterministic state to the TSA firewall during
16122 * rule-set transitions.
16124 #define MC_CMD_TSA_RULESET_OVERRIDE 0x12a
16125 #undef MC_CMD_0x12a_PRIVILEGE_CTG
16127 #define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16129 /* MC_CMD_TSA_RULESET_OVERRIDE_IN msgrequest */
16130 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_LEN 4
16131 /* The override state to apply. */
16132 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_OFST 0
16133 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_LEN 4
16134 /* enum: No override in place - the existing ruleset is in operation. */
16135 #define MC_CMD_TSA_RULESET_OVERRIDE_NONE 0x0
16136 /* enum: Block all packets seen on all datapath channel except those packets
16137 * required for basic configuration of the TSA NIC such as ARPs and TSA-
16138 * communication traffic. Such exceptional traffic is handled differently
16139 * compared to TSA rulesets.
16141 #define MC_CMD_TSA_RULESET_OVERRIDE_BLOCK 0x1
16142 /* enum: Allow all packets through all datapath channel. The TSA adapter
16143 * behaves like a normal NIC without any firewalls.
16145 #define MC_CMD_TSA_RULESET_OVERRIDE_ALLOW 0x2
16147 /* MC_CMD_TSA_RULESET_OVERRIDE_OUT msgresponse */
16148 #define MC_CMD_TSA_RULESET_OVERRIDE_OUT_LEN 0
16151 /***********************************/
16152 /* MC_CMD_TSAC_REQUEST
16153 * Generic command to send requests from a TSA controller to a TSA adapter.
16154 * Specific usage is determined by the TYPE field.
16156 #define MC_CMD_TSAC_REQUEST 0x12b
16157 #undef MC_CMD_0x12b_PRIVILEGE_CTG
16159 #define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16161 /* MC_CMD_TSAC_REQUEST_IN msgrequest */
16162 #define MC_CMD_TSAC_REQUEST_IN_LEN 4
16163 /* The type of request from the controller. */
16164 #define MC_CMD_TSAC_REQUEST_IN_TYPE_OFST 0
16165 #define MC_CMD_TSAC_REQUEST_IN_TYPE_LEN 4
16166 /* enum: Request the adapter to resend localIP information from it's cache. The
16167 * command does not return any IP address information; IP addresses are sent as
16168 * TSA notifications as descibed in MC_CMD_TSA_INFO_IN_LOCAL_IP.
16170 #define MC_CMD_TSAC_REQUEST_LOCALIP 0x0
16172 /* MC_CMD_TSAC_REQUEST_OUT msgresponse */
16173 #define MC_CMD_TSAC_REQUEST_OUT_LEN 0
16176 /***********************************/
16177 /* MC_CMD_SUC_VERSION
16178 * Get the version of the SUC
16180 #define MC_CMD_SUC_VERSION 0x134
16181 #undef MC_CMD_0x134_PRIVILEGE_CTG
16183 #define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16185 /* MC_CMD_SUC_VERSION_IN msgrequest */
16186 #define MC_CMD_SUC_VERSION_IN_LEN 0
16188 /* MC_CMD_SUC_VERSION_OUT msgresponse */
16189 #define MC_CMD_SUC_VERSION_OUT_LEN 24
16190 /* The SUC firmware version as four numbers - a.b.c.d */
16191 #define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0
16192 #define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4
16193 #define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4
16194 /* The date, in seconds since the Unix epoch, when the firmware image was
16197 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16
16198 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4
16199 /* The ID of the SUC chip. This is specific to the platform but typically
16200 * indicates family, memory sizes etc. See SF-116728-SW for further details.
16202 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20
16203 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4
16206 /***********************************/
16207 /* MC_CMD_SUC_MANFTEST
16208 * Operations to support manftest on SUC based systems.
16210 #define MC_CMD_SUC_MANFTEST 0x135
16211 #undef MC_CMD_0x135_PRIVILEGE_CTG
16213 #define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16215 /* MC_CMD_SUC_MANFTEST_IN msgrequest */
16216 #define MC_CMD_SUC_MANFTEST_IN_LEN 4
16217 /* The manftest operation to be performed. */
16218 #define MC_CMD_SUC_MANFTEST_IN_OP_OFST 0
16219 #define MC_CMD_SUC_MANFTEST_IN_OP_LEN 4
16220 /* enum: Read serial number and use count. */
16221 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ 0x0
16222 /* enum: Update use count on wearout adapter. */
16223 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE 0x1
16224 /* enum: Start an ADC calibration. */
16225 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START 0x2
16226 /* enum: Read the status of an ADC calibration. */
16227 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS 0x3
16228 /* enum: Read the results of an ADC calibration. */
16229 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT 0x4
16230 /* enum: Read the PCIe configuration. */
16231 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ 0x5
16232 /* enum: Write the PCIe configuration. */
16233 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE 0x6
16235 /* MC_CMD_SUC_MANFTEST_OUT msgresponse */
16236 #define MC_CMD_SUC_MANFTEST_OUT_LEN 0
16238 /* MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN msgrequest */
16239 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_LEN 4
16240 /* The manftest operation to be performed. This must be
16241 * MC_CMD_SUC_MANFTEST_WEAROUT_READ.
16243 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_OFST 0
16244 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_LEN 4
16246 /* MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT msgresponse */
16247 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_LEN 20
16248 /* The serial number of the wearout adapter, see SF-112717-PR for format. */
16249 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_OFST 0
16250 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_LEN 16
16251 /* The use count of the wearout adapter. */
16252 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_OFST 16
16253 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_LEN 4
16255 /* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN msgrequest */
16256 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_LEN 4
16257 /* The manftest operation to be performed. This must be
16258 * MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE.
16260 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_OFST 0
16261 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_LEN 4
16263 /* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT msgresponse */
16264 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT_LEN 0
16266 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN msgrequest */
16267 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_LEN 4
16268 /* The manftest operation to be performed. This must be
16269 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START.
16271 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_OFST 0
16272 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_LEN 4
16274 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT msgresponse */
16275 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT_LEN 0
16277 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN msgrequest */
16278 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_LEN 4
16279 /* The manftest operation to be performed. This must be
16280 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS.
16282 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_OFST 0
16283 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_LEN 4
16285 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT msgresponse */
16286 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_LEN 4
16287 /* The combined status of the calibration operation. */
16288 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_OFST 0
16289 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_LEN 4
16290 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_LBN 0
16291 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_WIDTH 1
16292 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_LBN 1
16293 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_WIDTH 1
16294 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_LBN 2
16295 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_WIDTH 4
16296 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_LBN 6
16297 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_WIDTH 2
16299 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN msgrequest */
16300 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_LEN 4
16301 /* The manftest operation to be performed. This must be
16302 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT.
16304 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_OFST 0
16305 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_LEN 4
16307 /* MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT msgresponse */
16308 #define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_LEN 12
16309 /* The set of calibration results. */
16310 #define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_OFST 0
16311 #define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_LEN 4
16312 #define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_NUM 3
16314 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN msgrequest */
16315 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_LEN 4
16316 /* The manftest operation to be performed. This must be
16317 * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ.
16319 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_OFST 0
16320 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_LEN 4
16322 /* MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT msgresponse */
16323 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_LEN 4
16324 /* The PCIe vendor ID. */
16325 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_VENDOR_ID_OFST 0
16326 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_VENDOR_ID_LEN 2
16327 /* The PCIe device ID. */
16328 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_DEVICE_ID_OFST 2
16329 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_DEVICE_ID_LEN 2
16331 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN msgrequest */
16332 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_LEN 8
16333 /* The manftest operation to be performed. This must be
16334 * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE.
16336 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_OFST 0
16337 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_LEN 4
16338 /* The PCIe vendor ID. */
16339 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_OFST 4
16340 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_LEN 2
16341 /* The PCIe device ID. */
16342 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_OFST 6
16343 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_LEN 2
16345 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT msgresponse */
16346 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT_LEN 0
16348 #endif /* _SIENA_MC_DRIVER_PCOL_H */