1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2008-2018 Solarflare Communications Inc.
7 /*! \cidoxg_firmware_mc_cmd */
9 #ifndef _SIENA_MC_DRIVER_PCOL_AOE_H
10 #define _SIENA_MC_DRIVER_PCOL_AOE_H
14 /***********************************/
16 * Perform an FC operation
20 /* MC_CMD_FC_IN msgrequest */
21 #define MC_CMD_FC_IN_LEN 4
22 #define MC_CMD_FC_IN_OP_HDR_OFST 0
23 #define MC_CMD_FC_IN_OP_HDR_LEN 4
24 #define MC_CMD_FC_IN_OP_LBN 0
25 #define MC_CMD_FC_IN_OP_WIDTH 8
26 /* enum: NULL MCDI command to FC. */
27 #define MC_CMD_FC_OP_NULL 0x1
28 /* enum: Unused opcode */
29 #define MC_CMD_FC_OP_UNUSED 0x2
30 /* enum: MAC driver commands */
31 #define MC_CMD_FC_OP_MAC 0x3
32 /* enum: Read FC memory */
33 #define MC_CMD_FC_OP_READ32 0x4
34 /* enum: Write to FC memory */
35 #define MC_CMD_FC_OP_WRITE32 0x5
36 /* enum: Read FC memory */
37 #define MC_CMD_FC_OP_TRC_READ 0x6
38 /* enum: Write to FC memory */
39 #define MC_CMD_FC_OP_TRC_WRITE 0x7
40 /* enum: FC firmware Version */
41 #define MC_CMD_FC_OP_GET_VERSION 0x8
42 /* enum: Read FC memory */
43 #define MC_CMD_FC_OP_TRC_RX_READ 0x9
44 /* enum: Write to FC memory */
45 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa
46 /* enum: SFP parameters */
47 #define MC_CMD_FC_OP_SFP 0xb
49 #define MC_CMD_FC_OP_DDR_TEST 0xc
50 /* enum: Get Crash context from FC */
51 #define MC_CMD_FC_OP_GET_ASSERT 0xd
52 /* enum: Get FPGA Build registers */
53 #define MC_CMD_FC_OP_FPGA_BUILD 0xe
54 /* enum: Read map support commands */
55 #define MC_CMD_FC_OP_READ_MAP 0xf
56 /* enum: FC Capabilities */
57 #define MC_CMD_FC_OP_CAPABILITIES 0x10
58 /* enum: FC Global flags */
59 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11
60 /* enum: FC IO using relative addressing modes */
61 #define MC_CMD_FC_OP_IO_REL 0x12
62 /* enum: FPGA link information */
63 #define MC_CMD_FC_OP_UHLINK 0x13
64 /* enum: Configure loopbacks and link on FPGA ports */
65 #define MC_CMD_FC_OP_SET_LINK 0x14
66 /* enum: Licensing operations relating to AOE */
67 #define MC_CMD_FC_OP_LICENSE 0x15
68 /* enum: Startup information to the FC */
69 #define MC_CMD_FC_OP_STARTUP 0x16
70 /* enum: Configure a DMA read */
71 #define MC_CMD_FC_OP_DMA 0x17
72 /* enum: Configure a timed read */
73 #define MC_CMD_FC_OP_TIMED_READ 0x18
74 /* enum: Control UART logging */
75 #define MC_CMD_FC_OP_LOG 0x19
76 /* enum: Get the value of a given clock_id */
77 #define MC_CMD_FC_OP_CLOCK 0x1a
78 /* enum: DDR3/QDR3 parameters */
79 #define MC_CMD_FC_OP_DDR 0x1b
80 /* enum: PTP and timestamp control */
81 #define MC_CMD_FC_OP_TIMESTAMP 0x1c
82 /* enum: Commands for SPI Flash interface */
83 #define MC_CMD_FC_OP_SPI 0x1d
84 /* enum: Commands for diagnostic components */
85 #define MC_CMD_FC_OP_DIAG 0x1e
86 /* enum: External AOE port. */
87 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0
88 /* enum: Internal AOE port. */
89 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40
91 /* MC_CMD_FC_IN_NULL msgrequest */
92 #define MC_CMD_FC_IN_NULL_LEN 4
93 #define MC_CMD_FC_IN_CMD_OFST 0
94 #define MC_CMD_FC_IN_CMD_LEN 4
96 /* MC_CMD_FC_IN_PHY msgrequest */
97 #define MC_CMD_FC_IN_PHY_LEN 5
98 /* MC_CMD_FC_IN_CMD_OFST 0 */
99 /* MC_CMD_FC_IN_CMD_LEN 4 */
100 /* FC PHY driver operation code */
101 #define MC_CMD_FC_IN_PHY_OP_OFST 4
102 #define MC_CMD_FC_IN_PHY_OP_LEN 1
103 /* enum: PHY init handler */
104 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1
105 /* enum: PHY reconfigure handler */
106 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2
107 /* enum: PHY reboot handler */
108 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3
109 /* enum: PHY get_supported_cap handler */
110 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4
111 /* enum: PHY get_config handler */
112 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5
113 /* enum: PHY get_media_info handler */
114 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6
115 /* enum: PHY set_led handler */
116 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7
117 /* enum: PHY lasi_interrupt handler */
118 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8
119 /* enum: PHY check_link handler */
120 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9
121 /* enum: PHY fill_stats handler */
122 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa
123 /* enum: PHY bpx_link_state_changed handler */
124 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb
125 /* enum: PHY get_state handler */
126 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc
127 /* enum: PHY start_bist handler */
128 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd
129 /* enum: PHY poll_bist handler */
130 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe
131 /* enum: PHY nvram_test handler */
132 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf
133 /* enum: PHY relinquish handler */
134 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10
135 /* enum: PHY read connection from FC - may be not required */
136 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11
137 /* enum: PHY read flags from FC - may be not required */
138 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12
140 /* MC_CMD_FC_IN_PHY_INIT msgrequest */
141 #define MC_CMD_FC_IN_PHY_INIT_LEN 4
142 #define MC_CMD_FC_IN_PHY_CMD_OFST 0
143 #define MC_CMD_FC_IN_PHY_CMD_LEN 4
145 /* MC_CMD_FC_IN_MAC msgrequest */
146 #define MC_CMD_FC_IN_MAC_LEN 8
147 /* MC_CMD_FC_IN_CMD_OFST 0 */
148 /* MC_CMD_FC_IN_CMD_LEN 4 */
149 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4
150 #define MC_CMD_FC_IN_MAC_HEADER_LEN 4
151 #define MC_CMD_FC_IN_MAC_OP_LBN 0
152 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8
153 /* enum: MAC reconfigure handler */
154 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1
155 /* enum: MAC Set command - same as MC_CMD_SET_MAC */
156 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2
157 /* enum: MAC statistics */
158 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3
159 /* enum: MAC RX statistics */
160 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6
161 /* enum: MAC TX statistics */
162 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7
163 /* enum: MAC Read status */
164 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8
165 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8
166 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8
167 /* enum: External FPGA port. */
168 #define MC_CMD_FC_PORT_EXT 0x0
169 /* enum: Internal Siena-facing FPGA ports. */
170 #define MC_CMD_FC_PORT_INT 0x1
171 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16
172 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8
173 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24
174 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8
175 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
176 * irrelevant. Port number is derived from pci_fn; passed in FC header.
178 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0
179 /* enum: Override default port number. Port number determined by fields
180 * PORT_TYPE and PORT_IDX.
182 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1
184 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */
185 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8
186 /* MC_CMD_FC_IN_CMD_OFST 0 */
187 /* MC_CMD_FC_IN_CMD_LEN 4 */
188 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
189 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
191 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */
192 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32
193 /* MC_CMD_FC_IN_CMD_OFST 0 */
194 /* MC_CMD_FC_IN_CMD_LEN 4 */
195 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
196 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
198 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8
199 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4
201 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12
202 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4
203 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
204 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
205 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16
206 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20
207 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24
208 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4
209 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0
210 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1
211 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1
212 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1
213 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28
214 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4
216 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */
217 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8
218 /* MC_CMD_FC_IN_CMD_OFST 0 */
219 /* MC_CMD_FC_IN_CMD_LEN 4 */
220 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
221 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
223 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */
224 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8
225 /* MC_CMD_FC_IN_CMD_OFST 0 */
226 /* MC_CMD_FC_IN_CMD_LEN 4 */
227 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
228 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
230 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */
231 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8
232 /* MC_CMD_FC_IN_CMD_OFST 0 */
233 /* MC_CMD_FC_IN_CMD_LEN 4 */
234 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
235 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
237 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */
238 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20
239 /* MC_CMD_FC_IN_CMD_OFST 0 */
240 /* MC_CMD_FC_IN_CMD_LEN 4 */
241 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
242 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
243 /* MC Statistics index */
244 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8
245 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4
246 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12
247 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4
248 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0
249 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1
250 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1
251 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1
252 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2
253 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1
254 /* Number of statistics to read */
255 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16
256 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4
257 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */
258 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */
260 /* MC_CMD_FC_IN_READ32 msgrequest */
261 #define MC_CMD_FC_IN_READ32_LEN 16
262 /* MC_CMD_FC_IN_CMD_OFST 0 */
263 /* MC_CMD_FC_IN_CMD_LEN 4 */
264 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4
265 #define MC_CMD_FC_IN_READ32_ADDR_HI_LEN 4
266 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8
267 #define MC_CMD_FC_IN_READ32_ADDR_LO_LEN 4
268 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12
269 #define MC_CMD_FC_IN_READ32_NUMWORDS_LEN 4
271 /* MC_CMD_FC_IN_WRITE32 msgrequest */
272 #define MC_CMD_FC_IN_WRITE32_LENMIN 16
273 #define MC_CMD_FC_IN_WRITE32_LENMAX 252
274 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))
275 /* MC_CMD_FC_IN_CMD_OFST 0 */
276 /* MC_CMD_FC_IN_CMD_LEN 4 */
277 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4
278 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4
279 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8
280 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4
281 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12
282 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4
283 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1
284 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60
286 /* MC_CMD_FC_IN_TRC_READ msgrequest */
287 #define MC_CMD_FC_IN_TRC_READ_LEN 12
288 /* MC_CMD_FC_IN_CMD_OFST 0 */
289 /* MC_CMD_FC_IN_CMD_LEN 4 */
290 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4
291 #define MC_CMD_FC_IN_TRC_READ_TRC_LEN 4
292 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8
293 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4
295 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */
296 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28
297 /* MC_CMD_FC_IN_CMD_OFST 0 */
298 /* MC_CMD_FC_IN_CMD_LEN 4 */
299 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4
300 #define MC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4
301 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8
302 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4
303 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12
304 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4
305 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4
307 /* MC_CMD_FC_IN_GET_VERSION msgrequest */
308 #define MC_CMD_FC_IN_GET_VERSION_LEN 4
309 /* MC_CMD_FC_IN_CMD_OFST 0 */
310 /* MC_CMD_FC_IN_CMD_LEN 4 */
312 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */
313 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12
314 /* MC_CMD_FC_IN_CMD_OFST 0 */
315 /* MC_CMD_FC_IN_CMD_LEN 4 */
316 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4
317 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4
318 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8
319 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4
321 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */
322 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20
323 /* MC_CMD_FC_IN_CMD_OFST 0 */
324 /* MC_CMD_FC_IN_CMD_LEN 4 */
325 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4
326 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4
327 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8
328 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4
329 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12
330 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4
331 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2
333 /* MC_CMD_FC_IN_SFP msgrequest */
334 #define MC_CMD_FC_IN_SFP_LEN 28
335 /* MC_CMD_FC_IN_CMD_OFST 0 */
336 /* MC_CMD_FC_IN_CMD_LEN 4 */
337 /* Link speed is 100, 1000, 10000, 40000 */
338 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4
339 #define MC_CMD_FC_IN_SFP_SPEED_LEN 4
340 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */
341 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8
342 #define MC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4
343 /* Not relevant for cards with QSFP modules. For older cards, true if module is
344 * a dual speed SFP+ module.
346 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12
347 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4
348 /* True if an SFP Module is present (other fields valid when true) */
349 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16
350 #define MC_CMD_FC_IN_SFP_PRESENT_LEN 4
351 /* The type of the SFP+ Module. For later cards with QSFP modules, this field
352 * is unused and the type is communicated by other means.
354 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20
355 #define MC_CMD_FC_IN_SFP_TYPE_LEN 4
356 /* Capabilities corresponding to 1 bits. */
357 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24
358 #define MC_CMD_FC_IN_SFP_CAPS_LEN 4
360 /* MC_CMD_FC_IN_DDR_TEST msgrequest */
361 #define MC_CMD_FC_IN_DDR_TEST_LEN 8
362 /* MC_CMD_FC_IN_CMD_OFST 0 */
363 /* MC_CMD_FC_IN_CMD_LEN 4 */
364 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4
365 #define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4
366 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0
367 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8
368 /* enum: DRAM Test Start */
369 #define MC_CMD_FC_OP_DDR_TEST_START 0x1
370 /* enum: DRAM Test Poll */
371 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2
373 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */
374 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12
375 /* MC_CMD_FC_IN_CMD_OFST 0 */
376 /* MC_CMD_FC_IN_CMD_LEN 4 */
377 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */
378 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */
379 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8
380 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4
381 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0
382 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1
383 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1
384 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1
385 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2
386 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1
387 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3
388 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1
390 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */
391 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12
392 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0
393 #define MC_CMD_FC_IN_DDR_TEST_CMD_LEN 4
394 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */
395 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */
396 /* Clear previous test result and prepare for restarting DDR test */
397 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8
398 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4
400 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */
401 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4
402 /* MC_CMD_FC_IN_CMD_OFST 0 */
403 /* MC_CMD_FC_IN_CMD_LEN 4 */
405 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */
406 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8
407 /* MC_CMD_FC_IN_CMD_OFST 0 */
408 /* MC_CMD_FC_IN_CMD_LEN 4 */
409 /* FPGA build info operation code */
410 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4
411 #define MC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4
412 /* enum: Get the build registers */
413 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1
414 /* enum: Get the services registers */
415 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2
416 /* enum: Get the BSP version */
417 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3
418 /* enum: Get build register for V2 (SFA974X) */
419 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4
420 /* enum: GEt the services register for V2 (SFA974X) */
421 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5
423 /* MC_CMD_FC_IN_READ_MAP msgrequest */
424 #define MC_CMD_FC_IN_READ_MAP_LEN 8
425 /* MC_CMD_FC_IN_CMD_OFST 0 */
426 /* MC_CMD_FC_IN_CMD_LEN 4 */
427 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4
428 #define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4
429 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0
430 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8
431 /* enum: Get the number of map regions */
432 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1
433 /* enum: Get the specified map */
434 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2
436 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */
437 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8
438 /* MC_CMD_FC_IN_CMD_OFST 0 */
439 /* MC_CMD_FC_IN_CMD_LEN 4 */
440 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */
441 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */
443 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */
444 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12
445 /* MC_CMD_FC_IN_CMD_OFST 0 */
446 /* MC_CMD_FC_IN_CMD_LEN 4 */
447 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */
448 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */
449 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8
450 #define MC_CMD_FC_IN_MAP_INDEX_LEN 4
452 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */
453 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4
454 /* MC_CMD_FC_IN_CMD_OFST 0 */
455 /* MC_CMD_FC_IN_CMD_LEN 4 */
457 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */
458 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8
459 /* MC_CMD_FC_IN_CMD_OFST 0 */
460 /* MC_CMD_FC_IN_CMD_LEN 4 */
461 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4
462 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4
463 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0
464 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1
465 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1
466 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1
467 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2
468 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1
469 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3
470 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1
471 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4
472 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1
473 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5
474 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1
476 /* MC_CMD_FC_IN_IO_REL msgrequest */
477 #define MC_CMD_FC_IN_IO_REL_LEN 8
478 /* MC_CMD_FC_IN_CMD_OFST 0 */
479 /* MC_CMD_FC_IN_CMD_LEN 4 */
480 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4
481 #define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4
482 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0
483 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8
484 /* enum: Get the base address that the FC applies to relative commands */
485 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1
486 /* enum: Read data */
487 #define MC_CMD_FC_IN_IO_REL_READ32 0x2
488 /* enum: Write data */
489 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3
490 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8
491 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8
492 /* enum: Application address space */
493 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1
494 /* enum: Flash address space */
495 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2
497 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */
498 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8
499 /* MC_CMD_FC_IN_CMD_OFST 0 */
500 /* MC_CMD_FC_IN_CMD_LEN 4 */
501 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
502 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */
504 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */
505 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20
506 /* MC_CMD_FC_IN_CMD_OFST 0 */
507 /* MC_CMD_FC_IN_CMD_LEN 4 */
508 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
509 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */
510 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8
511 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4
512 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12
513 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4
514 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16
515 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4
517 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */
518 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20
519 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252
520 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))
521 /* MC_CMD_FC_IN_CMD_OFST 0 */
522 /* MC_CMD_FC_IN_CMD_LEN 4 */
523 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
524 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */
525 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8
526 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4
527 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12
528 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4
529 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16
530 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4
531 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1
532 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59
534 /* MC_CMD_FC_IN_UHLINK msgrequest */
535 #define MC_CMD_FC_IN_UHLINK_LEN 8
536 /* MC_CMD_FC_IN_CMD_OFST 0 */
537 /* MC_CMD_FC_IN_CMD_LEN 4 */
538 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4
539 #define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4
540 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0
541 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8
542 /* enum: Get PHY configuration info */
543 #define MC_CMD_FC_OP_UHLINK_PHY 0x1
544 /* enum: Get MAC configuration info */
545 #define MC_CMD_FC_OP_UHLINK_MAC 0x2
546 /* enum: Get Rx eye table */
547 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3
548 /* enum: Get Rx eye plot */
549 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4
550 /* enum: Get Rx eye plot */
551 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5
552 /* enum: Retune Rx settings */
553 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6
554 /* enum: Set loopback mode on fpga port */
555 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7
556 /* enum: Get loopback mode config state on fpga port */
557 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8
558 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8
559 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8
560 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16
561 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8
562 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24
563 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8
564 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
565 * irrelevant. Port number is derived from pci_fn; passed in FC header.
567 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0
568 /* enum: Override default port number. Port number determined by fields
569 * PORT_TYPE and PORT_IDX.
571 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1
573 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */
574 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8
575 /* MC_CMD_FC_IN_CMD_OFST 0 */
576 /* MC_CMD_FC_IN_CMD_LEN 4 */
577 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
578 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
580 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */
581 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8
582 /* MC_CMD_FC_IN_CMD_OFST 0 */
583 /* MC_CMD_FC_IN_CMD_LEN 4 */
584 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
585 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
587 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */
588 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12
589 /* MC_CMD_FC_IN_CMD_OFST 0 */
590 /* MC_CMD_FC_IN_CMD_LEN 4 */
591 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
592 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
593 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8
594 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4
595 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */
597 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */
598 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8
599 /* MC_CMD_FC_IN_CMD_OFST 0 */
600 /* MC_CMD_FC_IN_CMD_LEN 4 */
601 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
602 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
604 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */
605 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20
606 /* MC_CMD_FC_IN_CMD_OFST 0 */
607 /* MC_CMD_FC_IN_CMD_LEN 4 */
608 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
609 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
610 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8
611 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4
612 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12
613 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4
614 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16
615 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4
616 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */
618 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */
619 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8
620 /* MC_CMD_FC_IN_CMD_OFST 0 */
621 /* MC_CMD_FC_IN_CMD_LEN 4 */
622 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
623 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
625 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */
626 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16
627 /* MC_CMD_FC_IN_CMD_OFST 0 */
628 /* MC_CMD_FC_IN_CMD_LEN 4 */
629 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
630 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
631 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8
632 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4
633 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */
634 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */
635 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */
636 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12
637 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4
638 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */
639 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */
641 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */
642 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12
643 /* MC_CMD_FC_IN_CMD_OFST 0 */
644 /* MC_CMD_FC_IN_CMD_LEN 4 */
645 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
646 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
647 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8
648 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4
650 /* MC_CMD_FC_IN_SET_LINK msgrequest */
651 #define MC_CMD_FC_IN_SET_LINK_LEN 16
652 /* MC_CMD_FC_IN_CMD_OFST 0 */
653 /* MC_CMD_FC_IN_CMD_LEN 4 */
654 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
655 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4
656 #define MC_CMD_FC_IN_SET_LINK_MODE_LEN 4
657 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8
658 #define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4
659 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12
660 #define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4
661 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0
662 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1
663 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1
664 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1
665 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2
666 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1
668 /* MC_CMD_FC_IN_LICENSE msgrequest */
669 #define MC_CMD_FC_IN_LICENSE_LEN 8
670 /* MC_CMD_FC_IN_CMD_OFST 0 */
671 /* MC_CMD_FC_IN_CMD_LEN 4 */
672 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4
673 #define MC_CMD_FC_IN_LICENSE_OP_LEN 4
674 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */
675 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */
677 /* MC_CMD_FC_IN_STARTUP msgrequest */
678 #define MC_CMD_FC_IN_STARTUP_LEN 40
679 /* MC_CMD_FC_IN_CMD_OFST 0 */
680 /* MC_CMD_FC_IN_CMD_LEN 4 */
681 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4
682 #define MC_CMD_FC_IN_STARTUP_BASE_LEN 4
683 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8
684 #define MC_CMD_FC_IN_STARTUP_LENGTH_LEN 4
685 /* Length of identifier */
686 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12
687 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4
688 /* Identifier for AOE FPGA */
689 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16
690 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1
691 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24
693 /* MC_CMD_FC_IN_DMA msgrequest */
694 #define MC_CMD_FC_IN_DMA_LEN 8
695 /* MC_CMD_FC_IN_CMD_OFST 0 */
696 /* MC_CMD_FC_IN_CMD_LEN 4 */
697 #define MC_CMD_FC_IN_DMA_OP_OFST 4
698 #define MC_CMD_FC_IN_DMA_OP_LEN 4
699 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */
700 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */
702 /* MC_CMD_FC_IN_DMA_STOP msgrequest */
703 #define MC_CMD_FC_IN_DMA_STOP_LEN 12
704 /* MC_CMD_FC_IN_CMD_OFST 0 */
705 /* MC_CMD_FC_IN_CMD_LEN 4 */
706 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */
707 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */
708 /* FC supplied handle */
709 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8
710 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4
712 /* MC_CMD_FC_IN_DMA_READ msgrequest */
713 #define MC_CMD_FC_IN_DMA_READ_LEN 16
714 /* MC_CMD_FC_IN_CMD_OFST 0 */
715 /* MC_CMD_FC_IN_CMD_LEN 4 */
716 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */
717 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */
718 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8
719 #define MC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4
720 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12
721 #define MC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4
723 /* MC_CMD_FC_IN_TIMED_READ msgrequest */
724 #define MC_CMD_FC_IN_TIMED_READ_LEN 8
725 /* MC_CMD_FC_IN_CMD_OFST 0 */
726 /* MC_CMD_FC_IN_CMD_LEN 4 */
727 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4
728 #define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4
729 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */
730 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */
731 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */
733 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */
734 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52
735 /* MC_CMD_FC_IN_CMD_OFST 0 */
736 /* MC_CMD_FC_IN_CMD_LEN 4 */
737 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
738 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */
739 /* Host supplied handle (unique) */
740 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8
741 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4
742 /* Address into which to transfer data in host */
743 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
744 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
745 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
746 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
747 /* AOE address from which to transfer data */
748 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
749 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
750 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
751 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
752 /* Length of AOE transfer (total) */
753 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
754 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4
755 /* Length of host transfer (total) */
756 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32
757 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4
758 /* Offset back from aoe_address to apply operation to */
759 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36
760 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4
761 /* Data to apply at offset */
762 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40
763 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4
764 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44
765 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4
766 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0
767 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1
768 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1
769 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1
770 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2
771 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1
772 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3
773 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2
774 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */
775 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */
776 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */
777 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */
778 /* Period at which reads are performed (100ms units) */
779 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48
780 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4
782 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */
783 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12
784 /* MC_CMD_FC_IN_CMD_OFST 0 */
785 /* MC_CMD_FC_IN_CMD_LEN 4 */
786 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
787 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */
788 /* FC supplied handle */
789 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8
790 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4
792 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */
793 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12
794 /* MC_CMD_FC_IN_CMD_OFST 0 */
795 /* MC_CMD_FC_IN_CMD_LEN 4 */
796 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
797 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */
798 /* FC supplied handle */
799 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8
800 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4
802 /* MC_CMD_FC_IN_LOG msgrequest */
803 #define MC_CMD_FC_IN_LOG_LEN 8
804 /* MC_CMD_FC_IN_CMD_OFST 0 */
805 /* MC_CMD_FC_IN_CMD_LEN 4 */
806 #define MC_CMD_FC_IN_LOG_OP_OFST 4
807 #define MC_CMD_FC_IN_LOG_OP_LEN 4
808 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */
809 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */
811 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */
812 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20
813 /* MC_CMD_FC_IN_CMD_OFST 0 */
814 /* MC_CMD_FC_IN_CMD_LEN 4 */
815 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */
816 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */
817 /* Partition offset into flash */
818 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8
819 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4
820 /* Partition length */
821 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12
822 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4
823 /* Partition erase size */
824 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16
825 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4
827 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */
828 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12
829 /* MC_CMD_FC_IN_CMD_OFST 0 */
830 /* MC_CMD_FC_IN_CMD_LEN 4 */
831 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */
832 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */
833 /* Enable/disable printing to JTAG UART */
834 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8
835 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4
837 /* MC_CMD_FC_IN_CLOCK msgrequest */
838 #define MC_CMD_FC_IN_CLOCK_LEN 12
839 /* MC_CMD_FC_IN_CMD_OFST 0 */
840 /* MC_CMD_FC_IN_CMD_LEN 4 */
841 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4
842 #define MC_CMD_FC_IN_CLOCK_OP_LEN 4
843 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */
844 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */
845 /* Perform a clock operation */
846 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8
847 #define MC_CMD_FC_IN_CLOCK_ID_LEN 4
848 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */
849 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */
851 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */
852 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12
853 /* MC_CMD_FC_IN_CMD_OFST 0 */
854 /* MC_CMD_FC_IN_CMD_LEN 4 */
855 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
856 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */
857 /* Retrieve the clock value of the specified clock */
858 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
859 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */
861 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */
862 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24
863 /* MC_CMD_FC_IN_CMD_OFST 0 */
864 /* MC_CMD_FC_IN_CMD_LEN 4 */
865 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
866 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */
867 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
868 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */
869 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12
870 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
871 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
872 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
873 /* Set the clock value of the specified clock */
874 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
875 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4
877 /* MC_CMD_FC_IN_DDR msgrequest */
878 #define MC_CMD_FC_IN_DDR_LEN 12
879 /* MC_CMD_FC_IN_CMD_OFST 0 */
880 /* MC_CMD_FC_IN_CMD_LEN 4 */
881 #define MC_CMD_FC_IN_DDR_OP_OFST 4
882 #define MC_CMD_FC_IN_DDR_OP_LEN 4
883 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */
884 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */
885 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */
886 #define MC_CMD_FC_IN_DDR_BANK_OFST 8
887 #define MC_CMD_FC_IN_DDR_BANK_LEN 4
888 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */
889 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */
890 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */
891 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */
892 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */
894 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */
895 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148
896 /* MC_CMD_FC_IN_CMD_OFST 0 */
897 /* MC_CMD_FC_IN_CMD_LEN 4 */
898 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */
899 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */
901 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */
902 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */
904 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12
905 #define MC_CMD_FC_IN_DDR_FLAGS_LEN 4
906 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */
907 /* 128-byte page of serial presence detect data read from module's EEPROM */
908 #define MC_CMD_FC_IN_DDR_SPD_OFST 16
909 #define MC_CMD_FC_IN_DDR_SPD_LEN 1
910 #define MC_CMD_FC_IN_DDR_SPD_NUM 128
911 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */
912 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144
913 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4
915 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */
916 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16
917 /* MC_CMD_FC_IN_CMD_OFST 0 */
918 /* MC_CMD_FC_IN_CMD_LEN 4 */
919 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */
920 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */
922 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */
923 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */
925 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12
926 #define MC_CMD_FC_IN_DDR_SIZE_LEN 4
928 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */
929 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12
930 /* MC_CMD_FC_IN_CMD_OFST 0 */
931 /* MC_CMD_FC_IN_CMD_LEN 4 */
932 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */
933 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */
935 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */
936 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */
938 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */
939 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8
940 /* MC_CMD_FC_IN_CMD_OFST 0 */
941 /* MC_CMD_FC_IN_CMD_LEN 4 */
942 /* FC timestamp operation code */
943 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4
944 #define MC_CMD_FC_IN_TIMESTAMP_OP_LEN 4
945 /* enum: Read transmit timestamp(s) */
946 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0
947 /* enum: Read snapshot timestamps */
948 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1
949 /* enum: Clear all transmit timestamps */
950 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2
952 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */
953 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28
954 /* MC_CMD_FC_IN_CMD_OFST 0 */
955 /* MC_CMD_FC_IN_CMD_LEN 4 */
956 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4
957 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4
958 /* Control filtering of the returned timestamp and sequence number specified
961 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8
962 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4
963 /* enum: Return most recent timestamp. No filtering */
964 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0
965 /* enum: Match timestamp against the PTP clock ID, port number and sequence
968 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1
969 /* Clock identity of PTP packet for which timestamp required */
970 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
971 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
972 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
973 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
974 /* Port number of PTP packet for which timestamp required */
975 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
976 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4
977 /* Sequence number of PTP packet for which timestamp required */
978 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24
979 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4
981 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */
982 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8
983 /* MC_CMD_FC_IN_CMD_OFST 0 */
984 /* MC_CMD_FC_IN_CMD_LEN 4 */
985 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4
986 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4
988 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */
989 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8
990 /* MC_CMD_FC_IN_CMD_OFST 0 */
991 /* MC_CMD_FC_IN_CMD_LEN 4 */
992 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4
993 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4
995 /* MC_CMD_FC_IN_SPI msgrequest */
996 #define MC_CMD_FC_IN_SPI_LEN 8
997 /* MC_CMD_FC_IN_CMD_OFST 0 */
998 /* MC_CMD_FC_IN_CMD_LEN 4 */
999 /* Basic commands for SPI Flash. */
1000 #define MC_CMD_FC_IN_SPI_OP_OFST 4
1001 #define MC_CMD_FC_IN_SPI_OP_LEN 4
1002 /* enum: SPI Flash read */
1003 #define MC_CMD_FC_IN_SPI_READ 0x0
1004 /* enum: SPI Flash write */
1005 #define MC_CMD_FC_IN_SPI_WRITE 0x1
1006 /* enum: SPI Flash erase */
1007 #define MC_CMD_FC_IN_SPI_ERASE 0x2
1009 /* MC_CMD_FC_IN_SPI_READ msgrequest */
1010 #define MC_CMD_FC_IN_SPI_READ_LEN 16
1011 /* MC_CMD_FC_IN_CMD_OFST 0 */
1012 /* MC_CMD_FC_IN_CMD_LEN 4 */
1013 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4
1014 #define MC_CMD_FC_IN_SPI_READ_OP_LEN 4
1015 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8
1016 #define MC_CMD_FC_IN_SPI_READ_ADDR_LEN 4
1017 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12
1018 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4
1020 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */
1021 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16
1022 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252
1023 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))
1024 /* MC_CMD_FC_IN_CMD_OFST 0 */
1025 /* MC_CMD_FC_IN_CMD_LEN 4 */
1026 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4
1027 #define MC_CMD_FC_IN_SPI_WRITE_OP_LEN 4
1028 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8
1029 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4
1030 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12
1031 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4
1032 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1
1033 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60
1035 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */
1036 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16
1037 /* MC_CMD_FC_IN_CMD_OFST 0 */
1038 /* MC_CMD_FC_IN_CMD_LEN 4 */
1039 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4
1040 #define MC_CMD_FC_IN_SPI_ERASE_OP_LEN 4
1041 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8
1042 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4
1043 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12
1044 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4
1046 /* MC_CMD_FC_IN_DIAG msgrequest */
1047 #define MC_CMD_FC_IN_DIAG_LEN 8
1048 /* MC_CMD_FC_IN_CMD_OFST 0 */
1049 /* MC_CMD_FC_IN_CMD_LEN 4 */
1050 /* Operation code indicating component type */
1051 #define MC_CMD_FC_IN_DIAG_OP_OFST 4
1052 #define MC_CMD_FC_IN_DIAG_OP_LEN 4
1053 /* enum: Power noise generator. */
1054 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0
1055 /* enum: DDR soak test component. */
1056 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1
1057 /* enum: Diagnostics datapath control component. */
1058 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2
1060 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */
1061 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12
1062 /* MC_CMD_FC_IN_CMD_OFST 0 */
1063 /* MC_CMD_FC_IN_CMD_LEN 4 */
1064 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4
1065 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4
1066 /* Sub-opcode describing the operation to be carried out */
1067 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8
1068 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4
1069 /* enum: Read the configuration (the 32-bit values in each of the clock enable
1070 * count and toggle count registers)
1072 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0
1073 /* enum: Write a new configuration to the clock enable count and toggle count
1076 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1
1078 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */
1079 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12
1080 /* MC_CMD_FC_IN_CMD_OFST 0 */
1081 /* MC_CMD_FC_IN_CMD_LEN 4 */
1082 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4
1083 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4
1084 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8
1085 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4
1087 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */
1088 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20
1089 /* MC_CMD_FC_IN_CMD_OFST 0 */
1090 /* MC_CMD_FC_IN_CMD_LEN 4 */
1091 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4
1092 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4
1093 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8
1094 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4
1095 /* The 32-bit value to be written to the toggle count register */
1096 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12
1097 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4
1098 /* The 32-bit value to be written to the clock enable count register */
1099 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16
1100 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4
1102 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */
1103 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12
1104 /* MC_CMD_FC_IN_CMD_OFST 0 */
1105 /* MC_CMD_FC_IN_CMD_LEN 4 */
1106 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4
1107 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4
1108 /* Sub-opcode describing the operation to be carried out */
1109 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8
1110 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4
1111 /* enum: Starts DDR soak test on selected banks */
1112 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0
1113 /* enum: Read status of DDR soak test */
1114 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1
1115 /* enum: Stop test */
1116 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2
1117 /* enum: Set or clear bit that triggers fake errors. These cause subsequent
1118 * tests to fail until the bit is cleared.
1120 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3
1122 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */
1123 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24
1124 /* MC_CMD_FC_IN_CMD_OFST 0 */
1125 /* MC_CMD_FC_IN_CMD_LEN 4 */
1126 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4
1127 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4
1128 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8
1129 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4
1130 /* Mask of DDR banks to be tested */
1131 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12
1132 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4
1133 /* Pattern to use in the soak test */
1134 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16
1135 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4
1136 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */
1137 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */
1138 /* Either multiple automatic tests until a STOP command is issued, or one
1141 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20
1142 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4
1143 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */
1144 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */
1146 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */
1147 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16
1148 /* MC_CMD_FC_IN_CMD_OFST 0 */
1149 /* MC_CMD_FC_IN_CMD_LEN 4 */
1150 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4
1151 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4
1152 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8
1153 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4
1154 /* DDR bank to read status from */
1155 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12
1156 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4
1157 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */
1158 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */
1159 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */
1160 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */
1161 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */
1163 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */
1164 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16
1165 /* MC_CMD_FC_IN_CMD_OFST 0 */
1166 /* MC_CMD_FC_IN_CMD_LEN 4 */
1167 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4
1168 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4
1169 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8
1170 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4
1171 /* Mask of DDR banks to be tested */
1172 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12
1173 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4
1175 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */
1176 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20
1177 /* MC_CMD_FC_IN_CMD_OFST 0 */
1178 /* MC_CMD_FC_IN_CMD_LEN 4 */
1179 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4
1180 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4
1181 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8
1182 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4
1183 /* Mask of DDR banks to set/clear error flag on */
1184 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12
1185 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4
1186 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16
1187 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4
1188 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */
1189 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */
1191 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */
1192 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12
1193 /* MC_CMD_FC_IN_CMD_OFST 0 */
1194 /* MC_CMD_FC_IN_CMD_LEN 4 */
1195 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4
1196 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4
1197 /* Sub-opcode describing the operation to be carried out */
1198 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8
1199 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4
1200 /* enum: Set a known datapath configuration */
1201 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0
1202 /* enum: Apply raw config to datapath control registers */
1203 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1
1205 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */
1206 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16
1207 /* MC_CMD_FC_IN_CMD_OFST 0 */
1208 /* MC_CMD_FC_IN_CMD_LEN 4 */
1209 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4
1210 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4
1211 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8
1212 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4
1213 /* Datapath configuration identifier */
1214 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12
1215 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4
1216 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */
1217 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */
1219 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */
1220 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24
1221 /* MC_CMD_FC_IN_CMD_OFST 0 */
1222 /* MC_CMD_FC_IN_CMD_LEN 4 */
1223 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4
1224 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4
1225 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8
1226 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4
1227 /* Value to write into control register 1 */
1228 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12
1229 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4
1230 /* Value to write into control register 2 */
1231 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16
1232 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4
1233 /* Value to write into control register 3 */
1234 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20
1235 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4
1237 /* MC_CMD_FC_OUT msgresponse */
1238 #define MC_CMD_FC_OUT_LEN 0
1240 /* MC_CMD_FC_OUT_NULL msgresponse */
1241 #define MC_CMD_FC_OUT_NULL_LEN 0
1243 /* MC_CMD_FC_OUT_READ32 msgresponse */
1244 #define MC_CMD_FC_OUT_READ32_LENMIN 4
1245 #define MC_CMD_FC_OUT_READ32_LENMAX 252
1246 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))
1247 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0
1248 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4
1249 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1
1250 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63
1252 /* MC_CMD_FC_OUT_WRITE32 msgresponse */
1253 #define MC_CMD_FC_OUT_WRITE32_LEN 0
1255 /* MC_CMD_FC_OUT_TRC_READ msgresponse */
1256 #define MC_CMD_FC_OUT_TRC_READ_LEN 16
1257 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0
1258 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4
1259 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4
1261 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */
1262 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0
1264 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */
1265 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12
1266 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0
1267 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4
1268 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4
1269 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8
1270 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4
1271 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8
1273 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */
1274 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8
1275 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0
1276 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4
1277 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2
1279 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */
1280 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0
1282 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */
1283 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0
1285 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */
1286 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0
1288 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */
1289 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4
1290 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0
1291 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4
1293 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */
1294 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3)
1295 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0
1296 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8
1297 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
1298 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
1299 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
1300 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
1301 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
1302 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */
1303 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
1304 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */
1305 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */
1306 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */
1307 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */
1308 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */
1309 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */
1310 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */
1311 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */
1312 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */
1313 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */
1314 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */
1315 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */
1316 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */
1317 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */
1318 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */
1319 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */
1320 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */
1321 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */
1322 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */
1323 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */
1324 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */
1325 /* enum: (Last entry) */
1326 #define MC_CMD_FC_MAC_RX_NSTATS 0x19
1328 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */
1329 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)
1330 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0
1331 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8
1332 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
1333 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
1334 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
1335 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
1336 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
1337 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */
1338 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
1339 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */
1340 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */
1341 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */
1342 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */
1343 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */
1344 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */
1345 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */
1346 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */
1347 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */
1348 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */
1349 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */
1350 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */
1351 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */
1352 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */
1353 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */
1354 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */
1355 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */
1356 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */
1357 /* enum: (Last entry) */
1358 #define MC_CMD_FC_MAC_TX_NSTATS 0x16
1360 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */
1361 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)
1362 /* MAC Statistics */
1363 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
1364 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
1365 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
1366 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4
1367 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK
1369 /* MC_CMD_FC_OUT_MAC msgresponse */
1370 #define MC_CMD_FC_OUT_MAC_LEN 0
1372 /* MC_CMD_FC_OUT_SFP msgresponse */
1373 #define MC_CMD_FC_OUT_SFP_LEN 0
1375 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */
1376 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0
1378 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */
1379 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8
1380 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0
1381 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4
1382 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0
1383 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8
1384 /* enum: Test not yet initiated */
1385 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0
1386 /* enum: Test is in progress */
1387 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1
1388 /* enum: Timed completed */
1389 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2
1390 /* enum: Test did not complete in specified time */
1391 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3
1392 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11
1393 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1
1394 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10
1395 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1
1396 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9
1397 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1
1398 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8
1399 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1
1400 /* Test result from FPGA */
1401 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4
1402 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4
1403 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31
1404 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1
1405 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30
1406 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1
1407 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29
1408 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1
1409 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28
1410 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1
1411 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15
1412 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5
1413 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10
1414 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5
1415 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5
1416 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5
1417 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0
1418 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5
1419 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */
1420 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */
1421 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */
1422 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */
1423 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */
1425 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */
1426 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0
1428 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */
1429 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144
1430 /* Assertion status flag. */
1431 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0
1432 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4
1433 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8
1434 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8
1435 /* enum: No crash data available */
1436 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0
1437 /* enum: New crash data available */
1438 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1
1439 /* enum: Crash data has been sent */
1440 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2
1441 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0
1442 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8
1443 /* enum: No crash has been recorded. */
1444 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0
1445 /* enum: Crash due to exception. */
1446 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1
1447 /* enum: Crash due to assertion. */
1448 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2
1449 /* Failing PC value */
1450 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4
1451 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4
1453 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8
1454 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4
1455 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31
1456 /* Exception Type */
1457 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132
1458 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4
1459 /* Instruction at which exception occurred */
1460 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136
1461 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4
1462 /* BAD Address that triggered address-based exception */
1463 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140
1464 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4
1466 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */
1467 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32
1468 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0
1469 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4
1470 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31
1471 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1
1472 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30
1473 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1
1474 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16
1475 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14
1476 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12
1477 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4
1478 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4
1479 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8
1480 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0
1481 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4
1482 /* Build timestamp (seconds since epoch) */
1483 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4
1484 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4
1485 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8
1486 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4
1487 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0
1488 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8
1489 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */
1490 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */
1491 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8
1492 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10
1493 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18
1494 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1
1495 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19
1496 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1
1497 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20
1498 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1
1499 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21
1500 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1
1501 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22
1502 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1
1503 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23
1504 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1
1505 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24
1506 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1
1507 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25
1508 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1
1509 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26
1510 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1
1511 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27
1512 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1
1513 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28
1514 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1
1515 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29
1516 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2
1517 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31
1518 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1
1519 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12
1520 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4
1521 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0
1522 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16
1523 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16
1524 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1
1525 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */
1526 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */
1527 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17
1528 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15
1529 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16
1530 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4
1531 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0
1532 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16
1533 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16
1534 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
1535 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20
1536 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4
1537 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0
1538 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16
1539 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16
1540 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16
1541 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16
1542 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8
1543 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16
1544 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20
1545 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24
1546 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4
1547 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28
1548 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4
1549 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0
1550 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16
1552 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */
1553 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32
1554 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0
1555 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4
1556 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31
1557 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1
1558 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30
1559 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1
1560 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16
1561 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14
1562 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12
1563 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4
1564 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4
1565 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8
1566 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0
1567 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4
1568 /* Build timestamp (seconds since epoch) */
1569 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4
1570 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4
1571 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8
1572 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4
1573 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31
1574 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1
1575 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29
1576 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1
1577 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28
1578 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1
1579 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27
1580 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1
1581 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26
1582 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1
1583 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25
1584 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1
1585 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24
1586 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1
1587 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23
1588 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1
1589 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22
1590 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1
1591 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21
1592 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1
1593 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20
1594 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1
1595 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19
1596 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1
1597 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18
1598 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1
1599 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */
1600 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */
1601 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17
1602 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1
1603 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */
1604 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */
1605 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16
1606 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1
1607 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */
1608 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */
1609 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15
1610 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1
1611 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14
1612 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1
1613 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13
1614 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1
1615 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12
1616 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1
1617 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11
1618 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1
1619 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10
1620 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1
1621 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9
1622 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1
1623 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8
1624 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1
1625 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7
1626 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1
1627 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6
1628 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1
1629 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5
1630 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1
1631 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4
1632 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1
1633 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0
1634 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4
1635 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */
1636 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */
1637 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */
1638 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */
1639 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */
1640 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */
1641 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */
1642 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */
1643 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12
1644 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4
1645 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0
1646 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16
1647 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16
1648 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1
1649 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */
1650 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */
1651 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16
1652 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4
1653 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0
1654 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16
1655 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16
1656 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
1657 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20
1658 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4
1659 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0
1660 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16
1661 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16
1662 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16
1663 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24
1664 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4
1665 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28
1666 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4
1667 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0
1668 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16
1670 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */
1671 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32
1672 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0
1673 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4
1674 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31
1675 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1
1676 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30
1677 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1
1678 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16
1679 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14
1680 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12
1681 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4
1682 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4
1683 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8
1684 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0
1685 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4
1686 /* Build timestamp (seconds since epoch) */
1687 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4
1688 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4
1689 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8
1690 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4
1691 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8
1692 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1
1693 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27
1694 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1
1695 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28
1696 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1
1697 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29
1698 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1
1699 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30
1700 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1
1701 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31
1702 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1
1703 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12
1704 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4
1705 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0
1706 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16
1707 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16
1708 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1
1709 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16
1710 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4
1711 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0
1712 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16
1713 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16
1714 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16
1715 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20
1716 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4
1717 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0
1718 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16
1719 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16
1720 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16
1721 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24
1722 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4
1723 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28
1724 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4
1725 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0
1726 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16
1728 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */
1729 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32
1730 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0
1731 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4
1732 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31
1733 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1
1734 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30
1735 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1
1736 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16
1737 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14
1738 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12
1739 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4
1740 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4
1741 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8
1742 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0
1743 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4
1744 /* Build timestamp (seconds since epoch) */
1745 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4
1746 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4
1747 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8
1748 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4
1749 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0
1750 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1
1751 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8
1752 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1
1753 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12
1754 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4
1755 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0
1756 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16
1757 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16
1758 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1
1759 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */
1760 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */
1761 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24
1762 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4
1763 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28
1764 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4
1765 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0
1766 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16
1768 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */
1769 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4
1770 /* Qsys system ID */
1771 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0
1772 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4
1773 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12
1774 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4
1775 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4
1776 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8
1777 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0
1778 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4
1780 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */
1781 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4
1782 /* Number of maps */
1783 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0
1784 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4
1786 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */
1787 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164
1788 /* Index of the map */
1789 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0
1790 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4
1791 /* Options for the map */
1792 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4
1793 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4
1794 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */
1795 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */
1796 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */
1797 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */
1798 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */
1799 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */
1800 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */
1801 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */
1802 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */
1803 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */
1804 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */
1805 /* Address of start of map */
1806 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
1807 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
1808 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
1809 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
1810 /* Length of address map */
1811 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
1812 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
1813 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
1814 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
1815 /* Component information field */
1816 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
1817 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4
1818 /* License expiry data for map */
1819 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
1820 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
1821 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
1822 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
1823 /* Name of the component */
1824 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
1825 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
1826 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128
1828 /* MC_CMD_FC_OUT_READ_MAP msgresponse */
1829 #define MC_CMD_FC_OUT_READ_MAP_LEN 0
1831 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */
1832 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8
1833 /* Number of internal ports */
1834 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0
1835 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4
1836 /* Number of external ports */
1837 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4
1838 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4
1840 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */
1841 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4
1842 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0
1843 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4
1845 /* MC_CMD_FC_OUT_IO_REL msgresponse */
1846 #define MC_CMD_FC_OUT_IO_REL_LEN 0
1848 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */
1849 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8
1850 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0
1851 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4
1852 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4
1853 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4
1855 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */
1856 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4
1857 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252
1858 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))
1859 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0
1860 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4
1861 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1
1862 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63
1864 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */
1865 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0
1867 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */
1868 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48
1869 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0
1870 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4
1871 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0
1872 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16
1873 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16
1874 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16
1875 /* Transceiver Transmit settings */
1876 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4
1877 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4
1878 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0
1879 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16
1880 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16
1881 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16
1882 /* Transceiver Receive settings */
1883 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8
1884 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4
1885 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0
1886 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16
1887 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16
1888 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16
1889 /* Rx eye opening */
1890 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12
1891 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4
1892 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0
1893 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16
1894 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16
1895 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16
1896 /* PCS status word */
1897 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16
1898 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4
1899 /* Link status word */
1900 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20
1901 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4
1902 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0
1903 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1
1904 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1
1905 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1
1906 /* Current SFp parameters applied */
1907 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24
1908 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20
1909 /* Link speed is 100, 1000, 10000 */
1910 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24
1911 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4
1912 /* Length of copper cable - zero when not relevant */
1913 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28
1914 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4
1915 /* True if a dual speed SFP+ module */
1916 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32
1917 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4
1918 /* True if an SFP Module is present (other fields valid when true) */
1919 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36
1920 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4
1921 /* The type of the SFP+ Module */
1922 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40
1923 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4
1924 /* PHY config flags */
1925 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44
1926 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4
1927 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0
1928 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1
1929 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1
1930 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1
1931 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2
1932 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1
1934 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */
1935 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20
1936 /* MAC configuration applied */
1937 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0
1938 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4
1940 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4
1941 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4
1942 /* IF Mode status */
1943 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8
1944 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4
1945 /* MAC address configured */
1946 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
1947 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
1948 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
1949 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16
1951 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
1952 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
1953 /* Rx Eye measurements */
1954 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0
1955 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4
1956 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK
1958 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */
1959 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0
1961 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */
1962 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3)
1963 /* Has the eye plot dump completed and data returned is valid? */
1964 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0
1965 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4
1966 /* Rx Eye binary plot */
1967 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
1968 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
1969 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
1970 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8
1971 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK
1973 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */
1974 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0
1976 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */
1977 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0
1979 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */
1980 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4
1981 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0
1982 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4
1984 /* MC_CMD_FC_OUT_UHLINK msgresponse */
1985 #define MC_CMD_FC_OUT_UHLINK_LEN 0
1987 /* MC_CMD_FC_OUT_SET_LINK msgresponse */
1988 #define MC_CMD_FC_OUT_SET_LINK_LEN 0
1990 /* MC_CMD_FC_OUT_LICENSE msgresponse */
1991 #define MC_CMD_FC_OUT_LICENSE_LEN 12
1992 /* Count of valid keys */
1993 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0
1994 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4
1995 /* Count of invalid keys */
1996 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4
1997 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4
1998 /* Count of blacklisted keys */
1999 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8
2000 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4
2002 /* MC_CMD_FC_OUT_STARTUP msgresponse */
2003 #define MC_CMD_FC_OUT_STARTUP_LEN 4
2004 /* Capabilities of the FPGA/FC */
2005 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0
2006 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4
2007 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0
2008 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1
2010 /* MC_CMD_FC_OUT_DMA_READ msgresponse */
2011 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1
2012 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252
2013 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))
2015 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0
2016 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1
2017 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1
2018 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252
2020 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */
2021 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4
2023 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0
2024 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4
2026 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */
2027 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52
2028 /* Host supplied handle (unique) */
2029 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0
2030 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4
2031 /* Address into which to transfer data in host */
2032 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
2033 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
2034 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
2035 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
2036 /* AOE address from which to transfer data */
2037 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
2038 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
2039 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
2040 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
2041 /* Length of AOE transfer (total) */
2042 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
2043 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4
2044 /* Length of host transfer (total) */
2045 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24
2046 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4
2047 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */
2048 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28
2049 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4
2050 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32
2051 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4
2052 /* When active, start read time */
2053 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
2054 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
2055 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
2056 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
2057 /* When active, end read time */
2058 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
2059 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
2060 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
2061 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48
2063 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */
2064 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0
2066 /* MC_CMD_FC_OUT_LOG msgresponse */
2067 #define MC_CMD_FC_OUT_LOG_LEN 0
2069 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */
2070 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24
2071 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0
2072 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4
2073 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4
2074 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8
2075 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4
2076 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8
2077 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12
2078 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4
2079 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16
2080 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4
2081 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20
2082 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4
2084 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */
2085 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0
2087 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */
2088 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0
2090 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */
2091 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0
2093 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */
2094 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4
2095 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0
2096 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4
2097 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0
2098 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1
2099 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1
2100 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1
2102 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */
2103 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8
2104 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0
2105 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4
2106 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4
2107 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4
2109 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */
2110 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8
2111 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248
2112 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))
2113 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0
2114 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4
2115 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4
2116 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4
2117 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0
2118 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8
2119 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0
2120 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
2121 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
2122 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
2124 /* MC_CMD_FC_OUT_SPI_READ msgresponse */
2125 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4
2126 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252
2127 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))
2128 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0
2129 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4
2130 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1
2131 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63
2133 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */
2134 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0
2136 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */
2137 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0
2139 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */
2140 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8
2141 /* The 32-bit value read from the toggle count register */
2142 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0
2143 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4
2144 /* The 32-bit value read from the clock enable count register */
2145 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4
2146 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4
2148 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */
2149 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0
2151 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */
2152 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0
2154 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */
2155 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8
2156 /* DDR soak test status word; bits [4:0] are relevant. */
2157 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0
2158 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4
2159 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0
2160 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1
2161 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1
2162 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1
2163 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2
2164 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1
2165 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3
2166 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1
2167 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4
2168 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1
2169 /* DDR soak test error count */
2170 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4
2171 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4
2173 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */
2174 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0
2176 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */
2177 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0
2179 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */
2180 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0
2182 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */
2183 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0
2186 /***********************************/
2188 * AOE operations on MC
2190 #define MC_CMD_AOE 0xa
2192 /* MC_CMD_AOE_IN msgrequest */
2193 #define MC_CMD_AOE_IN_LEN 4
2194 #define MC_CMD_AOE_IN_OP_HDR_OFST 0
2195 #define MC_CMD_AOE_IN_OP_HDR_LEN 4
2196 #define MC_CMD_AOE_IN_OP_LBN 0
2197 #define MC_CMD_AOE_IN_OP_WIDTH 8
2198 /* enum: FPGA and CPLD information */
2199 #define MC_CMD_AOE_OP_INFO 0x1
2200 /* enum: Currents and voltages read from MCP3424s; DEBUG */
2201 #define MC_CMD_AOE_OP_CURRENTS 0x2
2202 /* enum: Temperatures at locations around the PCB; DEBUG */
2203 #define MC_CMD_AOE_OP_TEMPERATURES 0x3
2204 /* enum: Set CPLD to idle */
2205 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4
2206 /* enum: Read from CPLD register */
2207 #define MC_CMD_AOE_OP_CPLD_READ 0x5
2208 /* enum: Write to CPLD register */
2209 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6
2210 /* enum: Execute CPLD instruction */
2211 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7
2212 /* enum: Reprogram the CPLD on the AOE device */
2213 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8
2214 /* enum: AOE power control */
2215 #define MC_CMD_AOE_OP_POWER 0x9
2216 /* enum: AOE image loading */
2217 #define MC_CMD_AOE_OP_LOAD 0xa
2218 /* enum: Fan monitoring */
2219 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb
2220 /* enum: Fan failures since last reset */
2221 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc
2222 /* enum: Get generic AOE MAC statistics */
2223 #define MC_CMD_AOE_OP_MAC_STATS 0xd
2224 /* enum: Retrieve PHY specific information */
2225 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe
2226 /* enum: Write a number of JTAG primitive commands, return will give data */
2227 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf
2228 /* enum: Control access to the FPGA via the Siena JTAG Chain */
2229 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10
2230 /* enum: Set the MTU offset between Siena and AOE MACs */
2231 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11
2232 /* enum: How link state is handled */
2233 #define MC_CMD_AOE_OP_LINK_STATE 0x12
2234 /* enum: How Siena MAC statistics are reported (deprecated - use
2235 * MC_CMD_AOE_OP_ASIC_STATS)
2237 #define MC_CMD_AOE_OP_SIENA_STATS 0x13
2238 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated
2239 * command MC_CMD_AOE_OP_SIENA_STATS
2241 #define MC_CMD_AOE_OP_ASIC_STATS 0x13
2242 /* enum: DDR memory information */
2243 #define MC_CMD_AOE_OP_DDR 0x14
2244 /* enum: FC control */
2245 #define MC_CMD_AOE_OP_FC 0x15
2246 /* enum: DDR ECC status reads */
2247 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16
2248 /* enum: Commands for MC-SPI Master emulation */
2249 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17
2250 /* enum: Commands for FC boot control */
2251 #define MC_CMD_AOE_OP_FC_BOOT 0x18
2252 /* enum: Get number of internal ports */
2253 #define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19
2254 /* enum: Get FC assert information and register dump */
2255 #define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a
2257 /* MC_CMD_AOE_OUT msgresponse */
2258 #define MC_CMD_AOE_OUT_LEN 0
2260 /* MC_CMD_AOE_IN_INFO msgrequest */
2261 #define MC_CMD_AOE_IN_INFO_LEN 4
2262 #define MC_CMD_AOE_IN_CMD_OFST 0
2263 #define MC_CMD_AOE_IN_CMD_LEN 4
2265 /* MC_CMD_AOE_IN_CURRENTS msgrequest */
2266 #define MC_CMD_AOE_IN_CURRENTS_LEN 4
2267 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2268 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2270 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */
2271 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4
2272 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2273 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2275 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */
2276 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4
2277 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2278 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2280 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */
2281 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12
2282 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2283 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2284 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4
2285 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4
2286 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8
2287 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4
2289 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */
2290 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16
2291 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2292 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2293 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4
2294 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4
2295 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8
2296 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4
2297 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12
2298 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4
2300 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */
2301 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8
2302 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2303 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2304 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4
2305 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4
2307 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */
2308 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8
2309 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2310 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2311 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4
2312 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4
2313 /* enum: Reprogram CPLD, poll for completion */
2314 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1
2315 /* enum: Reprogram CPLD, send event on completion */
2316 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3
2317 /* enum: Get status of reprogramming operation */
2318 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4
2320 /* MC_CMD_AOE_IN_POWER msgrequest */
2321 #define MC_CMD_AOE_IN_POWER_LEN 8
2322 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2323 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2324 /* Turn on or off AOE power */
2325 #define MC_CMD_AOE_IN_POWER_OP_OFST 4
2326 #define MC_CMD_AOE_IN_POWER_OP_LEN 4
2327 /* enum: Turn off FPGA power */
2328 #define MC_CMD_AOE_IN_POWER_OFF 0x0
2329 /* enum: Turn on FPGA power */
2330 #define MC_CMD_AOE_IN_POWER_ON 0x1
2331 /* enum: Clear peak power measurement */
2332 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2
2333 /* enum: Show current power in sensors output */
2334 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3
2335 /* enum: Show peak power in sensors output */
2336 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4
2337 /* enum: Show current DDR current */
2338 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5
2339 /* enum: Show peak DDR current */
2340 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6
2341 /* enum: Clear peak DDR current */
2342 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7
2344 /* MC_CMD_AOE_IN_LOAD msgrequest */
2345 #define MC_CMD_AOE_IN_LOAD_LEN 8
2346 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2347 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2348 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence
2350 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4
2351 #define MC_CMD_AOE_IN_LOAD_IMAGE_LEN 4
2353 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */
2354 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8
2355 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2356 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2357 /* If non zero report measured fan RPM rather than nominal */
2358 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4
2359 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4
2361 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */
2362 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4
2363 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2364 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2366 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */
2367 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24
2368 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2369 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2371 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4
2372 #define MC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4
2373 /* Host memory address for statistics */
2374 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
2375 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
2376 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
2377 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12
2378 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16
2379 #define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4
2380 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0
2381 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1
2382 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1
2383 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1
2384 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2
2385 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1
2386 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3
2387 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1
2388 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4
2389 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1
2390 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5
2391 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1
2392 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16
2393 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16
2394 /* Length of DMA data (optional) */
2395 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20
2396 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4
2398 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */
2399 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12
2400 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2401 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2403 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4
2404 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4
2405 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8
2406 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4
2408 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */
2409 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12
2410 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252
2411 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))
2412 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2413 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2414 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4
2415 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4
2416 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8
2417 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4
2418 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1
2419 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61
2421 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */
2422 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8
2423 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2424 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2425 /* Enable or disable access */
2426 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4
2427 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4
2428 /* enum: Enable access */
2429 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1
2430 /* enum: Disable access */
2431 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2
2433 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */
2434 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12
2435 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2436 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2437 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */
2438 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4
2439 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4
2440 /* enum: Apply to all external ports */
2441 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000
2442 /* enum: Apply to all internal ports */
2443 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000
2444 /* The MTU offset to be applied to the external ports */
2445 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8
2446 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4
2448 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */
2449 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8
2450 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2451 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2452 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4
2453 #define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4
2454 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0
2455 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8
2456 /* enum: AOE and associated external port */
2457 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0
2458 /* enum: AOE and OR of all external ports */
2459 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1
2460 /* enum: Individual ports */
2461 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2
2462 /* enum: Configure link state mode on given AOE port */
2463 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3
2464 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8
2465 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8
2467 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0
2468 /* enum: logical OR of all SFP ports link status */
2469 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1
2470 /* enum: logical AND of all SFP ports link status */
2471 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2
2472 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16
2473 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16
2475 /* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */
2476 #define MC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4
2477 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2478 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2480 /* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */
2481 #define MC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4
2482 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2483 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2485 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */
2486 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8
2487 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2488 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2489 /* How MAC statistics are reported */
2490 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4
2491 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4
2492 /* enum: Statistics from Siena (default) */
2493 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0
2494 /* enum: Statistics from AOE external ports */
2495 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1
2497 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */
2498 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8
2499 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2500 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2501 /* How MAC statistics are reported */
2502 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4
2503 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4
2504 /* enum: Statistics from the ASIC (default) */
2505 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0
2506 /* enum: Statistics from AOE external ports */
2507 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1
2509 /* MC_CMD_AOE_IN_DDR msgrequest */
2510 #define MC_CMD_AOE_IN_DDR_LEN 12
2511 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2512 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2513 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4
2514 #define MC_CMD_AOE_IN_DDR_BANK_LEN 4
2515 /* Enum values, see field(s): */
2516 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */
2517 /* Page index of SPD data */
2518 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8
2519 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4
2521 /* MC_CMD_AOE_IN_FC msgrequest */
2522 #define MC_CMD_AOE_IN_FC_LEN 4
2523 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2524 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2526 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */
2527 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8
2528 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2529 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2530 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4
2531 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4
2532 /* Enum values, see field(s): */
2533 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */
2535 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */
2536 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8
2537 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2538 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2539 /* Basic commands for MC SPI Master emulation. */
2540 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4
2541 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4
2542 /* enum: MC SPI read */
2543 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0
2544 /* enum: MC SPI write */
2545 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1
2547 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */
2548 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12
2549 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2550 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2551 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4
2552 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4
2553 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8
2554 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4
2556 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */
2557 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16
2558 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2559 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2560 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4
2561 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4
2562 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8
2563 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4
2564 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12
2565 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4
2567 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */
2568 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8
2569 /* MC_CMD_AOE_IN_CMD_OFST 0 */
2570 /* MC_CMD_AOE_IN_CMD_LEN 4 */
2571 /* FC boot control flags */
2572 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4
2573 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4
2574 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0
2575 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1
2577 /* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */
2578 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144
2579 /* Assertion status flag. */
2580 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0
2581 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4
2582 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8
2583 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8
2584 /* enum: No crash data available */
2585 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */
2586 /* enum: New crash data available */
2587 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */
2588 /* enum: Crash data has been sent */
2589 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */
2590 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0
2591 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8
2592 /* enum: No crash has been recorded. */
2593 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */
2594 /* enum: Crash due to exception. */
2595 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */
2596 /* enum: Crash due to assertion. */
2597 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */
2598 /* Failing PC value */
2599 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4
2600 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4
2602 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8
2603 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4
2604 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31
2605 /* Exception Type */
2606 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132
2607 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4
2608 /* Instruction at which exception occurred */
2609 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136
2610 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4
2611 /* BAD Address that triggered address-based exception */
2612 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140
2613 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4
2615 /* MC_CMD_AOE_OUT_INFO msgresponse */
2616 #define MC_CMD_AOE_OUT_INFO_LEN 44
2617 /* JTAG IDCODE of CPLD */
2618 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0
2619 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4
2620 /* Version of CPLD */
2621 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4
2622 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4
2623 /* JTAG IDCODE of FPGA */
2624 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8
2625 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4
2626 /* JTAG USERCODE of FPGA */
2627 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12
2628 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4
2629 /* FPGA type - read from CPLD straps */
2630 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16
2631 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4
2632 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */
2633 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */
2634 /* FPGA state (debug) */
2635 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20
2636 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4
2637 /* FPGA image - partition from which loaded */
2638 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24
2639 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4
2641 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28
2642 #define MC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4
2643 /* enum: Set if watchdog working */
2644 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1
2645 /* enum: Set if MC-FC communications working */
2646 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2
2647 /* Random pieces of information */
2648 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32
2649 #define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4
2650 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */
2651 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1
2652 /* enum: CPLD apparently good */
2653 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2
2654 /* enum: FPGA working normally */
2655 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4
2656 /* enum: FPGA is powered */
2657 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8
2658 /* enum: Board has incompatible SODIMMs fitted */
2659 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10
2660 /* enum: Board has ByteBlaster connected */
2661 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20
2662 /* enum: FPGA Boot flash has an invalid header. */
2663 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40
2664 /* enum: FPGA Application flash is accessible. */
2665 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80
2666 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */
2667 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36
2668 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4
2669 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */
2670 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */
2671 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */
2672 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */
2673 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */
2674 /* Result of FC booting - not valid while a ByteBlaster is connected. */
2675 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40
2676 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4
2677 /* enum: No error */
2678 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0
2679 /* enum: Bad address set in CPLD */
2680 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1
2681 /* enum: Bad header */
2682 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2
2683 /* enum: Bad text section details */
2684 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3
2685 /* enum: Bad checksum */
2686 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4
2688 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5
2689 /* enum: Flash mode is invalid */
2690 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6
2691 /* enum: FC application loaded and execution attempted */
2692 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80
2693 /* enum: FC application Started */
2694 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81
2695 /* enum: No bootrom in FPGA */
2696 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff
2698 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */
2699 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68
2700 /* Set of currents and voltages (mA or mV as appropriate) */
2701 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0
2702 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4
2703 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17
2704 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */
2705 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */
2706 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */
2707 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */
2708 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */
2709 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */
2710 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */
2711 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */
2712 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */
2713 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */
2714 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */
2715 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */
2716 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */
2717 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */
2718 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */
2719 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */
2720 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */
2722 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */
2723 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40
2724 /* Set of temperatures */
2725 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0
2726 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4
2727 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10
2728 /* enum: The first set of enum values are for Modena code. */
2729 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0
2730 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */
2731 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */
2732 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */
2733 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */
2734 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */
2735 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */
2736 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */
2737 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */
2738 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */
2739 /* enum: The second set of enum values are for Sorrento code. */
2740 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0
2741 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */
2742 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */
2743 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */
2744 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */
2745 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */
2746 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */
2747 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */
2748 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */
2750 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */
2751 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4
2752 /* The value read from the CPLD */
2753 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0
2754 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4
2756 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */
2757 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4
2758 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252
2759 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))
2760 /* Failure counts for each fan */
2761 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0
2762 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4
2763 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1
2764 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63
2766 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */
2767 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4
2768 /* Results of status command (only) */
2769 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0
2770 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4
2772 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */
2773 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0
2775 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */
2776 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0
2778 /* MC_CMD_AOE_OUT_LOAD msgresponse */
2779 #define MC_CMD_AOE_OUT_LOAD_LEN 0
2781 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */
2782 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0
2784 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA
2787 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
2788 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
2789 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
2790 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0
2791 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4
2792 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
2794 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
2795 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5
2796 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252
2797 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))
2799 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0
2800 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4
2801 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4
2802 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1
2803 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1
2804 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248
2806 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */
2807 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12
2808 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252
2809 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))
2810 /* Used to align the in and out data blocks so the MC can re-use the cmd */
2811 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0
2812 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4
2814 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4
2815 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4
2816 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8
2817 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4
2818 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1
2819 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61
2821 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */
2822 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0
2824 /* MC_CMD_AOE_OUT_DDR msgresponse */
2825 #define MC_CMD_AOE_OUT_DDR_LENMIN 17
2826 #define MC_CMD_AOE_OUT_DDR_LENMAX 252
2827 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))
2828 /* Information on the module. */
2829 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0
2830 #define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4
2831 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0
2832 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1
2833 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1
2834 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1
2835 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2
2836 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1
2837 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3
2838 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1
2839 /* Memory size, in MB. */
2840 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4
2841 #define MC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4
2842 /* The memory type, as reported from SPD information */
2843 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8
2844 #define MC_CMD_AOE_OUT_DDR_TYPE_LEN 4
2845 /* Nominal voltage of the module (as applied) */
2846 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12
2847 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4
2848 /* SPD data read from the module */
2849 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16
2850 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1
2851 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1
2852 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236
2854 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */
2855 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0
2857 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */
2858 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0
2860 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */
2861 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0
2863 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */
2864 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0
2866 /* MC_CMD_AOE_OUT_FC msgresponse */
2867 #define MC_CMD_AOE_OUT_FC_LEN 0
2869 /* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */
2870 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4
2871 /* get the number of internal ports */
2872 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0
2873 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4
2875 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */
2876 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8
2877 /* Flags describing status info on the module. */
2878 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0
2879 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4
2880 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0
2881 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1
2882 /* DDR ECC status on the module. */
2883 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4
2884 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4
2885 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0
2886 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1
2887 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1
2888 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1
2889 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2
2890 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1
2891 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8
2892 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8
2893 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16
2894 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8
2895 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24
2896 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8
2898 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */
2899 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4
2900 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0
2901 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4
2903 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */
2904 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0
2906 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */
2907 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0
2909 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */
2910 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0
2912 #endif /* _SIENA_MC_DRIVER_PCOL_AOE_H */
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